York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 1 | config ARCH_LS1012A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 2 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 3 | select ARMV8_SET_SMPEN |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 4 | select FSL_LSCH2 |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 5 | select SYS_FSL_DDR_BE |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 6 | select SYS_FSL_MMDC |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 7 | select SYS_FSL_ERRATUM_A010315 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 8 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 9 | select BOARD_EARLY_INIT_F |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 10 | |
| 11 | config ARCH_LS1043A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 12 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 13 | select ARMV8_SET_SMPEN |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 14 | select FSL_LSCH2 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 15 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 16 | select SYS_FSL_DDR_BE |
| 17 | select SYS_FSL_DDR_VER_50 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 18 | select SYS_FSL_ERRATUM_A008850 |
| 19 | select SYS_FSL_ERRATUM_A009660 |
| 20 | select SYS_FSL_ERRATUM_A009663 |
| 21 | select SYS_FSL_ERRATUM_A009929 |
| 22 | select SYS_FSL_ERRATUM_A009942 |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 23 | select SYS_FSL_ERRATUM_A010315 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 24 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 25 | select SYS_FSL_HAS_DDR3 |
| 26 | select SYS_FSL_HAS_DDR4 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 27 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 28 | select BOARD_EARLY_INIT_F |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 29 | |
York Sun | bad4984 | 2016-09-26 08:09:24 -0700 | [diff] [blame] | 30 | config ARCH_LS1046A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 31 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 32 | select ARMV8_SET_SMPEN |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 33 | select FSL_LSCH2 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 34 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 35 | select SYS_FSL_DDR_BE |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 36 | select SYS_FSL_DDR_VER_50 |
York Sun | f195cf7 | 2017-01-27 09:57:31 -0800 | [diff] [blame] | 37 | select SYS_FSL_ERRATUM_A008336 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 38 | select SYS_FSL_ERRATUM_A008511 |
| 39 | select SYS_FSL_ERRATUM_A009801 |
| 40 | select SYS_FSL_ERRATUM_A009803 |
| 41 | select SYS_FSL_ERRATUM_A009942 |
| 42 | select SYS_FSL_ERRATUM_A010165 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 43 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 44 | select SYS_FSL_HAS_DDR4 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 45 | select SYS_FSL_SRDS_2 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 46 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 47 | select BOARD_EARLY_INIT_F |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 48 | |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 49 | config ARCH_LS2080A |
| 50 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 51 | select ARMV8_SET_SMPEN |
Tom Rini | bacb52c | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 52 | select ARM_ERRATA_826974 |
| 53 | select ARM_ERRATA_828024 |
| 54 | select ARM_ERRATA_829520 |
| 55 | select ARM_ERRATA_833471 |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 56 | select FSL_LSCH3 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 57 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 58 | select SYS_FSL_DDR_LE |
| 59 | select SYS_FSL_DDR_VER_50 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 60 | select SYS_FSL_HAS_DP_DDR |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 61 | select SYS_FSL_HAS_SEC |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 62 | select SYS_FSL_HAS_DDR4 |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 63 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 64 | select SYS_FSL_SEC_LE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 65 | select SYS_FSL_SRDS_2 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 66 | select SYS_FSL_ERRATUM_A008336 |
| 67 | select SYS_FSL_ERRATUM_A008511 |
| 68 | select SYS_FSL_ERRATUM_A008514 |
| 69 | select SYS_FSL_ERRATUM_A008585 |
| 70 | select SYS_FSL_ERRATUM_A009635 |
| 71 | select SYS_FSL_ERRATUM_A009663 |
| 72 | select SYS_FSL_ERRATUM_A009801 |
| 73 | select SYS_FSL_ERRATUM_A009803 |
| 74 | select SYS_FSL_ERRATUM_A009942 |
| 75 | select SYS_FSL_ERRATUM_A010165 |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 76 | select SYS_FSL_ERRATUM_A009203 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 77 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 78 | select BOARD_EARLY_INIT_F |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 79 | |
| 80 | config FSL_LSCH2 |
| 81 | bool |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 82 | select SYS_FSL_HAS_SEC |
| 83 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 84 | select SYS_FSL_SEC_BE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 85 | select SYS_FSL_SRDS_1 |
| 86 | select SYS_HAS_SERDES |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 87 | |
| 88 | config FSL_LSCH3 |
| 89 | bool |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 90 | select SYS_FSL_SRDS_1 |
| 91 | select SYS_HAS_SERDES |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 92 | |
York Sun | 6c08974 | 2017-03-06 09:02:25 -0800 | [diff] [blame] | 93 | config FSL_MC_ENET |
| 94 | bool "Management Complex network" |
| 95 | depends on ARCH_LS2080A |
| 96 | default y |
| 97 | select RESV_RAM |
| 98 | help |
| 99 | Enable Management Complex (MC) network |
| 100 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 101 | menu "Layerscape architecture" |
| 102 | depends on FSL_LSCH2 || FSL_LSCH3 |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 103 | |
Hou Zhiqiang | d553bf2 | 2016-12-13 14:54:24 +0800 | [diff] [blame] | 104 | config FSL_PCIE_COMPAT |
| 105 | string "PCIe compatible of Kernel DT" |
| 106 | depends on PCIE_LAYERSCAPE |
| 107 | default "fsl,ls1012a-pcie" if ARCH_LS1012A |
| 108 | default "fsl,ls1043a-pcie" if ARCH_LS1043A |
| 109 | default "fsl,ls1046a-pcie" if ARCH_LS1046A |
| 110 | default "fsl,ls2080a-pcie" if ARCH_LS2080A |
| 111 | help |
| 112 | This compatible is used to find pci controller node in Kernel DT |
| 113 | to complete fixup. |
| 114 | |
Wenbin Song | a8f57a9 | 2017-01-17 18:31:15 +0800 | [diff] [blame] | 115 | config HAS_FEATURE_GIC64K_ALIGN |
| 116 | bool |
| 117 | default y if ARCH_LS1043A |
| 118 | |
Wenbin Song | c6bc7c0 | 2017-01-17 18:31:16 +0800 | [diff] [blame] | 119 | config HAS_FEATURE_ENHANCED_MSI |
| 120 | bool |
| 121 | default y if ARCH_LS1043A |
Wenbin Song | a8f57a9 | 2017-01-17 18:31:15 +0800 | [diff] [blame] | 122 | |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 123 | menu "Layerscape PPA" |
| 124 | config FSL_LS_PPA |
| 125 | bool "FSL Layerscape PPA firmware support" |
macro.wave.z@gmail.com | 01bd334 | 2016-12-08 11:58:22 +0800 | [diff] [blame] | 126 | depends on !ARMV8_PSCI |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 127 | select ARMV8_SEC_FIRMWARE_SUPPORT |
Hou Zhiqiang | 6be115d | 2017-01-16 17:31:48 +0800 | [diff] [blame] | 128 | select SEC_FIRMWARE_ARMV8_PSCI |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 129 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 130 | help |
| 131 | The FSL Primary Protected Application (PPA) is a software component |
| 132 | which is loaded during boot stage, and then remains resident in RAM |
| 133 | and runs in the TrustZone after boot. |
| 134 | Say y to enable it. |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 135 | choice |
| 136 | prompt "FSL Layerscape PPA firmware loading-media select" |
| 137 | depends on FSL_LS_PPA |
| 138 | default SYS_LS_PPA_FW_IN_XIP |
| 139 | |
| 140 | config SYS_LS_PPA_FW_IN_XIP |
| 141 | bool "XIP" |
| 142 | help |
| 143 | Say Y here if the PPA firmware locate at XIP flash, such |
| 144 | as NOR or QSPI flash. |
| 145 | |
| 146 | endchoice |
| 147 | |
| 148 | config SYS_LS_PPA_FW_ADDR |
| 149 | hex "Address of PPA firmware loading from" |
| 150 | depends on FSL_LS_PPA |
| 151 | default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT |
Santan Kumar | c61c699 | 2017-03-07 11:21:03 +0530 | [diff] [blame^] | 152 | default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 153 | default 0x60500000 if SYS_LS_PPA_FW_IN_XIP |
| 154 | help |
| 155 | If the PPA firmware locate at XIP flash, such as NOR or |
| 156 | QSPI flash, this address is a directly memory-mapped. |
| 157 | If it is in a serial accessed flash, such as NAND and SD |
| 158 | card, it is a byte offset. |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 159 | endmenu |
| 160 | |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 161 | config SYS_FSL_ERRATUM_A010315 |
| 162 | bool "Workaround for PCIe erratum A010315" |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 163 | |
| 164 | config SYS_FSL_ERRATUM_A010539 |
| 165 | bool "Workaround for PIN MUX erratum A010539" |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 166 | |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 167 | config MAX_CPUS |
| 168 | int "Maximum number of CPUs permitted for Layerscape" |
| 169 | default 4 if ARCH_LS1043A |
| 170 | default 4 if ARCH_LS1046A |
| 171 | default 16 if ARCH_LS2080A |
| 172 | default 1 |
| 173 | help |
| 174 | Set this number to the maximum number of possible CPUs in the SoC. |
| 175 | SoCs may have multiple clusters with each cluster may have multiple |
| 176 | ports. If some ports are reserved but higher ports are used for |
| 177 | cores, count the reserved ports. This will allocate enough memory |
| 178 | in spin table to properly handle all cores. |
| 179 | |
York Sun | 728e700 | 2016-12-02 09:32:35 -0800 | [diff] [blame] | 180 | config SECURE_BOOT |
York Sun | 8a3d8ed | 2017-01-04 10:32:08 -0800 | [diff] [blame] | 181 | bool "Secure Boot" |
York Sun | 728e700 | 2016-12-02 09:32:35 -0800 | [diff] [blame] | 182 | help |
| 183 | Enable Freescale Secure Boot feature |
| 184 | |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 185 | config QSPI_AHB_INIT |
| 186 | bool "Init the QSPI AHB bus" |
| 187 | help |
| 188 | The default setting for QSPI AHB bus just support 3bytes addressing. |
| 189 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB |
| 190 | bus for those flashes to support the full QSPI flash size. |
| 191 | |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 192 | config SYS_FSL_IFC_BANK_COUNT |
| 193 | int "Maximum banks of Integrated flash controller" |
| 194 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A |
| 195 | default 4 if ARCH_LS1043A |
| 196 | default 4 if ARCH_LS1046A |
| 197 | default 8 if ARCH_LS2080A |
| 198 | |
York Sun | 0dc9abb | 2016-10-04 14:46:50 -0700 | [diff] [blame] | 199 | config SYS_FSL_HAS_DP_DDR |
| 200 | bool |
| 201 | |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 202 | config SYS_FSL_SRDS_1 |
| 203 | bool |
| 204 | |
| 205 | config SYS_FSL_SRDS_2 |
| 206 | bool |
| 207 | |
| 208 | config SYS_HAS_SERDES |
| 209 | bool |
| 210 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 211 | endmenu |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 212 | |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 213 | menu "Layerscape clock tree configuration" |
| 214 | depends on FSL_LSCH2 || FSL_LSCH3 |
| 215 | |
| 216 | config SYS_FSL_CLK |
| 217 | bool "Enable clock tree initialization" |
| 218 | default y |
| 219 | |
| 220 | config CLUSTER_CLK_FREQ |
| 221 | int "Reference clock of core cluster" |
| 222 | depends on ARCH_LS1012A |
| 223 | default 100000000 |
| 224 | help |
| 225 | This number is the reference clock frequency of core PLL. |
| 226 | For most platforms, the core PLL and Platform PLL have the same |
| 227 | reference clock, but for some platforms, LS1012A for instance, |
| 228 | they are provided sepatately. |
| 229 | |
| 230 | config SYS_FSL_PCLK_DIV |
| 231 | int "Platform clock divider" |
| 232 | default 1 if ARCH_LS1043A |
| 233 | default 1 if ARCH_LS1046A |
| 234 | default 2 |
| 235 | help |
| 236 | This is the divider that is used to derive Platform clock from |
| 237 | Platform PLL, in another word: |
| 238 | Platform_clk = Platform_PLL_freq / this_divider |
| 239 | |
| 240 | config SYS_FSL_DSPI_CLK_DIV |
| 241 | int "DSPI clock divider" |
| 242 | default 1 if ARCH_LS1043A |
| 243 | default 2 |
| 244 | help |
| 245 | This is the divider that is used to derive DSPI clock from Platform |
| 246 | PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. |
| 247 | |
| 248 | config SYS_FSL_DUART_CLK_DIV |
| 249 | int "DUART clock divider" |
| 250 | default 1 if ARCH_LS1043A |
| 251 | default 2 |
| 252 | help |
| 253 | This is the divider that is used to derive DUART clock from Platform |
| 254 | clock, in another word DUART_clk = Platform_clk / this_divider. |
| 255 | |
| 256 | config SYS_FSL_I2C_CLK_DIV |
| 257 | int "I2C clock divider" |
| 258 | default 1 if ARCH_LS1043A |
| 259 | default 2 |
| 260 | help |
| 261 | This is the divider that is used to derive I2C clock from Platform |
| 262 | clock, in another word I2C_clk = Platform_clk / this_divider. |
| 263 | |
| 264 | config SYS_FSL_IFC_CLK_DIV |
| 265 | int "IFC clock divider" |
| 266 | default 1 if ARCH_LS1043A |
| 267 | default 2 |
| 268 | help |
| 269 | This is the divider that is used to derive IFC clock from Platform |
| 270 | clock, in another word IFC_clk = Platform_clk / this_divider. |
| 271 | |
| 272 | config SYS_FSL_LPUART_CLK_DIV |
| 273 | int "LPUART clock divider" |
| 274 | default 1 if ARCH_LS1043A |
| 275 | default 2 |
| 276 | help |
| 277 | This is the divider that is used to derive LPUART clock from Platform |
| 278 | clock, in another word LPUART_clk = Platform_clk / this_divider. |
| 279 | |
| 280 | config SYS_FSL_SDHC_CLK_DIV |
| 281 | int "SDHC clock divider" |
| 282 | default 1 if ARCH_LS1043A |
| 283 | default 1 if ARCH_LS1012A |
| 284 | default 2 |
| 285 | help |
| 286 | This is the divider that is used to derive SDHC clock from Platform |
| 287 | clock, in another word SDHC_clk = Platform_clk / this_divider. |
| 288 | endmenu |
| 289 | |
York Sun | d6964b3 | 2017-03-06 09:02:24 -0800 | [diff] [blame] | 290 | config RESV_RAM |
| 291 | bool |
| 292 | help |
| 293 | Reserve memory from the top, tracked by gd->arch.resv_ram. This |
| 294 | reserved RAM can be used by special driver that resides in memory |
| 295 | after U-Boot exits. It's up to implementation to allocate and allow |
| 296 | access to this reserved memory. For example, the reserved RAM can |
| 297 | be at the high end of physical memory. The reserve RAM may be |
| 298 | excluded from memory bank(s) passed to OS, or marked as reserved. |
| 299 | |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 300 | config SYS_FSL_ERRATUM_A008336 |
| 301 | bool |
| 302 | |
| 303 | config SYS_FSL_ERRATUM_A008514 |
| 304 | bool |
| 305 | |
| 306 | config SYS_FSL_ERRATUM_A008585 |
| 307 | bool |
| 308 | |
| 309 | config SYS_FSL_ERRATUM_A008850 |
| 310 | bool |
| 311 | |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 312 | config SYS_FSL_ERRATUM_A009203 |
| 313 | bool |
| 314 | |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 315 | config SYS_FSL_ERRATUM_A009635 |
| 316 | bool |
| 317 | |
| 318 | config SYS_FSL_ERRATUM_A009660 |
| 319 | bool |
| 320 | |
| 321 | config SYS_FSL_ERRATUM_A009929 |
| 322 | bool |
York Sun | 1a77075 | 2017-03-06 09:02:26 -0800 | [diff] [blame] | 323 | |
| 324 | config SYS_MC_RSV_MEM_ALIGN |
| 325 | hex "Management Complex reserved memory alignment" |
| 326 | depends on RESV_RAM |
| 327 | default 0x20000000 |
| 328 | help |
| 329 | Reserved memory needs to be aligned for MC to use. Default value |
| 330 | is 512MB. |