blob: 0068d3c1fa3f343b24dadddec3d9c470d858dabd [file] [log] [blame]
York Sunb3d71642016-09-26 08:09:26 -07001config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +08003 select ARMV8_SET_SMPEN
York Sun4dd8c612016-10-04 14:31:48 -07004 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -07005 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -07006 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -07007 select SYS_FSL_ERRATUM_A010315
Simon Glass62adede2017-01-23 13:31:19 -07008 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -07009 select BOARD_EARLY_INIT_F
York Sun149eb332016-09-26 08:09:27 -070010
11config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -070012 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080013 select ARMV8_SET_SMPEN
York Sun4dd8c612016-10-04 14:31:48 -070014 select FSL_LSCH2
York Sund297d392016-12-28 08:43:40 -080015 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070016 select SYS_FSL_DDR_BE
17 select SYS_FSL_DDR_VER_50
York Sun1dc61ca2016-12-28 08:43:41 -080018 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
York Sun149eb332016-09-26 08:09:27 -070023 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080024 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080025 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
Simon Glass62adede2017-01-23 13:31:19 -070027 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070028 select BOARD_EARLY_INIT_F
York Sunb3d71642016-09-26 08:09:26 -070029
York Sunbad49842016-09-26 08:09:24 -070030config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -070031 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080032 select ARMV8_SET_SMPEN
York Sun4dd8c612016-10-04 14:31:48 -070033 select FSL_LSCH2
York Sund297d392016-12-28 08:43:40 -080034 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070035 select SYS_FSL_DDR_BE
York Sunb6fffd82016-10-04 18:03:08 -070036 select SYS_FSL_DDR_VER_50
York Sunf195cf72017-01-27 09:57:31 -080037 select SYS_FSL_ERRATUM_A008336
York Sun1dc61ca2016-12-28 08:43:41 -080038 select SYS_FSL_ERRATUM_A008511
39 select SYS_FSL_ERRATUM_A009801
40 select SYS_FSL_ERRATUM_A009803
41 select SYS_FSL_ERRATUM_A009942
42 select SYS_FSL_ERRATUM_A010165
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080043 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080044 select SYS_FSL_HAS_DDR4
York Sun6b62ef02016-10-04 18:01:34 -070045 select SYS_FSL_SRDS_2
Simon Glass62adede2017-01-23 13:31:19 -070046 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070047 select BOARD_EARLY_INIT_F
York Sunb3d71642016-09-26 08:09:26 -070048
York Sunfcd0e742016-10-04 14:31:47 -070049config ARCH_LS2080A
50 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080051 select ARMV8_SET_SMPEN
Tom Rinibacb52c2017-03-07 07:13:42 -050052 select ARM_ERRATA_826974
53 select ARM_ERRATA_828024
54 select ARM_ERRATA_829520
55 select ARM_ERRATA_833471
York Sun4dd8c612016-10-04 14:31:48 -070056 select FSL_LSCH3
York Sund297d392016-12-28 08:43:40 -080057 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070058 select SYS_FSL_DDR_LE
59 select SYS_FSL_DDR_VER_50
York Sun6b62ef02016-10-04 18:01:34 -070060 select SYS_FSL_HAS_DP_DDR
York Sun92c36e22016-12-28 08:43:30 -080061 select SYS_FSL_HAS_SEC
York Sund297d392016-12-28 08:43:40 -080062 select SYS_FSL_HAS_DDR4
York Sun92c36e22016-12-28 08:43:30 -080063 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -080064 select SYS_FSL_SEC_LE
York Sun6b62ef02016-10-04 18:01:34 -070065 select SYS_FSL_SRDS_2
York Sun1dc61ca2016-12-28 08:43:41 -080066 select SYS_FSL_ERRATUM_A008336
67 select SYS_FSL_ERRATUM_A008511
68 select SYS_FSL_ERRATUM_A008514
69 select SYS_FSL_ERRATUM_A008585
70 select SYS_FSL_ERRATUM_A009635
71 select SYS_FSL_ERRATUM_A009663
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803
74 select SYS_FSL_ERRATUM_A009942
75 select SYS_FSL_ERRATUM_A010165
Ashish kumar3b52a232017-02-23 16:03:57 +053076 select SYS_FSL_ERRATUM_A009203
Simon Glass62adede2017-01-23 13:31:19 -070077 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070078 select BOARD_EARLY_INIT_F
York Sun4dd8c612016-10-04 14:31:48 -070079
80config FSL_LSCH2
81 bool
York Sun92c36e22016-12-28 08:43:30 -080082 select SYS_FSL_HAS_SEC
83 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -080084 select SYS_FSL_SEC_BE
York Sun6b62ef02016-10-04 18:01:34 -070085 select SYS_FSL_SRDS_1
86 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -070087
88config FSL_LSCH3
89 bool
York Sun6b62ef02016-10-04 18:01:34 -070090 select SYS_FSL_SRDS_1
91 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -070092
York Sun6c089742017-03-06 09:02:25 -080093config FSL_MC_ENET
94 bool "Management Complex network"
95 depends on ARCH_LS2080A
96 default y
97 select RESV_RAM
98 help
99 Enable Management Complex (MC) network
100
York Sun4dd8c612016-10-04 14:31:48 -0700101menu "Layerscape architecture"
102 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700103
Hou Zhiqiangd553bf22016-12-13 14:54:24 +0800104config FSL_PCIE_COMPAT
105 string "PCIe compatible of Kernel DT"
106 depends on PCIE_LAYERSCAPE
107 default "fsl,ls1012a-pcie" if ARCH_LS1012A
108 default "fsl,ls1043a-pcie" if ARCH_LS1043A
109 default "fsl,ls1046a-pcie" if ARCH_LS1046A
110 default "fsl,ls2080a-pcie" if ARCH_LS2080A
111 help
112 This compatible is used to find pci controller node in Kernel DT
113 to complete fixup.
114
Wenbin Songa8f57a92017-01-17 18:31:15 +0800115config HAS_FEATURE_GIC64K_ALIGN
116 bool
117 default y if ARCH_LS1043A
118
Wenbin Songc6bc7c02017-01-17 18:31:16 +0800119config HAS_FEATURE_ENHANCED_MSI
120 bool
121 default y if ARCH_LS1043A
Wenbin Songa8f57a92017-01-17 18:31:15 +0800122
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800123menu "Layerscape PPA"
124config FSL_LS_PPA
125 bool "FSL Layerscape PPA firmware support"
macro.wave.z@gmail.com01bd3342016-12-08 11:58:22 +0800126 depends on !ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800127 select ARMV8_SEC_FIRMWARE_SUPPORT
Hou Zhiqiang6be115d2017-01-16 17:31:48 +0800128 select SEC_FIRMWARE_ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800129 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800130 help
131 The FSL Primary Protected Application (PPA) is a software component
132 which is loaded during boot stage, and then remains resident in RAM
133 and runs in the TrustZone after boot.
134 Say y to enable it.
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800135choice
136 prompt "FSL Layerscape PPA firmware loading-media select"
137 depends on FSL_LS_PPA
138 default SYS_LS_PPA_FW_IN_XIP
139
140config SYS_LS_PPA_FW_IN_XIP
141 bool "XIP"
142 help
143 Say Y here if the PPA firmware locate at XIP flash, such
144 as NOR or QSPI flash.
145
146endchoice
147
148config SYS_LS_PPA_FW_ADDR
149 hex "Address of PPA firmware loading from"
150 depends on FSL_LS_PPA
151 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
Santan Kumarc61c6992017-03-07 11:21:03 +0530152 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800153 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
154 help
155 If the PPA firmware locate at XIP flash, such as NOR or
156 QSPI flash, this address is a directly memory-mapped.
157 If it is in a serial accessed flash, such as NAND and SD
158 card, it is a byte offset.
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800159endmenu
160
York Sun149eb332016-09-26 08:09:27 -0700161config SYS_FSL_ERRATUM_A010315
162 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800163
164config SYS_FSL_ERRATUM_A010539
165 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700166
York Sunf188d222016-10-04 14:45:01 -0700167config MAX_CPUS
168 int "Maximum number of CPUs permitted for Layerscape"
169 default 4 if ARCH_LS1043A
170 default 4 if ARCH_LS1046A
171 default 16 if ARCH_LS2080A
172 default 1
173 help
174 Set this number to the maximum number of possible CPUs in the SoC.
175 SoCs may have multiple clusters with each cluster may have multiple
176 ports. If some ports are reserved but higher ports are used for
177 cores, count the reserved ports. This will allocate enough memory
178 in spin table to properly handle all cores.
179
York Sun728e7002016-12-02 09:32:35 -0800180config SECURE_BOOT
York Sun8a3d8ed2017-01-04 10:32:08 -0800181 bool "Secure Boot"
York Sun728e7002016-12-02 09:32:35 -0800182 help
183 Enable Freescale Secure Boot feature
184
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800185config QSPI_AHB_INIT
186 bool "Init the QSPI AHB bus"
187 help
188 The default setting for QSPI AHB bus just support 3bytes addressing.
189 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
190 bus for those flashes to support the full QSPI flash size.
191
York Sune7310a32016-10-04 14:45:54 -0700192config SYS_FSL_IFC_BANK_COUNT
193 int "Maximum banks of Integrated flash controller"
194 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
195 default 4 if ARCH_LS1043A
196 default 4 if ARCH_LS1046A
197 default 8 if ARCH_LS2080A
198
York Sun0dc9abb2016-10-04 14:46:50 -0700199config SYS_FSL_HAS_DP_DDR
200 bool
201
York Sun6b62ef02016-10-04 18:01:34 -0700202config SYS_FSL_SRDS_1
203 bool
204
205config SYS_FSL_SRDS_2
206 bool
207
208config SYS_HAS_SERDES
209 bool
210
York Sun4dd8c612016-10-04 14:31:48 -0700211endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800212
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800213menu "Layerscape clock tree configuration"
214 depends on FSL_LSCH2 || FSL_LSCH3
215
216config SYS_FSL_CLK
217 bool "Enable clock tree initialization"
218 default y
219
220config CLUSTER_CLK_FREQ
221 int "Reference clock of core cluster"
222 depends on ARCH_LS1012A
223 default 100000000
224 help
225 This number is the reference clock frequency of core PLL.
226 For most platforms, the core PLL and Platform PLL have the same
227 reference clock, but for some platforms, LS1012A for instance,
228 they are provided sepatately.
229
230config SYS_FSL_PCLK_DIV
231 int "Platform clock divider"
232 default 1 if ARCH_LS1043A
233 default 1 if ARCH_LS1046A
234 default 2
235 help
236 This is the divider that is used to derive Platform clock from
237 Platform PLL, in another word:
238 Platform_clk = Platform_PLL_freq / this_divider
239
240config SYS_FSL_DSPI_CLK_DIV
241 int "DSPI clock divider"
242 default 1 if ARCH_LS1043A
243 default 2
244 help
245 This is the divider that is used to derive DSPI clock from Platform
246 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
247
248config SYS_FSL_DUART_CLK_DIV
249 int "DUART clock divider"
250 default 1 if ARCH_LS1043A
251 default 2
252 help
253 This is the divider that is used to derive DUART clock from Platform
254 clock, in another word DUART_clk = Platform_clk / this_divider.
255
256config SYS_FSL_I2C_CLK_DIV
257 int "I2C clock divider"
258 default 1 if ARCH_LS1043A
259 default 2
260 help
261 This is the divider that is used to derive I2C clock from Platform
262 clock, in another word I2C_clk = Platform_clk / this_divider.
263
264config SYS_FSL_IFC_CLK_DIV
265 int "IFC clock divider"
266 default 1 if ARCH_LS1043A
267 default 2
268 help
269 This is the divider that is used to derive IFC clock from Platform
270 clock, in another word IFC_clk = Platform_clk / this_divider.
271
272config SYS_FSL_LPUART_CLK_DIV
273 int "LPUART clock divider"
274 default 1 if ARCH_LS1043A
275 default 2
276 help
277 This is the divider that is used to derive LPUART clock from Platform
278 clock, in another word LPUART_clk = Platform_clk / this_divider.
279
280config SYS_FSL_SDHC_CLK_DIV
281 int "SDHC clock divider"
282 default 1 if ARCH_LS1043A
283 default 1 if ARCH_LS1012A
284 default 2
285 help
286 This is the divider that is used to derive SDHC clock from Platform
287 clock, in another word SDHC_clk = Platform_clk / this_divider.
288endmenu
289
York Sund6964b32017-03-06 09:02:24 -0800290config RESV_RAM
291 bool
292 help
293 Reserve memory from the top, tracked by gd->arch.resv_ram. This
294 reserved RAM can be used by special driver that resides in memory
295 after U-Boot exits. It's up to implementation to allocate and allow
296 access to this reserved memory. For example, the reserved RAM can
297 be at the high end of physical memory. The reserve RAM may be
298 excluded from memory bank(s) passed to OS, or marked as reserved.
299
York Sun1dc61ca2016-12-28 08:43:41 -0800300config SYS_FSL_ERRATUM_A008336
301 bool
302
303config SYS_FSL_ERRATUM_A008514
304 bool
305
306config SYS_FSL_ERRATUM_A008585
307 bool
308
309config SYS_FSL_ERRATUM_A008850
310 bool
311
Ashish kumar3b52a232017-02-23 16:03:57 +0530312config SYS_FSL_ERRATUM_A009203
313 bool
314
York Sun1dc61ca2016-12-28 08:43:41 -0800315config SYS_FSL_ERRATUM_A009635
316 bool
317
318config SYS_FSL_ERRATUM_A009660
319 bool
320
321config SYS_FSL_ERRATUM_A009929
322 bool
York Sun1a770752017-03-06 09:02:26 -0800323
324config SYS_MC_RSV_MEM_ALIGN
325 hex "Management Complex reserved memory alignment"
326 depends on RESV_RAM
327 default 0x20000000
328 help
329 Reserved memory needs to be aligned for MC to use. Default value
330 is 512MB.