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git01.mediatek.com / filogic / uboot / f7886b7a747771da1b77cd2fc729c36a92130eac / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 7dd939589528b3d96ef05cde2f17670a7165b985 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000[diff] [blame]2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]30/* Number of TLB CAM entries we have on FSL Book-E chips */
31#if defined(CONFIG_E500MC)
32#define CONFIG_SYS_NUM_TLBCAMS 64
33#elif defined(CONFIG_E500)
34#define CONFIG_SYS_NUM_TLBCAMS 16
35#endif
36
37#if defined(CONFIG_MPC8536)
38#define CONFIG_MAX_CPUS 1
39#define CONFIG_SYS_FSL_NUM_LAWS 12
40#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]41#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]42
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]43#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]44#define CONFIG_MAX_CPUS 1
45#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]46#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]47
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]48#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_MAX_CPUS 1
50#define CONFIG_SYS_FSL_NUM_LAWS 8
51#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]52#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]53
54#elif defined(CONFIG_MPC8544)
55#define CONFIG_MAX_CPUS 1
56#define CONFIG_SYS_FSL_NUM_LAWS 10
57#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]58#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]59
60#elif defined(CONFIG_MPC8548)
61#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
63#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]64#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala866c6fa2011-09-16 09:54:30 -0500[diff] [blame]65#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Galaf3339d62011-10-03 08:37:57 -0500[diff] [blame]66#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500[diff] [blame]67#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]68#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
69#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
70#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
71#define CONFIG_SYS_FSL_RMU
72#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]73
74#elif defined(CONFIG_MPC8555)
75#define CONFIG_MAX_CPUS 1
76#define CONFIG_SYS_FSL_NUM_LAWS 8
77#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]78#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]79
80#elif defined(CONFIG_MPC8560)
81#define CONFIG_MAX_CPUS 1
82#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]83#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]84
85#elif defined(CONFIG_MPC8568)
86#define CONFIG_MAX_CPUS 1
87#define CONFIG_SYS_FSL_NUM_LAWS 10
88#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]89#define QE_MURAM_SIZE 0x10000UL
90#define MAX_QE_RISC 2
91#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]92#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]93#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
94#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
95#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
96#define CONFIG_SYS_FSL_RMU
97#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]98
99#elif defined(CONFIG_MPC8569)
100#define CONFIG_MAX_CPUS 1
101#define CONFIG_SYS_FSL_NUM_LAWS 10
102#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]103#define QE_MURAM_SIZE 0x20000UL
104#define MAX_QE_RISC 4
105#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]106#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]107#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
108#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
109#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
110#define CONFIG_SYS_FSL_RMU
111#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]112
113#elif defined(CONFIG_MPC8572)
114#define CONFIG_MAX_CPUS 2
115#define CONFIG_SYS_FSL_NUM_LAWS 12
116#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]117#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]118#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]119#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]120
121#elif defined(CONFIG_P1010)
122#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]123#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]124#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]125#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]126#define CONFIG_TSECV2
127#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]128#define CONFIG_FSL_SATA_V2
129#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
130#define CONFIG_NUM_DDR_CONTROLLERS 1
131#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]132#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]133#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]134#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]135#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]136#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]137
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]138/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]139#elif defined(CONFIG_P1011)
140#define CONFIG_MAX_CPUS 1
141#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]142#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]143#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]144#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]145#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]146#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]147#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
148#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]149
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]150/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]151#elif defined(CONFIG_P1012)
152#define CONFIG_MAX_CPUS 1
153#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]154#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]155#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]156#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]157#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]158#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]159#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
160#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]161#define QE_MURAM_SIZE 0x6000UL
162#define MAX_QE_RISC 1
163#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]164
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]165/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]166#elif defined(CONFIG_P1013)
167#define CONFIG_MAX_CPUS 1
168#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]169#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]170#define CONFIG_TSECV2
171#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]172#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]173#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]174#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
175#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
176#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]177
178#elif defined(CONFIG_P1014)
179#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]180#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]181#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]182#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]183#define CONFIG_TSECV2
184#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]185#define CONFIG_FSL_SATA_V2
186#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
187#define CONFIG_NUM_DDR_CONTROLLERS 1
188#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]189#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]190#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]191#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]192#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]193
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]194/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]195#elif defined(CONFIG_P1017)
196#define CONFIG_MAX_CPUS 1
197#define CONFIG_SYS_FSL_NUM_LAWS 12
198#define CONFIG_SYS_FSL_SEC_COMPAT 4
199#define CONFIG_SYS_NUM_FMAN 1
200#define CONFIG_SYS_NUM_FM1_DTSEC 2
201#define CONFIG_NUM_DDR_CONTROLLERS 1
202#define CONFIG_SYS_QMAN_NUM_PORTALS 3
203#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]204#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]205#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]206#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]207
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]208#elif defined(CONFIG_P1020)
209#define CONFIG_MAX_CPUS 2
210#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]211#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]212#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]213#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]214#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]215#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]216#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
217#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]218
219#elif defined(CONFIG_P1021)
220#define CONFIG_MAX_CPUS 2
221#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]222#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]223#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]224#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]225#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]226#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]227#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
228#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]229#define QE_MURAM_SIZE 0x6000UL
230#define MAX_QE_RISC 1
231#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]232
233#elif defined(CONFIG_P1022)
234#define CONFIG_MAX_CPUS 2
235#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]236#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]237#define CONFIG_TSECV2
238#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]239#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]240#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]241#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
242#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
243#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]244
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]245#elif defined(CONFIG_P1023)
246#define CONFIG_MAX_CPUS 2
247#define CONFIG_SYS_FSL_NUM_LAWS 12
248#define CONFIG_SYS_FSL_SEC_COMPAT 4
249#define CONFIG_SYS_NUM_FMAN 1
250#define CONFIG_SYS_NUM_FM1_DTSEC 2
251#define CONFIG_NUM_DDR_CONTROLLERS 1
252#define CONFIG_SYS_QMAN_NUM_PORTALS 3
253#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]254#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]255#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]256#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]257
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]258/* P1024 is lower end variant of P1020 */
259#elif defined(CONFIG_P1024)
260#define CONFIG_MAX_CPUS 2
261#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]262#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]263#define CONFIG_TSECV2
264#define CONFIG_FSL_PCIE_DISABLE_ASPM
265#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]266#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]267#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
268#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
269
270/* P1025 is lower end variant of P1021 */
271#elif defined(CONFIG_P1025)
272#define CONFIG_MAX_CPUS 2
273#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]274#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]275#define CONFIG_TSECV2
276#define CONFIG_FSL_PCIE_DISABLE_ASPM
277#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]278#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]279#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
280#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]281#define QE_MURAM_SIZE 0x6000UL
282#define MAX_QE_RISC 1
283#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]284
285/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]286#elif defined(CONFIG_P2010)
287#define CONFIG_MAX_CPUS 1
288#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]289#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]290#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]291#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]292#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]293#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]294
295#elif defined(CONFIG_P2020)
296#define CONFIG_MAX_CPUS 2
297#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]298#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]299#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]300#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]301#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]302#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]303#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
304#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
305#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
306#define CONFIG_SYS_FSL_RMU
307#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]308
309#elif defined(CONFIG_PPC_P2040)
310#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]311#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]312#define CONFIG_SYS_FSL_NUM_LAWS 32
313#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]314#define CONFIG_SYS_NUM_FMAN 1
315#define CONFIG_SYS_NUM_FM1_DTSEC 5
316#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]317#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]318#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]319#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]320#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]321#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
322#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]323#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]324#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]325#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]326#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]327#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]328#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
329#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
330#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]331
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]332#elif defined(CONFIG_PPC_P2041)
333#define CONFIG_MAX_CPUS 4
334#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
335#define CONFIG_SYS_FSL_NUM_LAWS 32
336#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]337#define CONFIG_FSL_SATA_V2
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]338#define CONFIG_SYS_NUM_FMAN 1
339#define CONFIG_SYS_NUM_FM1_DTSEC 5
340#define CONFIG_SYS_NUM_FM1_10GEC 1
341#define CONFIG_NUM_DDR_CONTROLLERS 1
342#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
343#define CONFIG_SYS_FSL_TBCLK_DIV 32
344#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]345#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]346#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
347#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]348#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]349#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]350#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]351#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]352#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]353#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
354#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
355#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]356
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]357#elif defined(CONFIG_PPC_P3041)
358#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]359#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]360#define CONFIG_SYS_FSL_NUM_LAWS 32
361#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]362#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]363#define CONFIG_SYS_NUM_FMAN 1
364#define CONFIG_SYS_NUM_FM1_DTSEC 5
365#define CONFIG_SYS_NUM_FM1_10GEC 1
366#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]367#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]368#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]369#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]370#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]371#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
372#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]373#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]374#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun53155532012-08-08 18:04:53 +0000[diff] [blame]375#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]376#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]377#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]378#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
379#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
380#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]381
382#elif defined(CONFIG_PPC_P4040)
383#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]384#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]385#define CONFIG_SYS_FSL_NUM_LAWS 32
386#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]387#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]388#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]389#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]390#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]391#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]392#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]393#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
394#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
395#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]396
397#elif defined(CONFIG_PPC_P4080)
398#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]399#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]400#define CONFIG_SYS_FSL_NUM_LAWS 32
401#define CONFIG_SYS_FSL_SEC_COMPAT 4
402#define CONFIG_SYS_NUM_FMAN 2
403#define CONFIG_SYS_NUM_FM1_DTSEC 4
404#define CONFIG_SYS_NUM_FM2_DTSEC 4
405#define CONFIG_SYS_NUM_FM1_10GEC 1
406#define CONFIG_SYS_NUM_FM2_10GEC 1
407#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]408#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]409#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]410#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]411#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]412#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
413#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]414#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]415#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
416#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
417#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
418#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
419#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]420#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]421#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]422#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]423#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]424#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]425#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]426#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]427#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
428#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
429#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
430#define CONFIG_SYS_FSL_RMU
431#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]432
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]433/* P5010 is single core version of P5020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]434#elif defined(CONFIG_PPC_P5010)
435#define CONFIG_MAX_CPUS 1
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]436#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]437#define CONFIG_SYS_FSL_NUM_LAWS 32
438#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]439#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]440#define CONFIG_SYS_NUM_FMAN 1
441#define CONFIG_SYS_NUM_FM1_DTSEC 5
442#define CONFIG_SYS_NUM_FM1_10GEC 1
443#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]444#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]445#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]446#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]447#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]448#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
449#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]450#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]451#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]452#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]453#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
454#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
455#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]456
457#elif defined(CONFIG_PPC_P5020)
458#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]459#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]460#define CONFIG_SYS_FSL_NUM_LAWS 32
461#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]462#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]463#define CONFIG_SYS_NUM_FMAN 1
464#define CONFIG_SYS_NUM_FM1_DTSEC 5
465#define CONFIG_SYS_NUM_FM1_10GEC 1
466#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]467#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]468#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]469#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]470#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]471#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
472#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]473#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]474#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]475#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]476#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
477#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
478#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]479
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000[diff] [blame]480#elif defined(CONFIG_BSC9131)
481#define CONFIG_MAX_CPUS 1
482#define CONFIG_FSL_SDHC_V2_3
483#define CONFIG_SYS_FSL_NUM_LAWS 12
484#define CONFIG_TSECV2
485#define CONFIG_SYS_FSL_SEC_COMPAT 4
486#define CONFIG_NUM_DDR_CONTROLLERS 1
487#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
488#define CONFIG_NAND_FSL_IFC
489#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
490#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
491
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]492#else
493#error Processor type not defined for this platform
494#endif
495
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]496#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
497#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
498#endif
499
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]500#endif /* _ASM_MPC85xx_CONFIG_H_ */