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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha1b51c932016-02-11 15:47:20 -08002/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha1b51c932016-02-11 15:47:20 -08005 */
Patrice Chotard789ee0e2017-10-23 09:53:58 +02006
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +01007#define LOG_CATEGORY UCLASS_CLK
8
Vikas Manocha1b51c932016-02-11 15:47:20 -08009#include <common.h>
Vikas Manochadaaeaab2017-02-12 10:25:45 -080010#include <clk-uclass.h>
11#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Patrice Chotard03f10a12017-11-15 13:14:51 +010013#include <stm32_rcc.h>
Vikas Manocha1b51c932016-02-11 15:47:20 -080014#include <asm/io.h>
Vikas Manocha1b51c932016-02-11 15:47:20 -080015#include <asm/arch/stm32.h>
Patrice Chotard22768d52017-11-15 13:14:44 +010016#include <asm/arch/stm32_pwr.h>
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +010017#include <dm/device_compat.h>
Patrice Chotard7bdf9712017-07-18 09:29:05 +020018#include <dt-bindings/mfd/stm32f7-rcc.h>
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +010019#include <linux/bitops.h>
Patrice Chotard7bdf9712017-07-18 09:29:05 +020020
Michael Kurzc204fb72017-01-22 16:04:24 +010021#define RCC_CR_HSION BIT(0)
22#define RCC_CR_HSEON BIT(16)
23#define RCC_CR_HSERDY BIT(17)
24#define RCC_CR_HSEBYP BIT(18)
25#define RCC_CR_CSSON BIT(19)
26#define RCC_CR_PLLON BIT(24)
27#define RCC_CR_PLLRDY BIT(25)
Patrice Chotard369d4832017-11-15 13:14:52 +010028#define RCC_CR_PLLSAION BIT(28)
29#define RCC_CR_PLLSAIRDY BIT(29)
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090030
Michael Kurzc204fb72017-01-22 16:04:24 +010031#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
32#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
33#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
34#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
35#define RCC_PLLCFGR_PLLSRC BIT(22)
36#define RCC_PLLCFGR_PLLM_SHIFT 0
37#define RCC_PLLCFGR_PLLN_SHIFT 6
38#define RCC_PLLCFGR_PLLP_SHIFT 16
39#define RCC_PLLCFGR_PLLQ_SHIFT 24
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090040
Michael Kurzc204fb72017-01-22 16:04:24 +010041#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
42#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
43#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
44#define RCC_CFGR_SW0 BIT(0)
45#define RCC_CFGR_SW1 BIT(1)
46#define RCC_CFGR_SW_MASK GENMASK(1, 0)
47#define RCC_CFGR_SW_HSI 0
48#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
49#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
50#define RCC_CFGR_SWS0 BIT(2)
51#define RCC_CFGR_SWS1 BIT(3)
52#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
53#define RCC_CFGR_SWS_HSI 0
54#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
55#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
56#define RCC_CFGR_HPRE_SHIFT 4
57#define RCC_CFGR_PPRE1_SHIFT 10
58#define RCC_CFGR_PPRE2_SHIFT 13
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +090059
Patrice Chotard9490aca2018-02-08 17:20:46 +010060#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
61#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
Patrice Chotard8aca2d12018-02-08 17:20:48 +010062#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
63#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
Patrice Chotard369d4832017-11-15 13:14:52 +010064#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
65#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
Patrice Chotard8aca2d12018-02-08 17:20:48 +010066#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
67#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
Patrice Chotardd5d36552018-01-19 18:02:40 +010068#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
Patrice Chotard369d4832017-11-15 13:14:52 +010069#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
Patrice Chotardff7b11e2018-02-08 17:20:49 +010070#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
Patrice Chotard369d4832017-11-15 13:14:52 +010071
Patrice Chotardef772872018-02-07 10:44:46 +010072#define RCC_DCKCFGRX_TIMPRE BIT(24)
Patrice Chotard369d4832017-11-15 13:14:52 +010073#define RCC_DCKCFGRX_CK48MSEL BIT(27)
74#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
75#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
76
Patrice Chotardff7b11e2018-02-08 17:20:49 +010077#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
78#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
79#define RCC_DCKCFGR_PLLSAIDIVR_2 0
80
Patrice Chotard06fc6482017-11-15 13:14:49 +010081/*
82 * RCC AHB1ENR specific definitions
83 */
84#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
85#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
86#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
87
88/*
89 * RCC APB1ENR specific definitions
90 */
91#define RCC_APB1ENR_TIM2EN BIT(0)
92#define RCC_APB1ENR_PWREN BIT(28)
93
94/*
95 * RCC APB2ENR specific definitions
96 */
97#define RCC_APB2ENR_SYSCFGEN BIT(14)
Patrice Chotarde2d564e2018-01-18 14:10:05 +010098#define RCC_APB2ENR_SAI1EN BIT(22)
Patrice Chotard06fc6482017-11-15 13:14:49 +010099
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100100enum pllsai_div {
101 PLLSAIP,
102 PLLSAIQ,
103 PLLSAIR,
104};
105
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100106static const struct stm32_clk_info stm32f4_clk_info = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100107 /* 180 MHz */
108 .sys_pll_psc = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100109 .pll_n = 360,
110 .pll_p = 2,
111 .pll_q = 8,
112 .ahb_psc = AHB_PSC_1,
113 .apb1_psc = APB_PSC_4,
114 .apb2_psc = APB_PSC_2,
115 },
116 .has_overdrive = false,
Patrice Chotard369d4832017-11-15 13:14:52 +0100117 .v2 = false,
Patrice Chotard1509d662017-11-15 13:14:47 +0100118};
119
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100120static const struct stm32_clk_info stm32f7_clk_info = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100121 /* 200 MHz */
122 .sys_pll_psc = {
Patrice Chotard1509d662017-11-15 13:14:47 +0100123 .pll_n = 400,
124 .pll_p = 2,
125 .pll_q = 8,
126 .ahb_psc = AHB_PSC_1,
127 .apb1_psc = APB_PSC_4,
128 .apb2_psc = APB_PSC_2,
129 },
130 .has_overdrive = true,
Patrice Chotard369d4832017-11-15 13:14:52 +0100131 .v2 = true,
Patrice Chotard1509d662017-11-15 13:14:47 +0100132};
133
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200134struct stm32_clk {
135 struct stm32_rcc_regs *base;
Patrice Chotard22768d52017-11-15 13:14:44 +0100136 struct stm32_pwr_regs *pwr_regs;
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100137 struct stm32_clk_info info;
138 unsigned long hse_rate;
Patrice Chotard7264aae2018-04-11 17:07:45 +0200139 bool pllsaip;
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900140};
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900141
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100142#ifdef CONFIG_VIDEO_STM32
143static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
144#endif
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100145static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
146
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200147static int configure_clocks(struct udevice *dev)
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900148{
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200149 struct stm32_clk *priv = dev_get_priv(dev);
150 struct stm32_rcc_regs *regs = priv->base;
Patrice Chotard22768d52017-11-15 13:14:44 +0100151 struct stm32_pwr_regs *pwr = priv->pwr_regs;
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100152 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200153
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900154 /* Reset RCC configuration */
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200155 setbits_le32(&regs->cr, RCC_CR_HSION);
156 writel(0, &regs->cfgr); /* Reset CFGR */
157 clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
Patrice Chotard369d4832017-11-15 13:14:52 +0100158 | RCC_CR_PLLON | RCC_CR_PLLSAION));
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200159 writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
160 clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
161 writel(0, &regs->cir); /* Disable all interrupts */
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900162
163 /* Configure for HSE+PLL operation */
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200164 setbits_le32(&regs->cr, RCC_CR_HSEON);
165 while (!(readl(&regs->cr) & RCC_CR_HSERDY))
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900166 ;
167
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200168 setbits_le32(&regs->cfgr, ((
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100169 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
170 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
171 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900172
173 /* Configure the main PLL */
Patrice Chotardb6653f62017-10-26 13:23:19 +0200174 setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
175 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100176 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
Patrice Chotardb6653f62017-10-26 13:23:19 +0200177 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100178 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
Patrice Chotardb6653f62017-10-26 13:23:19 +0200179 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100180 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
Patrice Chotardb6653f62017-10-26 13:23:19 +0200181 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100182 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900183
Patrice Chotardcb15d282018-02-08 17:20:47 +0100184 /* configure SDMMC clock */
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100185 if (priv->info.v2) { /*stm32f7 case */
Patrice Chotard7264aae2018-04-11 17:07:45 +0200186 if (priv->pllsaip)
187 /* select PLLSAIP as 48MHz clock source */
188 setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
189 else
190 /* select PLLQ as 48MHz clock source */
191 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
Patrice Chotard369d4832017-11-15 13:14:52 +0100192
193 /* select 48MHz as SDMMC1 clock source */
194 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
195
196 /* select 48MHz as SDMMC2 clock source */
197 clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
198 } else { /* stm32f4 case */
Patrice Chotard7264aae2018-04-11 17:07:45 +0200199 if (priv->pllsaip)
200 /* select PLLSAIP as 48MHz clock source */
201 setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
202 else
203 /* select PLLQ as 48MHz clock source */
204 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
Patrice Chotard369d4832017-11-15 13:14:52 +0100205
206 /* select 48MHz as SDMMC1 clock source */
207 clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
208 }
209
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100210 /*
Patrice Chotard7264aae2018-04-11 17:07:45 +0200211 * Configure the SAI PLL to generate LTDC pixel clock and
212 * 48 Mhz for SDMMC and USB
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100213 */
Patrice Chotard7264aae2018-04-11 17:07:45 +0200214 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIP_MASK,
215 RCC_PLLSAICFGR_PLLSAIP_4);
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100216 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
217 RCC_PLLSAICFGR_PLLSAIR_3);
218 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
219 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
220
221 clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
222 RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
Patrice Chotard7264aae2018-04-11 17:07:45 +0200223
Patrice Chotardcb15d282018-02-08 17:20:47 +0100224 /* Enable the main PLL */
225 setbits_le32(&regs->cr, RCC_CR_PLLON);
226 while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
Patrice Chotard369d4832017-11-15 13:14:52 +0100227 ;
228
Patrice Chotard7264aae2018-04-11 17:07:45 +0200229 /* Enable the SAI PLL */
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100230 setbits_le32(&regs->cr, RCC_CR_PLLSAION);
231 while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
232 ;
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200233 setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
Patrice Chotard1509d662017-11-15 13:14:47 +0100234
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100235 if (priv->info.has_overdrive) {
Patrice Chotard1509d662017-11-15 13:14:47 +0100236 /*
237 * Enable high performance mode
238 * System frequency up to 200 MHz
239 */
240 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
241 /* Infinite wait! */
242 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
243 ;
244 /* Enable the Over-drive switch */
245 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
246 /* Infinite wait! */
247 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
248 ;
249 }
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900250
251 stm32_flash_latency_cfg(5);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200252 clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
253 setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900254
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200255 while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900256 RCC_CFGR_SWS_PLL)
257 ;
258
Patrice Chotarde2d564e2018-01-18 14:10:05 +0100259#ifdef CONFIG_ETH_DESIGNWARE
260 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
261 setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
262#endif
263
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900264 return 0;
265}
266
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100267static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
Patrice Chotard369d4832017-11-15 13:14:52 +0100268{
269 struct stm32_rcc_regs *regs = priv->base;
Patrice Chotard369d4832017-11-15 13:14:52 +0100270
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100271 if (priv->info.v2) /*stm32f7 case */
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100272 return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
Patrice Chotard369d4832017-11-15 13:14:52 +0100273 else
Patrice Chotard369d4832017-11-15 13:14:52 +0100274
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100275 return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
276}
277
278static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
279{
280 struct stm32_rcc_regs *regs = priv->base;
281 u16 pllm, pllsain;
282
283 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
284 pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
285 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
286
287 return ((priv->hse_rate / pllm) * pllsain);
288}
289
290static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
291 enum pllsai_div output)
292{
293 struct stm32_rcc_regs *regs = priv->base;
294 u16 pll_div_output;
295
296 switch (output) {
297 case PLLSAIP:
298 pll_div_output = ((((readl(&regs->pllsaicfgr)
299 & RCC_PLLSAICFGR_PLLSAIP_MASK)
300 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
301 break;
302 case PLLSAIQ:
303 pll_div_output = (readl(&regs->pllsaicfgr)
304 & RCC_PLLSAICFGR_PLLSAIQ_MASK)
305 >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
306 break;
307 case PLLSAIR:
308 pll_div_output = (readl(&regs->pllsaicfgr)
309 & RCC_PLLSAICFGR_PLLSAIR_MASK)
310 >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
311 break;
312 default:
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100313 log_err("incorrect PLLSAI output %d\n", output);
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100314 return -EINVAL;
Patrice Chotard369d4832017-11-15 13:14:52 +0100315 }
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100316
317 return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
Patrice Chotard369d4832017-11-15 13:14:52 +0100318}
319
Patrice Chotardef772872018-02-07 10:44:46 +0100320static bool stm32_get_timpre(struct stm32_clk *priv)
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200321{
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200322 struct stm32_rcc_regs *regs = priv->base;
Patrice Chotardef772872018-02-07 10:44:46 +0100323 u32 val;
324
325 if (priv->info.v2) /*stm32f7 case */
326 val = readl(&regs->dckcfgr2);
327 else
328 val = readl(&regs->dckcfgr);
329 /* get timer prescaler */
330 return !!(val & RCC_DCKCFGRX_TIMPRE);
331}
332
333static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
334{
335 u8 shift;
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200336 /* Prescaler table lookups for clock computation */
337 u8 ahb_psc_table[16] = {
338 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
339 };
Patrice Chotardef772872018-02-07 10:44:46 +0100340
341 shift = ahb_psc_table[(
342 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
343 >> RCC_CFGR_HPRE_SHIFT)];
344
345 return sysclk >> shift;
346};
347
348static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
349{
350 /* Prescaler table lookups for clock computation */
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200351 u8 apb_psc_table[8] = {
352 0, 0, 0, 0, 1, 2, 3, 4
353 };
354
Patrice Chotardef772872018-02-07 10:44:46 +0100355 if (apb == APB1)
356 return apb_psc_table[(
357 (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
358 >> RCC_CFGR_PPRE1_SHIFT)];
359 else /* APB2 */
360 return apb_psc_table[(
361 (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
362 >> RCC_CFGR_PPRE2_SHIFT)];
363};
364
365static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
366 enum apb apb)
367{
368 struct stm32_rcc_regs *regs = priv->base;
369 u8 shift = stm32_get_apb_shift(regs, apb);
370
371 if (stm32_get_timpre(priv))
372 /*
373 * if APB prescaler is configured to a
374 * division factor of 1, 2 or 4
375 */
376 switch (shift) {
377 case 0:
378 case 1:
379 case 2:
380 return stm32_get_hclk_rate(regs, sysclk);
381 default:
382 return (sysclk >> shift) * 4;
383 }
384 else
385 /*
386 * if APB prescaler is configured to a
387 * division factor of 1
388 */
389 if (shift == 0)
390 return sysclk;
391 else
392 return (sysclk >> shift) * 2;
393};
394
395static ulong stm32_clk_get_rate(struct clk *clk)
396{
397 struct stm32_clk *priv = dev_get_priv(clk->dev);
398 struct stm32_rcc_regs *regs = priv->base;
399 u32 sysclk = 0;
Patrice Chotard81d77652018-02-08 17:20:45 +0100400 u32 vco;
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100401 u32 sdmmcxsel_bit;
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100402 u32 saidivr;
403 u32 pllsai_rate;
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100404 u16 pllm, plln, pllp, pllq;
Patrice Chotardef772872018-02-07 10:44:46 +0100405
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200406 if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
407 RCC_CFGR_SWS_PLL) {
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200408 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
409 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
410 >> RCC_PLLCFGR_PLLN_SHIFT);
411 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
412 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100413 pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
414 >> RCC_PLLCFGR_PLLQ_SHIFT);
Patrice Chotard81d77652018-02-08 17:20:45 +0100415 vco = (priv->hse_rate / pllm) * plln;
416 sysclk = vco / pllp;
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200417 } else {
418 return -EINVAL;
419 }
420
421 switch (clk->id) {
422 /*
423 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
424 * AHB1, AHB2 and AHB3
425 */
426 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
Patrice Chotardef772872018-02-07 10:44:46 +0100427 return stm32_get_hclk_rate(regs, sysclk);
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200428 /* APB1 CLOCK */
429 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
Patrice Chotardef772872018-02-07 10:44:46 +0100430 /* For timer clock, an additionnal prescaler is used*/
431 switch (clk->id) {
432 case STM32F7_APB1_CLOCK(TIM2):
433 case STM32F7_APB1_CLOCK(TIM3):
434 case STM32F7_APB1_CLOCK(TIM4):
435 case STM32F7_APB1_CLOCK(TIM5):
436 case STM32F7_APB1_CLOCK(TIM6):
437 case STM32F7_APB1_CLOCK(TIM7):
438 case STM32F7_APB1_CLOCK(TIM12):
439 case STM32F7_APB1_CLOCK(TIM13):
440 case STM32F7_APB1_CLOCK(TIM14):
441 return stm32_get_timer_rate(priv, sysclk, APB1);
442 }
443 return (sysclk >> stm32_get_apb_shift(regs, APB1));
444
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200445 /* APB2 CLOCK */
Patrice Chotarde199c3a2018-02-08 17:20:51 +0100446 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100447 switch (clk->id) {
Patrice Chotard369d4832017-11-15 13:14:52 +0100448 /*
449 * particular case for SDMMC1 and SDMMC2 :
450 * 48Mhz source clock can be from main PLL or from
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100451 * PLLSAIP
Patrice Chotard369d4832017-11-15 13:14:52 +0100452 */
Patrice Chotard369d4832017-11-15 13:14:52 +0100453 case STM32F7_APB2_CLOCK(SDMMC1):
Patrice Chotard369d4832017-11-15 13:14:52 +0100454 case STM32F7_APB2_CLOCK(SDMMC2):
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100455 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
456 sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
457 else
458 sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
459
460 if (readl(&regs->dckcfgr2) & sdmmcxsel_bit)
461 /* System clock is selected as SDMMC1 clock */
Patrice Chotard369d4832017-11-15 13:14:52 +0100462 return sysclk;
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100463 /*
464 * 48 MHz can be generated by either PLLSAIP
465 * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
466 */
467 if (stm32_clk_get_ck48msel(priv))
468 return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
Patrice Chotard369d4832017-11-15 13:14:52 +0100469 else
Patrice Chotard8aca2d12018-02-08 17:20:48 +0100470 return (vco / pllq);
Patrice Chotard369d4832017-11-15 13:14:52 +0100471 break;
Patrice Chotardef772872018-02-07 10:44:46 +0100472
473 /* For timer clock, an additionnal prescaler is used*/
474 case STM32F7_APB2_CLOCK(TIM1):
475 case STM32F7_APB2_CLOCK(TIM8):
476 case STM32F7_APB2_CLOCK(TIM9):
477 case STM32F7_APB2_CLOCK(TIM10):
478 case STM32F7_APB2_CLOCK(TIM11):
479 return stm32_get_timer_rate(priv, sysclk, APB2);
480 break;
Patrice Chotardff7b11e2018-02-08 17:20:49 +0100481
482 /* particular case for LTDC clock */
483 case STM32F7_APB2_CLOCK(LTDC):
484 saidivr = readl(&regs->dckcfgr);
485 saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
486 >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
487 pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
488
489 return pllsai_rate / pllsaidivr_table[saidivr];
Patrice Chotard369d4832017-11-15 13:14:52 +0100490 }
Patrice Chotardef772872018-02-07 10:44:46 +0100491 return (sysclk >> stm32_get_apb_shift(regs, APB2));
Patrice Chotard369d4832017-11-15 13:14:52 +0100492
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200493 default:
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100494 dev_err(clk->dev, "clock index %ld out of range\n", clk->id);
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200495 return -EINVAL;
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200496 }
497}
498
Patrice Chotard24e85782018-01-29 18:14:14 +0100499static ulong stm32_set_rate(struct clk *clk, ulong rate)
500{
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100501#ifdef CONFIG_VIDEO_STM32
502 struct stm32_clk *priv = dev_get_priv(clk->dev);
503 struct stm32_rcc_regs *regs = priv->base;
504 u32 pllsair_rate, pllsai_vco_rate, current_rate;
505 u32 best_div, best_diff, diff;
506 u16 div;
507 u8 best_plldivr, best_pllsaidivr;
508 u8 i, j;
509 bool found = false;
510
511 /* Only set_rate for LTDC clock is implemented */
512 if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100513 dev_err(clk->dev,
514 "set_rate not implemented for clock index %ld\n",
515 clk->id);
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100516 return 0;
517 }
518
519 if (rate == stm32_clk_get_rate(clk))
520 /* already set to requested rate */
521 return rate;
522
523 /* get the current PLLSAIR output freq */
524 pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
Dario Binacchi8dcbf812023-11-11 11:46:19 +0100525 if ((pllsair_rate % rate) == 0) {
526 best_div = pllsair_rate / rate;
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100527
Dario Binacchi8dcbf812023-11-11 11:46:19 +0100528 /* look into pllsaidivr_table if this divider is available */
529 for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
530 if (best_div == pllsaidivr_table[i]) {
531 /* set pll_saidivr with found value */
532 clrsetbits_le32(&regs->dckcfgr,
533 RCC_DCKCFGR_PLLSAIDIVR_MASK,
534 pllsaidivr_table[i] <<
535 RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
536 return rate;
537 }
538 }
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100539
540 /*
541 * As no pllsaidivr value is suitable to obtain requested freq,
542 * test all combination of pllsaidivr * pllsair and find the one
543 * which give freq closest to requested rate.
544 */
545
546 pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
547 best_diff = ULONG_MAX;
548 best_pllsaidivr = 0;
549 best_plldivr = 0;
550 /*
551 * start at index 2 of plldivr_table as divider value at index 0
552 * and 1 are 0)
553 */
554 for (i = 2; i < sizeof(plldivr_table); i++) {
555 for (j = 0; j < sizeof(pllsaidivr_table); j++) {
556 div = plldivr_table[i] * pllsaidivr_table[j];
557 current_rate = pllsai_vco_rate / div;
558 /* perfect combination is found ? */
559 if (current_rate == rate) {
560 best_pllsaidivr = j;
561 best_plldivr = i;
562 found = true;
563 break;
564 }
565
566 diff = (current_rate > rate) ?
567 current_rate - rate : rate - current_rate;
568
569 /* found a better combination ? */
570 if (diff < best_diff) {
571 best_diff = diff;
572 best_pllsaidivr = j;
573 best_plldivr = i;
574 }
575 }
576
577 if (found)
578 break;
579 }
580
581 /* Disable the SAI PLL */
582 clrbits_le32(&regs->cr, RCC_CR_PLLSAION);
583
584 /* set pll_saidivr with found value */
585 clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
586 best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
587
588 /* set pllsair with found value */
589 clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
590 plldivr_table[best_plldivr]
591 << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
592
593 /* Enable the SAI PLL */
594 setbits_le32(&regs->cr, RCC_CR_PLLSAION);
595 while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY))
596 ;
597
598 div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
599 return pllsai_vco_rate / div;
600#else
Patrice Chotard24e85782018-01-29 18:14:14 +0100601 return 0;
Patrice Chotard2cd1ed12018-02-08 17:20:50 +0100602#endif
Patrice Chotard24e85782018-01-29 18:14:14 +0100603}
604
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800605static int stm32_clk_enable(struct clk *clk)
606{
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200607 struct stm32_clk *priv = dev_get_priv(clk->dev);
608 struct stm32_rcc_regs *regs = priv->base;
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800609 u32 offset = clk->id / 32;
610 u32 bit_index = clk->id % 32;
611
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100612 dev_dbg(clk->dev, "clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
613 clk->id, offset, bit_index);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200614 setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800615
616 return 0;
617}
Toshifumi NISHINAGA65bfb9c2016-07-08 01:02:24 +0900618
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800619static int stm32_clk_probe(struct udevice *dev)
620{
Patrice Chotard22768d52017-11-15 13:14:44 +0100621 struct ofnode_phandle_args args;
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100622 struct udevice *fixed_clock_dev = NULL;
623 struct clk clk;
Patrice Chotard22768d52017-11-15 13:14:44 +0100624 int err;
625
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100626 dev_dbg(dev, "%s\n", __func__);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200627
628 struct stm32_clk *priv = dev_get_priv(dev);
629 fdt_addr_t addr;
630
Patrice Chotard1509d662017-11-15 13:14:47 +0100631 addr = dev_read_addr(dev);
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200632 if (addr == FDT_ADDR_T_NONE)
633 return -EINVAL;
634
635 priv->base = (struct stm32_rcc_regs *)addr;
Patrice Chotard7264aae2018-04-11 17:07:45 +0200636 priv->pllsaip = true;
Patrice Chotard03f10a12017-11-15 13:14:51 +0100637
638 switch (dev_get_driver_data(dev)) {
Patrice Chotard7264aae2018-04-11 17:07:45 +0200639 case STM32F42X:
640 priv->pllsaip = false;
641 /* fallback into STM32F469 case */
642 case STM32F469:
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100643 memcpy(&priv->info, &stm32f4_clk_info,
644 sizeof(struct stm32_clk_info));
Patrice Chotard03f10a12017-11-15 13:14:51 +0100645 break;
Patrice Chotard7264aae2018-04-11 17:07:45 +0200646
Patrice Chotard03f10a12017-11-15 13:14:51 +0100647 case STM32F7:
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100648 memcpy(&priv->info, &stm32f7_clk_info,
649 sizeof(struct stm32_clk_info));
Patrice Chotard03f10a12017-11-15 13:14:51 +0100650 break;
651 default:
652 return -EINVAL;
653 }
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200654
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100655 /* retrieve HSE frequency (external oscillator) */
656 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
657 &fixed_clock_dev);
658
659 if (err) {
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100660 dev_err(dev, "Can't find fixed clock (%d)", err);
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100661 return err;
662 }
663
664 err = clk_request(fixed_clock_dev, &clk);
665 if (err) {
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100666 dev_err(dev, "Can't request %s clk (%d)",
667 fixed_clock_dev->name, err);
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100668 return err;
669 }
670
671 /*
672 * set pllm factor accordingly to the external oscillator
673 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
674 * freq at 1MHz
675 * if input PLL frequency is 25Mhz, divide it by 25
676 */
677 clk.id = 0;
678 priv->hse_rate = clk_get_rate(&clk);
679
680 if (priv->hse_rate < 1000000) {
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100681 dev_err(dev, "unexpected HSE clock rate = %ld \"n",
682 priv->hse_rate);
Patrice Chotardacd97ca2018-01-18 13:39:30 +0100683 return -EINVAL;
684 }
685
686 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
687
688 if (priv->info.has_overdrive) {
Patrice Chotard1509d662017-11-15 13:14:47 +0100689 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
690 &args);
691 if (err) {
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100692 dev_err(dev, "can't find syscon device (%d)\n", err);
Patrice Chotard1509d662017-11-15 13:14:47 +0100693 return err;
694 }
Patrice Chotard22768d52017-11-15 13:14:44 +0100695
Patrice Chotard1509d662017-11-15 13:14:47 +0100696 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
697 }
Patrice Chotard22768d52017-11-15 13:14:44 +0100698
Patrice Chotardd93fc2c2017-07-18 09:29:04 +0200699 configure_clocks(dev);
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800700
701 return 0;
702}
703
Simon Glassb7ae2772017-05-18 20:09:40 -0600704static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800705{
Patrick Delaunaya57b8cd2020-11-06 19:01:46 +0100706 dev_dbg(clk->dev, "clk=%p\n", clk);
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800707
708 if (args->args_count != 2) {
Sean Andersona1b654b2021-12-01 14:26:53 -0500709 dev_dbg(clk->dev, "Invalid args_count: %d\n", args->args_count);
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800710 return -EINVAL;
711 }
712
713 if (args->args_count)
714 clk->id = args->args[1];
715 else
716 clk->id = 0;
717
718 return 0;
719}
720
721static struct clk_ops stm32_clk_ops = {
722 .of_xlate = stm32_clk_of_xlate,
723 .enable = stm32_clk_enable,
Patrice Chotard7bdf9712017-07-18 09:29:05 +0200724 .get_rate = stm32_clk_get_rate,
Patrice Chotard24e85782018-01-29 18:14:14 +0100725 .set_rate = stm32_set_rate,
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800726};
727
Patrice Chotardd4f2d202017-11-15 13:14:48 +0100728U_BOOT_DRIVER(stm32fx_clk) = {
Patrice Chotard03f10a12017-11-15 13:14:51 +0100729 .name = "stm32fx_rcc_clock",
Patrice Chotardb323de52017-09-21 10:08:09 +0200730 .id = UCLASS_CLK,
Patrice Chotardb323de52017-09-21 10:08:09 +0200731 .ops = &stm32_clk_ops,
732 .probe = stm32_clk_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700733 .priv_auto = sizeof(struct stm32_clk),
Patrice Chotardb323de52017-09-21 10:08:09 +0200734 .flags = DM_FLAG_PRE_RELOC,
Vikas Manochadaaeaab2017-02-12 10:25:45 -0800735};