| commit | d5d365558e74941a54e99bc953f63071a21f227d | [log] [tgz] |
|---|---|---|
| author | Patrice Chotard <patrice.chotard@st.com> | Fri Jan 19 18:02:40 2018 +0100 |
| committer | Tom Rini <trini@konsulko.com> | Sun Jan 28 09:39:15 2018 -0500 |
| tree | fd36d56ba6c9e344287fa52d73134b8c6842d83c | |
| parent | d24bdf14ba2b9671410828b84280aa617ddd3961 [diff] |
clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR register, available combination are : 00: PLLSAIP = 2 01: PLLSAIP = 4 10: PLLSAIP = 6 11: PLLSAIP = 8 Previously, the divider value was incorrectly set to 6. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>