| commit | cb15d287fc905f7a6e6f3fb599a2a9032741d428 | [log] [tgz] |
|---|---|---|
| author | Patrice Chotard <patrice.chotard@st.com> | Thu Feb 08 17:20:47 2018 +0100 |
| committer | Tom Rini <trini@konsulko.com> | Tue Mar 13 21:45:37 2018 -0400 |
| tree | e232ca28e0a82338535efbce219c0b77b560bd9c | |
| parent | 9490aca1a11c15c6b39455fcba83b1b714543c0a [diff] |
clk: clk_stm32f: No more need of 48Mhz from PLL_SAI Initially, 48Mhz for SDIO clock was generated from SAI pll for STM32F469 and STM32F746 SoCs, but this solution was not suitable for STM32F429 SoCs. A generic solution is to used the PLL_Q output as 48Mhz clock for all STM32F SOCs family. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>