commit e2d564ed2f306a569787d5a95817f6efc01df128
author Patrice Chotard <patrice.chotard@st.com> Thu Jan 18 14:10:05 2018 +0100
committer Tom Rini <trini@konsulko.com> Sun Jan 28 09:39:15 2018 -0500
tree 3464baa7bb585da850cb900b37bd23441bb605d1
parent b710b7f9b1bdca06e496ce411e1c0078e7b5c41b

clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()

Move SYSCFG clock setup into configure_clocks() instead of calling
clock_setup() from board file.

As this clock is only needed in case of ethernet enabled and as
both stm32f4 and stm32f7 are using the Designware ethernet IP,
we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed.

Move the RMII setup from board_early_init_f() to board_init()
to insure that RMII bit is set only when clock driver is initialized.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

drivers/clk/clk_stm32f.c

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 2187be8..8d0f9d4 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -67,8 +67,6 @@
 #define RCC_DCKCFGRX_SDMMC1SEL		BIT(28)
 #define RCC_DCKCFGR2_SDMMC2SEL		BIT(29)
 
-#define RCC_APB2ENR_SAI1EN		BIT(22)
-
 /*
  * RCC AHB1ENR specific definitions
  */
@@ -86,9 +84,9 @@
  * RCC APB2ENR specific definitions
  */
 #define RCC_APB2ENR_SYSCFGEN		BIT(14)
+#define RCC_APB2ENR_SAI1EN		BIT(22)
 
 enum periph_clock {
-	SYSCFG_CLOCK_CFG,
 	TIMER2_CLOCK_CFG,
 };
 
@@ -226,6 +224,11 @@
 	/* gate the SAI clock, needed for MMC 1&2 clocks */
 	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);
 
+#ifdef CONFIG_ETH_DESIGNWARE
+	/* gate the SYSCFG clock, needed to set RMII ethernet interface */
+	setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
+#endif
+
 	return 0;
 }
 
@@ -351,9 +354,6 @@
 void clock_setup(int peripheral)
 {
 	switch (peripheral) {
-	case SYSCFG_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
-		break;
 	case TIMER2_CLOCK_CFG:
 		setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 		break;