| commit | b6653f60fc49762171c6460fa057c59bbb334d75 | [log] [tgz] |
|---|---|---|
| author | Patrice Chotard <patrice.chotard@st.com> | Thu Oct 26 13:23:19 2017 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Fri Nov 17 07:44:13 2017 -0500 |
| tree | e274e317b778b67e276832726a2c5de4284c8240 | |
| parent | c8e7bd6666bc5878155bbdb16bf97095c66329fb [diff] |
clk: clk_stm32f7: fix PLL clock division factor Fix clock division factor initialization for RCC_PLLCFGR registers. PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared, it's a forbidden value. So update RCC_PLLCFGR using clrsetbits_le32() to set only necessary bits fields. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>