blob: 79f644a935b84128569af5fa59842445f53c8bcd [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass0bdfc3e2016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassf6de2572016-09-12 23:18:42 -06009config SPL_LIBDISK_SUPPORT
10 default y
11
Simon Glassb16c92c2016-09-12 23:18:43 -060012config SPL_LIBGENERIC_SUPPORT
13 default y
14
Simon Glassbd58f1d2016-09-12 23:18:44 -060015config SPL_MMC_SUPPORT
16 default y
17
Simon Glass0d7c7e02016-09-12 23:18:54 -060018config SPL_POWER_SUPPORT
19 default y
20
Simon Glasse076d6f2016-09-12 23:18:56 -060021config SPL_SERIAL_SUPPORT
22 default y
23
Hans de Goedef07872b2015-04-06 20:33:34 +020024# Note only one of these may be selected at a time! But hidden choices are
25# not supported by Kconfig
26config SUNXI_GEN_SUN4I
27 bool
28 ---help---
29 Select this for sunxi SoCs which have resets and clocks set up
30 as the original A10 (mach-sun4i).
31
32config SUNXI_GEN_SUN6I
33 bool
34 ---help---
35 Select this for sunxi SoCs which have sun6i like periphery, like
36 separate ahb reset control registers, custom pmic bus, new style
37 watchdog, etc.
38
39
Ian Campbelld8e69e02014-10-24 21:20:44 +010040choice
41 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020042 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010043
Ian Campbell4a24a1c2014-10-24 21:20:45 +010044config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010045 bool "sun4i (Allwinner A10)"
46 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020047 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010048 select SUPPORT_SPL
49
Ian Campbell4a24a1c2014-10-24 21:20:45 +010050config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010051 bool "sun5i (Allwinner A13)"
52 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 select SUPPORT_SPL
55
Ian Campbell4a24a1c2014-10-24 21:20:45 +010056config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010057 bool "sun6i (Allwinner A31)"
58 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080059 select CPU_V7_HAS_NONSEC
60 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090061 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020062 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020063 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080064 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010065
Ian Campbell4a24a1c2014-10-24 21:20:45 +010066config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010067 bool "sun7i (Allwinner A20)"
68 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010069 select CPU_V7_HAS_NONSEC
70 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090071 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020072 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010073 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020074 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010075
Hans de Goedef055ed62015-04-06 20:55:39 +020076config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010077 bool "sun8i (Allwinner A23)"
78 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080079 select CPU_V7_HAS_NONSEC
80 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090081 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020082 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010083 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080084 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010085
Vishnu Patekar3702f142015-03-01 23:47:48 +053086config MACH_SUN8I_A33
87 bool "sun8i (Allwinner A33)"
88 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080089 select CPU_V7_HAS_NONSEC
90 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090091 select ARCH_SUPPORT_PSCI
Vishnu Patekar3702f142015-03-01 23:47:48 +053092 select SUNXI_GEN_SUN6I
93 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080094 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +053095
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +080096config MACH_SUN8I_A83T
97 bool "sun8i (Allwinner A83T)"
98 select CPU_V7
99 select SUNXI_GEN_SUN6I
100 select SUPPORT_SPL
101
Jens Kuskef9770722015-11-17 15:12:58 +0100102config MACH_SUN8I_H3
103 bool "sun8i (Allwinner H3)"
104 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900107 select ARCH_SUPPORT_PSCI
Jens Kuskef9770722015-11-17 15:12:58 +0100108 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +0100109 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800110 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +0100111
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100112config MACH_SUN9I
113 bool "sun9i (Allwinner A80)"
114 select CPU_V7
115 select SUNXI_GEN_SUN6I
116
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800117config MACH_SUN50I
118 bool "sun50i (Allwinner A64)"
119 select ARM64
120 select SUNXI_GEN_SUN6I
121
Ian Campbelld8e69e02014-10-24 21:20:44 +0100122endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800123
Hans de Goedef055ed62015-04-06 20:55:39 +0200124# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
125config MACH_SUN8I
126 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800127 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200128
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800129config DRAM_TYPE
130 int "sunxi dram type"
131 depends on MACH_SUN8I_A83T
132 default 3
133 ---help---
134 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200135
Hans de Goede3aeaa282014-11-15 19:46:39 +0100136config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100137 int "sunxi dram clock speed"
138 default 312 if MACH_SUN6I || MACH_SUN8I
139 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100140 ---help---
141 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +0100142 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100143
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200144if MACH_SUN5I || MACH_SUN7I
145config DRAM_MBUS_CLK
146 int "sunxi mbus clock speed"
147 default 300
148 ---help---
149 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
150
151endif
152
Hans de Goede3aeaa282014-11-15 19:46:39 +0100153config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100154 int "sunxi dram zq value"
155 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
156 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100157 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100158 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100159
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200160config DRAM_ODT_EN
161 bool "sunxi dram odt enable"
162 default n if !MACH_SUN8I_A23
163 default y if MACH_SUN8I_A23
164 ---help---
165 Select this to enable dram odt (on die termination).
166
Hans de Goede59d9fc72015-01-17 14:24:55 +0100167if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
168config DRAM_EMR1
169 int "sunxi dram emr1 value"
170 default 0 if MACH_SUN4I
171 default 4 if MACH_SUN5I || MACH_SUN7I
172 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100173 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200174
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200175config DRAM_TPR3
176 hex "sunxi dram tpr3 value"
177 default 0
178 ---help---
179 Set the dram controller tpr3 parameter. This parameter configures
180 the delay on the command lane and also phase shifts, which are
181 applied for sampling incoming read data. The default value 0
182 means that no phase/delay adjustments are necessary. Properly
183 configuring this parameter increases reliability at high DRAM
184 clock speeds.
185
186config DRAM_DQS_GATING_DELAY
187 hex "sunxi dram dqs_gating_delay value"
188 default 0
189 ---help---
190 Set the dram controller dqs_gating_delay parmeter. Each byte
191 encodes the DQS gating delay for each byte lane. The delay
192 granularity is 1/4 cycle. For example, the value 0x05060606
193 means that the delay is 5 quarter-cycles for one lane (1.25
194 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
195 The default value 0 means autodetection. The results of hardware
196 autodetection are not very reliable and depend on the chip
197 temperature (sometimes producing different results on cold start
198 and warm reboot). But the accuracy of hardware autodetection
199 is usually good enough, unless running at really high DRAM
200 clocks speeds (up to 600MHz). If unsure, keep as 0.
201
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200202choice
203 prompt "sunxi dram timings"
204 default DRAM_TIMINGS_VENDOR_MAGIC
205 ---help---
206 Select the timings of the DDR3 chips.
207
208config DRAM_TIMINGS_VENDOR_MAGIC
209 bool "Magic vendor timings from Android"
210 ---help---
211 The same DRAM timings as in the Allwinner boot0 bootloader.
212
213config DRAM_TIMINGS_DDR3_1066F_1333H
214 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
215 ---help---
216 Use the timings of the standard JEDEC DDR3-1066F speed bin for
217 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
218 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
219 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
220 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
221 that down binning to DDR3-1066F is supported (because DDR3-1066F
222 uses a bit faster timings than DDR3-1333H).
223
224config DRAM_TIMINGS_DDR3_800E_1066G_1333J
225 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
226 ---help---
227 Use the timings of the slowest possible JEDEC speed bin for the
228 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
229 DDR3-800E, DDR3-1066G or DDR3-1333J.
230
231endchoice
232
Hans de Goede3aeaa282014-11-15 19:46:39 +0100233endif
234
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200235if MACH_SUN8I_A23
236config DRAM_ODT_CORRECTION
237 int "sunxi dram odt correction value"
238 default 0
239 ---help---
240 Set the dram odt correction value (range -255 - 255). In allwinner
241 fex files, this option is found in bits 8-15 of the u32 odt_en variable
242 in the [dram] section. When bit 31 of the odt_en variable is set
243 then the correction is negative. Usually the value for this is 0.
244endif
245
Iain Paton630df142015-03-28 10:26:38 +0000246config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200247 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000248 default 912000000 if MACH_SUN7I
249 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
250
Maxime Ripard2c519412014-10-03 20:16:29 +0800251config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100252 default "sun4i" if MACH_SUN4I
253 default "sun5i" if MACH_SUN5I
254 default "sun6i" if MACH_SUN6I
255 default "sun7i" if MACH_SUN7I
256 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100257 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200258 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900259
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900260config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900261 default "sunxi"
262
263config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900264 default "sunxi"
265
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200266config UART0_PORT_F
267 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200268 default n
269 ---help---
270 Repurpose the SD card slot for getting access to the UART0 serial
271 console. Primarily useful only for low level u-boot debugging on
272 tablets, where normal UART0 is difficult to access and requires
273 device disassembly and/or soldering. As the SD card can't be used
274 at the same time, the system can be only booted in the FEL mode.
275 Only enable this if you really know what you are doing.
276
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200277config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900278 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200279 default n
280 ---help---
281 Set this to enable various workarounds for old kernels, this results in
282 sub-optimal settings for newer kernels, only enable if needed.
283
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200284config MMC
285 depends on !UART0_PORT_F
286 default y if ARCH_SUNXI
287
Hans de Goede7412ef82014-10-02 20:29:26 +0200288config MMC0_CD_PIN
289 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800290 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200291 default ""
292 ---help---
293 Set the card detect pin for mmc0, leave empty to not use cd. This
294 takes a string in the format understood by sunxi_name_to_gpio, e.g.
295 PH1 for pin 1 of port H.
296
297config MMC1_CD_PIN
298 string "Card detect pin for mmc1"
299 default ""
300 ---help---
301 See MMC0_CD_PIN help text.
302
303config MMC2_CD_PIN
304 string "Card detect pin for mmc2"
305 default ""
306 ---help---
307 See MMC0_CD_PIN help text.
308
309config MMC3_CD_PIN
310 string "Card detect pin for mmc3"
311 default ""
312 ---help---
313 See MMC0_CD_PIN help text.
314
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100315config MMC1_PINS
316 string "Pins for mmc1"
317 default ""
318 ---help---
319 Set the pins used for mmc1, when applicable. This takes a string in the
320 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
321
322config MMC2_PINS
323 string "Pins for mmc2"
324 default ""
325 ---help---
326 See MMC1_PINS help text.
327
328config MMC3_PINS
329 string "Pins for mmc3"
330 default ""
331 ---help---
332 See MMC1_PINS help text.
333
Hans de Goedeaf593e42014-10-02 20:43:50 +0200334config MMC_SUNXI_SLOT_EXTRA
335 int "mmc extra slot number"
336 default -1
337 ---help---
338 sunxi builds always enable mmc0, some boards also have a second sdcard
339 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
340 support for this.
341
Hans de Goede99c9fb02016-04-01 22:39:26 +0200342config INITIAL_USB_SCAN_DELAY
343 int "delay initial usb scan by x ms to allow builtin devices to init"
344 default 0
345 ---help---
346 Some boards have on board usb devices which need longer than the
347 USB spec's 1 second to connect from board powerup. Set this config
348 option to a non 0 value to add an extra delay before the first usb
349 bus scan.
350
Hans de Goedee7b852a2015-01-07 15:26:06 +0100351config USB0_VBUS_PIN
352 string "Vbus enable pin for usb0 (otg)"
353 default ""
354 ---help---
355 Set the Vbus enable pin for usb0 (otg). This takes a string in the
356 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
357
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100358config USB0_VBUS_DET
359 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100360 default ""
361 ---help---
362 Set the Vbus detect pin for usb0 (otg). This takes a string in the
363 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
364
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200365config USB0_ID_DET
366 string "ID detect pin for usb0 (otg)"
367 default ""
368 ---help---
369 Set the ID detect pin for usb0 (otg). This takes a string in the
370 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
371
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100372config USB1_VBUS_PIN
373 string "Vbus enable pin for usb1 (ehci0)"
374 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100375 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100376 ---help---
377 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
378 a string in the format understood by sunxi_name_to_gpio, e.g.
379 PH1 for pin 1 of port H.
380
381config USB2_VBUS_PIN
382 string "Vbus enable pin for usb2 (ehci1)"
383 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100384 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100385 ---help---
386 See USB1_VBUS_PIN help text.
387
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100388config USB3_VBUS_PIN
389 string "Vbus enable pin for usb3 (ehci2)"
390 default ""
391 ---help---
392 See USB1_VBUS_PIN help text.
393
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200394config I2C0_ENABLE
395 bool "Enable I2C/TWI controller 0"
396 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
397 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200398 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200399 ---help---
400 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
401 its clock and setting up the bus. This is especially useful on devices
402 with slaves connected to the bus or with pins exposed through e.g. an
403 expansion port/header.
404
405config I2C1_ENABLE
406 bool "Enable I2C/TWI controller 1"
407 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200408 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200409 ---help---
410 See I2C0_ENABLE help text.
411
412config I2C2_ENABLE
413 bool "Enable I2C/TWI controller 2"
414 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200415 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200416 ---help---
417 See I2C0_ENABLE help text.
418
419if MACH_SUN6I || MACH_SUN7I
420config I2C3_ENABLE
421 bool "Enable I2C/TWI controller 3"
422 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200423 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200424 ---help---
425 See I2C0_ENABLE help text.
426endif
427
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100428if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100429config R_I2C_ENABLE
430 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100431 # This is used for the pmic on H3
432 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200433 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100434 ---help---
435 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100436endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100437
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200438if MACH_SUN7I
439config I2C4_ENABLE
440 bool "Enable I2C/TWI controller 4"
441 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200442 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200443 ---help---
444 See I2C0_ENABLE help text.
445endif
446
Hans de Goede3ae1d132015-04-25 17:25:14 +0200447config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900448 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200449 default n
450 ---help---
451 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
452
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200453config VIDEO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900454 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywara8f977272016-09-05 01:32:40 +0100455 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200456 default y
457 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100458 Say Y here to add support for using a cfb console on the HDMI, LCD
459 or VGA output found on most sunxi devices. See doc/README.video for
460 info on how to select the video output and mode.
461
Hans de Goedee9544592014-12-23 23:04:35 +0100462config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900463 bool "HDMI output support"
Hans de Goedee9544592014-12-23 23:04:35 +0100464 depends on VIDEO && !MACH_SUN8I
465 default y
466 ---help---
467 Say Y here to add support for outputting video over HDMI.
468
Hans de Goede260f5202014-12-25 13:58:06 +0100469config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900470 bool "VGA output support"
Hans de Goede260f5202014-12-25 13:58:06 +0100471 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
472 default n
473 ---help---
474 Say Y here to add support for outputting video over VGA.
475
Hans de Goedeac1633c2014-12-24 12:17:07 +0100476config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900477 bool "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800478 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100479 default n
480 ---help---
481 Say Y here to add support for external DACs connected to the parallel
482 LCD interface driving a VGA connector, such as found on the
483 Olimex A13 boards.
484
Hans de Goede18366f72015-01-25 15:33:07 +0100485config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900486 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100487 depends on VIDEO_VGA_VIA_LCD
488 default n
489 ---help---
490 Say Y here if you've a board which uses opendrain drivers for the vga
491 hsync and vsync signals. Opendrain drivers cannot generate steep enough
492 positive edges for a stable video output, so on boards with opendrain
493 drivers the sync signals must always be active high.
494
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800495config VIDEO_VGA_EXTERNAL_DAC_EN
496 string "LCD panel power enable pin"
497 depends on VIDEO_VGA_VIA_LCD
498 default ""
499 ---help---
500 Set the enable pin for the external VGA DAC. This takes a string in the
501 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
502
Hans de Goedec06e00e2015-08-03 19:20:26 +0200503config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900504 bool "Composite video output support"
Hans de Goedec06e00e2015-08-03 19:20:26 +0200505 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
506 default n
507 ---help---
508 Say Y here to add support for outputting composite video.
509
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100510config VIDEO_LCD_MODE
511 string "LCD panel timing details"
512 depends on VIDEO
513 default ""
514 ---help---
515 LCD panel timing details string, leave empty if there is no LCD panel.
516 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
517 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200518 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100519
Hans de Goede481b6642015-01-13 13:21:46 +0100520config VIDEO_LCD_DCLK_PHASE
521 int "LCD panel display clock phase"
522 depends on VIDEO
523 default 1
524 ---help---
525 Select LCD panel display clock phase shift, range 0-3.
526
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100527config VIDEO_LCD_POWER
528 string "LCD panel power enable pin"
529 depends on VIDEO
530 default ""
531 ---help---
532 Set the power enable pin for the LCD panel. This takes a string in the
533 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
534
Hans de Goedece9e3322015-02-16 17:26:41 +0100535config VIDEO_LCD_RESET
536 string "LCD panel reset pin"
537 depends on VIDEO
538 default ""
539 ---help---
540 Set the reset pin for the LCD panel. This takes a string in the format
541 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
542
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100543config VIDEO_LCD_BL_EN
544 string "LCD panel backlight enable pin"
545 depends on VIDEO
546 default ""
547 ---help---
548 Set the backlight enable pin for the LCD panel. This takes a string in the
549 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
550 port H.
551
552config VIDEO_LCD_BL_PWM
553 string "LCD panel backlight pwm pin"
554 depends on VIDEO
555 default ""
556 ---help---
557 Set the backlight pwm pin for the LCD panel. This takes a string in the
558 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200559
Hans de Goede2d5d3022015-01-22 21:02:42 +0100560config VIDEO_LCD_BL_PWM_ACTIVE_LOW
561 bool "LCD panel backlight pwm is inverted"
562 depends on VIDEO
563 default y
564 ---help---
565 Set this if the backlight pwm output is active low.
566
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100567config VIDEO_LCD_PANEL_I2C
568 bool "LCD panel needs to be configured via i2c"
569 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100570 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200571 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100572 ---help---
573 Say y here if the LCD panel needs to be configured via i2c. This
574 will add a bitbang i2c controller using gpios to talk to the LCD.
575
576config VIDEO_LCD_PANEL_I2C_SDA
577 string "LCD panel i2c interface SDA pin"
578 depends on VIDEO_LCD_PANEL_I2C
579 default "PG12"
580 ---help---
581 Set the SDA pin for the LCD i2c interface. This takes a string in the
582 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
583
584config VIDEO_LCD_PANEL_I2C_SCL
585 string "LCD panel i2c interface SCL pin"
586 depends on VIDEO_LCD_PANEL_I2C
587 default "PG10"
588 ---help---
589 Set the SCL pin for the LCD i2c interface. This takes a string in the
590 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
591
Hans de Goede797a0f52015-01-01 22:04:34 +0100592
593# Note only one of these may be selected at a time! But hidden choices are
594# not supported by Kconfig
595config VIDEO_LCD_IF_PARALLEL
596 bool
597
598config VIDEO_LCD_IF_LVDS
599 bool
600
601
602choice
603 prompt "LCD panel support"
604 depends on VIDEO
605 ---help---
606 Select which type of LCD panel to support.
607
608config VIDEO_LCD_PANEL_PARALLEL
609 bool "Generic parallel interface LCD panel"
610 select VIDEO_LCD_IF_PARALLEL
611
612config VIDEO_LCD_PANEL_LVDS
613 bool "Generic lvds interface LCD panel"
614 select VIDEO_LCD_IF_LVDS
615
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200616config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
617 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
618 select VIDEO_LCD_SSD2828
619 select VIDEO_LCD_IF_PARALLEL
620 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200621 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
622
623config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
624 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
625 select VIDEO_LCD_ANX9804
626 select VIDEO_LCD_IF_PARALLEL
627 select VIDEO_LCD_PANEL_I2C
628 ---help---
629 Select this for eDP LCD panels with 4 lanes running at 1.62G,
630 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200631
Hans de Goede743fb9552015-01-20 09:23:36 +0100632config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
633 bool "Hitachi tx18d42vm LCD panel"
634 select VIDEO_LCD_HITACHI_TX18D42VM
635 select VIDEO_LCD_IF_LVDS
636 ---help---
637 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
638
Hans de Goede613dade2015-02-16 17:49:47 +0100639config VIDEO_LCD_TL059WV5C0
640 bool "tl059wv5c0 LCD panel"
641 select VIDEO_LCD_PANEL_I2C
642 select VIDEO_LCD_IF_PARALLEL
643 ---help---
644 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
645 Aigo M60/M608/M606 tablets.
646
Hans de Goede797a0f52015-01-01 22:04:34 +0100647endchoice
648
649
Hans de Goedebf880fe2015-01-25 12:10:48 +0100650config GMAC_TX_DELAY
651 int "GMAC Transmit Clock Delay Chain"
652 default 0
653 ---help---
654 Set the GMAC Transmit Clock Delay Chain value.
655
Hans de Goede66ab79d2015-09-13 13:02:48 +0200656config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200657 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200658 default 0x2fe00000 if MACH_SUN9I
659
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900660endif