blob: 323e972932c92025e66805fc09a648f0b755c682 [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goedef07872b2015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbelld8e69e02014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020021 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010022
Ian Campbell4a24a1c2014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbell4a24a1c2014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbell4a24a1c2014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010043
Ian Campbell4a24a1c2014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010052
Hans de Goedef055ed62015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020058 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010059 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080060 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010061
Vishnu Patekar3702f142015-03-01 23:47:48 +053062config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Vishnu Patekar3702f142015-03-01 23:47:48 +053067 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +053070
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +080071config MACH_SUN8I_A83T
72 bool "sun8i (Allwinner A83T)"
73 select CPU_V7
74 select SUNXI_GEN_SUN6I
75 select SUPPORT_SPL
76
Jens Kuskef9770722015-11-17 15:12:58 +010077config MACH_SUN8I_H3
78 bool "sun8i (Allwinner H3)"
79 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +080080 select CPU_V7_HAS_NONSEC
81 select CPU_V7_HAS_VIRT
Jens Kuskef9770722015-11-17 15:12:58 +010082 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +010083 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +080084 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +010085
Hans de Goede7bfe2bb2015-01-13 19:25:06 +010086config MACH_SUN9I
87 bool "sun9i (Allwinner A80)"
88 select CPU_V7
89 select SUNXI_GEN_SUN6I
90
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +080091config MACH_SUN50I
92 bool "sun50i (Allwinner A64)"
93 select ARM64
94 select SUNXI_GEN_SUN6I
95
Ian Campbelld8e69e02014-10-24 21:20:44 +010096endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +080097
Hans de Goedef055ed62015-04-06 20:55:39 +020098# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
99config MACH_SUN8I
100 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800101 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200102
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800103config DRAM_TYPE
104 int "sunxi dram type"
105 depends on MACH_SUN8I_A83T
106 default 3
107 ---help---
108 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200109
Hans de Goede3aeaa282014-11-15 19:46:39 +0100110config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100111 int "sunxi dram clock speed"
112 default 312 if MACH_SUN6I || MACH_SUN8I
113 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100114 ---help---
115 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +0100116 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100117
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200118if MACH_SUN5I || MACH_SUN7I
119config DRAM_MBUS_CLK
120 int "sunxi mbus clock speed"
121 default 300
122 ---help---
123 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
124
125endif
126
Hans de Goede3aeaa282014-11-15 19:46:39 +0100127config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100128 int "sunxi dram zq value"
129 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
130 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100131 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100132 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100133
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200134config DRAM_ODT_EN
135 bool "sunxi dram odt enable"
136 default n if !MACH_SUN8I_A23
137 default y if MACH_SUN8I_A23
138 ---help---
139 Select this to enable dram odt (on die termination).
140
Hans de Goede59d9fc72015-01-17 14:24:55 +0100141if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
142config DRAM_EMR1
143 int "sunxi dram emr1 value"
144 default 0 if MACH_SUN4I
145 default 4 if MACH_SUN5I || MACH_SUN7I
146 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100147 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200148
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200149config DRAM_TPR3
150 hex "sunxi dram tpr3 value"
151 default 0
152 ---help---
153 Set the dram controller tpr3 parameter. This parameter configures
154 the delay on the command lane and also phase shifts, which are
155 applied for sampling incoming read data. The default value 0
156 means that no phase/delay adjustments are necessary. Properly
157 configuring this parameter increases reliability at high DRAM
158 clock speeds.
159
160config DRAM_DQS_GATING_DELAY
161 hex "sunxi dram dqs_gating_delay value"
162 default 0
163 ---help---
164 Set the dram controller dqs_gating_delay parmeter. Each byte
165 encodes the DQS gating delay for each byte lane. The delay
166 granularity is 1/4 cycle. For example, the value 0x05060606
167 means that the delay is 5 quarter-cycles for one lane (1.25
168 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
169 The default value 0 means autodetection. The results of hardware
170 autodetection are not very reliable and depend on the chip
171 temperature (sometimes producing different results on cold start
172 and warm reboot). But the accuracy of hardware autodetection
173 is usually good enough, unless running at really high DRAM
174 clocks speeds (up to 600MHz). If unsure, keep as 0.
175
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200176choice
177 prompt "sunxi dram timings"
178 default DRAM_TIMINGS_VENDOR_MAGIC
179 ---help---
180 Select the timings of the DDR3 chips.
181
182config DRAM_TIMINGS_VENDOR_MAGIC
183 bool "Magic vendor timings from Android"
184 ---help---
185 The same DRAM timings as in the Allwinner boot0 bootloader.
186
187config DRAM_TIMINGS_DDR3_1066F_1333H
188 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
189 ---help---
190 Use the timings of the standard JEDEC DDR3-1066F speed bin for
191 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
192 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
193 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
194 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
195 that down binning to DDR3-1066F is supported (because DDR3-1066F
196 uses a bit faster timings than DDR3-1333H).
197
198config DRAM_TIMINGS_DDR3_800E_1066G_1333J
199 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
200 ---help---
201 Use the timings of the slowest possible JEDEC speed bin for the
202 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
203 DDR3-800E, DDR3-1066G or DDR3-1333J.
204
205endchoice
206
Hans de Goede3aeaa282014-11-15 19:46:39 +0100207endif
208
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200209if MACH_SUN8I_A23
210config DRAM_ODT_CORRECTION
211 int "sunxi dram odt correction value"
212 default 0
213 ---help---
214 Set the dram odt correction value (range -255 - 255). In allwinner
215 fex files, this option is found in bits 8-15 of the u32 odt_en variable
216 in the [dram] section. When bit 31 of the odt_en variable is set
217 then the correction is negative. Usually the value for this is 0.
218endif
219
Iain Paton630df142015-03-28 10:26:38 +0000220config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200221 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000222 default 912000000 if MACH_SUN7I
223 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
224
Maxime Ripard2c519412014-10-03 20:16:29 +0800225config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100226 default "sun4i" if MACH_SUN4I
227 default "sun5i" if MACH_SUN5I
228 default "sun6i" if MACH_SUN6I
229 default "sun7i" if MACH_SUN7I
230 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100231 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200232 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900233
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900234config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900235 default "sunxi"
236
237config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900238 default "sunxi"
239
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200240config UART0_PORT_F
241 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200242 default n
243 ---help---
244 Repurpose the SD card slot for getting access to the UART0 serial
245 console. Primarily useful only for low level u-boot debugging on
246 tablets, where normal UART0 is difficult to access and requires
247 device disassembly and/or soldering. As the SD card can't be used
248 at the same time, the system can be only booted in the FEL mode.
249 Only enable this if you really know what you are doing.
250
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200251config OLD_SUNXI_KERNEL_COMPAT
252 boolean "Enable workarounds for booting old kernels"
253 default n
254 ---help---
255 Set this to enable various workarounds for old kernels, this results in
256 sub-optimal settings for newer kernels, only enable if needed.
257
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200258config MMC
259 depends on !UART0_PORT_F
260 default y if ARCH_SUNXI
261
Hans de Goede7412ef82014-10-02 20:29:26 +0200262config MMC0_CD_PIN
263 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800264 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200265 default ""
266 ---help---
267 Set the card detect pin for mmc0, leave empty to not use cd. This
268 takes a string in the format understood by sunxi_name_to_gpio, e.g.
269 PH1 for pin 1 of port H.
270
271config MMC1_CD_PIN
272 string "Card detect pin for mmc1"
273 default ""
274 ---help---
275 See MMC0_CD_PIN help text.
276
277config MMC2_CD_PIN
278 string "Card detect pin for mmc2"
279 default ""
280 ---help---
281 See MMC0_CD_PIN help text.
282
283config MMC3_CD_PIN
284 string "Card detect pin for mmc3"
285 default ""
286 ---help---
287 See MMC0_CD_PIN help text.
288
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100289config MMC1_PINS
290 string "Pins for mmc1"
291 default ""
292 ---help---
293 Set the pins used for mmc1, when applicable. This takes a string in the
294 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
295
296config MMC2_PINS
297 string "Pins for mmc2"
298 default ""
299 ---help---
300 See MMC1_PINS help text.
301
302config MMC3_PINS
303 string "Pins for mmc3"
304 default ""
305 ---help---
306 See MMC1_PINS help text.
307
Hans de Goedeaf593e42014-10-02 20:43:50 +0200308config MMC_SUNXI_SLOT_EXTRA
309 int "mmc extra slot number"
310 default -1
311 ---help---
312 sunxi builds always enable mmc0, some boards also have a second sdcard
313 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
314 support for this.
315
Hans de Goede99c9fb02016-04-01 22:39:26 +0200316config INITIAL_USB_SCAN_DELAY
317 int "delay initial usb scan by x ms to allow builtin devices to init"
318 default 0
319 ---help---
320 Some boards have on board usb devices which need longer than the
321 USB spec's 1 second to connect from board powerup. Set this config
322 option to a non 0 value to add an extra delay before the first usb
323 bus scan.
324
Hans de Goedee7b852a2015-01-07 15:26:06 +0100325config USB0_VBUS_PIN
326 string "Vbus enable pin for usb0 (otg)"
327 default ""
328 ---help---
329 Set the Vbus enable pin for usb0 (otg). This takes a string in the
330 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
331
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100332config USB0_VBUS_DET
333 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100334 default ""
335 ---help---
336 Set the Vbus detect pin for usb0 (otg). This takes a string in the
337 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
338
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200339config USB0_ID_DET
340 string "ID detect pin for usb0 (otg)"
341 default ""
342 ---help---
343 Set the ID detect pin for usb0 (otg). This takes a string in the
344 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
345
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100346config USB1_VBUS_PIN
347 string "Vbus enable pin for usb1 (ehci0)"
348 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100349 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100350 ---help---
351 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
352 a string in the format understood by sunxi_name_to_gpio, e.g.
353 PH1 for pin 1 of port H.
354
355config USB2_VBUS_PIN
356 string "Vbus enable pin for usb2 (ehci1)"
357 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100358 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100359 ---help---
360 See USB1_VBUS_PIN help text.
361
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100362config USB3_VBUS_PIN
363 string "Vbus enable pin for usb3 (ehci2)"
364 default ""
365 ---help---
366 See USB1_VBUS_PIN help text.
367
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200368config I2C0_ENABLE
369 bool "Enable I2C/TWI controller 0"
370 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
371 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200372 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200373 ---help---
374 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
375 its clock and setting up the bus. This is especially useful on devices
376 with slaves connected to the bus or with pins exposed through e.g. an
377 expansion port/header.
378
379config I2C1_ENABLE
380 bool "Enable I2C/TWI controller 1"
381 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200382 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200383 ---help---
384 See I2C0_ENABLE help text.
385
386config I2C2_ENABLE
387 bool "Enable I2C/TWI controller 2"
388 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200389 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200390 ---help---
391 See I2C0_ENABLE help text.
392
393if MACH_SUN6I || MACH_SUN7I
394config I2C3_ENABLE
395 bool "Enable I2C/TWI controller 3"
396 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200397 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200398 ---help---
399 See I2C0_ENABLE help text.
400endif
401
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100402if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100403config R_I2C_ENABLE
404 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100405 # This is used for the pmic on H3
406 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200407 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100408 ---help---
409 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100410endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100411
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200412if MACH_SUN7I
413config I2C4_ENABLE
414 bool "Enable I2C/TWI controller 4"
415 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200416 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200417 ---help---
418 See I2C0_ENABLE help text.
419endif
420
Hans de Goede3ae1d132015-04-25 17:25:14 +0200421config AXP_GPIO
422 boolean "Enable support for gpio-s on axp PMICs"
423 default n
424 ---help---
425 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
426
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200427config VIDEO
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100428 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Chen-Yu Tsai40aa3d52016-05-02 10:28:09 +0800429 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200430 default y
431 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100432 Say Y here to add support for using a cfb console on the HDMI, LCD
433 or VGA output found on most sunxi devices. See doc/README.video for
434 info on how to select the video output and mode.
435
Hans de Goedee9544592014-12-23 23:04:35 +0100436config VIDEO_HDMI
437 boolean "HDMI output support"
438 depends on VIDEO && !MACH_SUN8I
439 default y
440 ---help---
441 Say Y here to add support for outputting video over HDMI.
442
Hans de Goede260f5202014-12-25 13:58:06 +0100443config VIDEO_VGA
444 boolean "VGA output support"
445 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
446 default n
447 ---help---
448 Say Y here to add support for outputting video over VGA.
449
Hans de Goedeac1633c2014-12-24 12:17:07 +0100450config VIDEO_VGA_VIA_LCD
451 boolean "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800452 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100453 default n
454 ---help---
455 Say Y here to add support for external DACs connected to the parallel
456 LCD interface driving a VGA connector, such as found on the
457 Olimex A13 boards.
458
Hans de Goede18366f72015-01-25 15:33:07 +0100459config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
460 boolean "Force sync active high for VGA via LCD controller support"
461 depends on VIDEO_VGA_VIA_LCD
462 default n
463 ---help---
464 Say Y here if you've a board which uses opendrain drivers for the vga
465 hsync and vsync signals. Opendrain drivers cannot generate steep enough
466 positive edges for a stable video output, so on boards with opendrain
467 drivers the sync signals must always be active high.
468
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800469config VIDEO_VGA_EXTERNAL_DAC_EN
470 string "LCD panel power enable pin"
471 depends on VIDEO_VGA_VIA_LCD
472 default ""
473 ---help---
474 Set the enable pin for the external VGA DAC. This takes a string in the
475 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
476
Hans de Goedec06e00e2015-08-03 19:20:26 +0200477config VIDEO_COMPOSITE
478 boolean "Composite video output support"
479 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
480 default n
481 ---help---
482 Say Y here to add support for outputting composite video.
483
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100484config VIDEO_LCD_MODE
485 string "LCD panel timing details"
486 depends on VIDEO
487 default ""
488 ---help---
489 LCD panel timing details string, leave empty if there is no LCD panel.
490 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
491 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200492 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100493
Hans de Goede481b6642015-01-13 13:21:46 +0100494config VIDEO_LCD_DCLK_PHASE
495 int "LCD panel display clock phase"
496 depends on VIDEO
497 default 1
498 ---help---
499 Select LCD panel display clock phase shift, range 0-3.
500
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100501config VIDEO_LCD_POWER
502 string "LCD panel power enable pin"
503 depends on VIDEO
504 default ""
505 ---help---
506 Set the power enable pin for the LCD panel. This takes a string in the
507 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
508
Hans de Goedece9e3322015-02-16 17:26:41 +0100509config VIDEO_LCD_RESET
510 string "LCD panel reset pin"
511 depends on VIDEO
512 default ""
513 ---help---
514 Set the reset pin for the LCD panel. This takes a string in the format
515 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
516
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100517config VIDEO_LCD_BL_EN
518 string "LCD panel backlight enable pin"
519 depends on VIDEO
520 default ""
521 ---help---
522 Set the backlight enable pin for the LCD panel. This takes a string in the
523 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
524 port H.
525
526config VIDEO_LCD_BL_PWM
527 string "LCD panel backlight pwm pin"
528 depends on VIDEO
529 default ""
530 ---help---
531 Set the backlight pwm pin for the LCD panel. This takes a string in the
532 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200533
Hans de Goede2d5d3022015-01-22 21:02:42 +0100534config VIDEO_LCD_BL_PWM_ACTIVE_LOW
535 bool "LCD panel backlight pwm is inverted"
536 depends on VIDEO
537 default y
538 ---help---
539 Set this if the backlight pwm output is active low.
540
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100541config VIDEO_LCD_PANEL_I2C
542 bool "LCD panel needs to be configured via i2c"
543 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100544 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200545 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100546 ---help---
547 Say y here if the LCD panel needs to be configured via i2c. This
548 will add a bitbang i2c controller using gpios to talk to the LCD.
549
550config VIDEO_LCD_PANEL_I2C_SDA
551 string "LCD panel i2c interface SDA pin"
552 depends on VIDEO_LCD_PANEL_I2C
553 default "PG12"
554 ---help---
555 Set the SDA pin for the LCD i2c interface. This takes a string in the
556 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
557
558config VIDEO_LCD_PANEL_I2C_SCL
559 string "LCD panel i2c interface SCL pin"
560 depends on VIDEO_LCD_PANEL_I2C
561 default "PG10"
562 ---help---
563 Set the SCL pin for the LCD i2c interface. This takes a string in the
564 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
565
Hans de Goede797a0f52015-01-01 22:04:34 +0100566
567# Note only one of these may be selected at a time! But hidden choices are
568# not supported by Kconfig
569config VIDEO_LCD_IF_PARALLEL
570 bool
571
572config VIDEO_LCD_IF_LVDS
573 bool
574
575
576choice
577 prompt "LCD panel support"
578 depends on VIDEO
579 ---help---
580 Select which type of LCD panel to support.
581
582config VIDEO_LCD_PANEL_PARALLEL
583 bool "Generic parallel interface LCD panel"
584 select VIDEO_LCD_IF_PARALLEL
585
586config VIDEO_LCD_PANEL_LVDS
587 bool "Generic lvds interface LCD panel"
588 select VIDEO_LCD_IF_LVDS
589
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200590config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
591 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
592 select VIDEO_LCD_SSD2828
593 select VIDEO_LCD_IF_PARALLEL
594 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200595 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
596
597config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
598 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
599 select VIDEO_LCD_ANX9804
600 select VIDEO_LCD_IF_PARALLEL
601 select VIDEO_LCD_PANEL_I2C
602 ---help---
603 Select this for eDP LCD panels with 4 lanes running at 1.62G,
604 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200605
Hans de Goede743fb9552015-01-20 09:23:36 +0100606config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
607 bool "Hitachi tx18d42vm LCD panel"
608 select VIDEO_LCD_HITACHI_TX18D42VM
609 select VIDEO_LCD_IF_LVDS
610 ---help---
611 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
612
Hans de Goede613dade2015-02-16 17:49:47 +0100613config VIDEO_LCD_TL059WV5C0
614 bool "tl059wv5c0 LCD panel"
615 select VIDEO_LCD_PANEL_I2C
616 select VIDEO_LCD_IF_PARALLEL
617 ---help---
618 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
619 Aigo M60/M608/M606 tablets.
620
Hans de Goede797a0f52015-01-01 22:04:34 +0100621endchoice
622
623
Hans de Goedebf880fe2015-01-25 12:10:48 +0100624config GMAC_TX_DELAY
625 int "GMAC Transmit Clock Delay Chain"
626 default 0
627 ---help---
628 Set the GMAC Transmit Clock Delay Chain value.
629
Hans de Goede66ab79d2015-09-13 13:02:48 +0200630config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200631 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200632 default 0x2fe00000 if MACH_SUN9I
633
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900634endif