blob: 733a8de4fb83b70e7912bae22ac3ce5bbfd1e34c [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton32464372016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +010010
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergerf0699602015-05-12 14:46:23 -050013 optional
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090014
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090015config TARGET_MALTA
16 bool "Support malta"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020017 select HAS_FIXED_TIMER_FREQUENCY
Daniel Schwierzeck45f78be2021-07-15 20:54:01 +020018 select BOARD_EARLY_INIT_R
Paul Burtona31a3df2016-05-17 07:43:28 +010019 select DM
20 select DM_SERIAL
Simon Glass3933d292021-08-01 18:54:44 -060021 select PCI
Paul Burton8d6600b2016-01-29 13:54:52 +000022 select DYNAMIC_IO_PORT_BASE
Paul Burton59a4c8b2016-09-21 11:18:56 +010023 select MIPS_CM
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +020024 select MIPS_INSERT_BOOT_CONFIG
Tom Rini3ef67ae2021-08-26 11:47:59 -040025 select SYS_CACHE_SHIFT_6
Paul Burton59a4c8b2016-09-21 11:18:56 +010026 select MIPS_L2_CACHE
Paul Burtona31a3df2016-05-17 07:43:28 +010027 select OF_CONTROL
28 select OF_ISA_BUS
Daniel Schwierzeck45f78be2021-07-15 20:54:01 +020029 select PCI_MAP_SYSTEM_MEMORY
Michal Simek84f3dec2018-07-23 15:55:13 +020030 select ROM_EXCEPTION_VECTORS
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +010031 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +010032 select SUPPORTS_CPU_MIPS32_R1
33 select SUPPORTS_CPU_MIPS32_R2
Paul Burton1c10e0d2016-05-16 10:52:14 +010034 select SUPPORTS_CPU_MIPS32_R6
Paul Burton825cfbd2016-05-26 14:49:36 +010035 select SUPPORTS_CPU_MIPS64_R1
36 select SUPPORTS_CPU_MIPS64_R2
37 select SUPPORTS_CPU_MIPS64_R6
Michal Simek84f3dec2018-07-23 15:55:13 +020038 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +010039 select SWAP_IO_SPACE
Michal Simek2e7c8192018-07-23 15:55:14 +020040 imply CMD_DM
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090041
Wills Wang833a1a82016-03-16 16:59:52 +080042config ARCH_ATH79
43 bool "Support QCA/Atheros ath79"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020044 select HAS_FIXED_TIMER_FREQUENCY
Wills Wang833a1a82016-03-16 16:59:52 +080045 select DM
Michal Simek84f3dec2018-07-23 15:55:13 +020046 select OF_CONTROL
Michal Simek2e7c8192018-07-23 15:55:14 +020047 imply CMD_DM
Wills Wang833a1a82016-03-16 16:59:52 +080048
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010049config ARCH_MSCC
50 bool "Support MSCC VCore-III"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020051 select HAS_FIXED_TIMER_FREQUENCY
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010052 select OF_CONTROL
53 select DM
54
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020055config ARCH_BMIPS
56 bool "Support BMIPS SoCs"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020057 select HAS_FIXED_TIMER_FREQUENCY
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020058 select CLK
59 select CPU
Michal Simek84f3dec2018-07-23 15:55:13 +020060 select DM
61 select OF_CONTROL
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020062 select RAM
63 select SYSRESET
Michal Simek2e7c8192018-07-23 15:55:14 +020064 imply CMD_DM
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020065
developer89f051b2019-04-30 11:13:58 +080066config ARCH_MTMIPS
67 bool "Support MediaTek MIPS platforms"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020068 select HAS_FIXED_TIMER_FREQUENCY
developer591826e2019-09-25 17:45:43 +080069 select CLK
Stefan Roese65da15e2018-09-05 15:12:35 +020070 imply CMD_DM
71 select DISPLAY_CPUINFO
72 select DM
Stefan Roese8bbb6bf2018-10-09 08:59:09 +020073 imply DM_GPIO
developer591826e2019-09-25 17:45:43 +080074 select DM_RESET
Stefan Roese65da15e2018-09-05 15:12:35 +020075 select DM_SERIAL
developer591826e2019-09-25 17:45:43 +080076 select PINCTRL
77 select PINMUX
78 select PINCONF
79 select RESET_MTMIPS
Tom Riniddb1ec12024-01-10 13:46:10 -050080 imply MTD
Stefan Roese65da15e2018-09-05 15:12:35 +020081 imply DM_SPI
82 imply DM_SPI_FLASH
Stefan Roese17679e42019-05-28 08:11:37 +020083 select LAST_STAGE_INIT
Stefan Roese65da15e2018-09-05 15:12:35 +020084 select MIPS_TUNE_24KC
85 select OF_CONTROL
86 select ROM_EXCEPTION_VECTORS
87 select SUPPORTS_CPU_MIPS32_R1
88 select SUPPORTS_CPU_MIPS32_R2
89 select SUPPORTS_LITTLE_ENDIAN
developer19d572e2020-04-21 09:28:47 +020090 select SUPPORT_SPL
Stefan Roese65da15e2018-09-05 15:12:35 +020091
Paul Burton96c68472018-12-16 19:25:22 -030092config ARCH_JZ47XX
93 bool "Support Ingenic JZ47xx"
94 select SUPPORT_SPL
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020095 select HAS_FIXED_TIMER_FREQUENCY
Paul Burton96c68472018-12-16 19:25:22 -030096 select OF_CONTROL
97 select DM
98
Aaron Williamsb2ea8182020-06-30 12:08:56 +020099config ARCH_OCTEON
100 bool "Support Marvell Octeon CN7xxx platforms"
Stefan Roese59735ef2022-04-07 09:11:46 +0200101 select ARCH_EARLY_INIT_R
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200102 select CPU_CAVIUM_OCTEON
103 select DISPLAY_CPUINFO
104 select DMA_ADDR_T_64BIT
105 select DM
Stefan Roese67b9edb2020-07-30 13:56:21 +0200106 select DM_GPIO
107 select DM_I2C
108 select DM_SERIAL
109 select DM_SPI
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200110 select MIPS_L2_CACHE
Stefan Roese15ba8022020-06-30 12:33:17 +0200111 select MIPS_MACH_EARLY_INIT
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200112 select MIPS_TUNE_OCTEON3
Tom Riniddb1ec12024-01-10 13:46:10 -0500113 select MTD
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200114 select ROM_EXCEPTION_VECTORS
115 select SUPPORTS_BIG_ENDIAN
116 select SUPPORTS_CPU_MIPS64_OCTEON
117 select PHYS_64BIT
118 select OF_CONTROL
119 select OF_LIVE
120 imply CMD_DM
121
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530122config MACH_PIC32
123 bool "Support Microchip PIC32"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200124 select HAS_FIXED_TIMER_FREQUENCY
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530125 select DM
Tom Rini7d3684a2023-01-16 15:46:49 -0500126 select DM_EVENT
Michal Simek84f3dec2018-07-23 15:55:13 +0200127 select OF_CONTROL
Michal Simek2e7c8192018-07-23 15:55:14 +0200128 imply CMD_DM
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530129
Paul Burtonf5de32a2016-09-08 07:47:39 +0100130config TARGET_BOSTON
131 bool "Support Boston"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200132 select HAS_FIXED_TIMER_FREQUENCY
Paul Burtonf5de32a2016-09-08 07:47:39 +0100133 select DM
134 select DM_SERIAL
Paul Burtonf5de32a2016-09-08 07:47:39 +0100135 select MIPS_CM
Tom Rini3ef67ae2021-08-26 11:47:59 -0400136 select SYS_CACHE_SHIFT_6
Paul Burtonf5de32a2016-09-08 07:47:39 +0100137 select MIPS_L2_CACHE
Paul Burtona315bcd2017-04-30 21:22:42 +0200138 select OF_BOARD_SETUP
Michal Simek84f3dec2018-07-23 15:55:13 +0200139 select OF_CONTROL
140 select ROM_EXCEPTION_VECTORS
Paul Burtonf5de32a2016-09-08 07:47:39 +0100141 select SUPPORTS_BIG_ENDIAN
Paul Burtonf5de32a2016-09-08 07:47:39 +0100142 select SUPPORTS_CPU_MIPS32_R1
143 select SUPPORTS_CPU_MIPS32_R2
144 select SUPPORTS_CPU_MIPS32_R6
145 select SUPPORTS_CPU_MIPS64_R1
146 select SUPPORTS_CPU_MIPS64_R2
147 select SUPPORTS_CPU_MIPS64_R6
Michal Simek84f3dec2018-07-23 15:55:13 +0200148 select SUPPORTS_LITTLE_ENDIAN
Jiaxun Yang4d47b8c2024-05-17 19:14:59 +0100149 imply OF_UPSTREAM
Jiaxun Yang40ecb902024-05-17 19:14:55 +0100150 imply BOOTSTD_FULL
151 imply CLK
152 imply CLK_BOSTON
Michal Simek2e7c8192018-07-23 15:55:14 +0200153 imply CMD_DM
Jiaxun Yang40ecb902024-05-17 19:14:55 +0100154 imply AHCI
155 imply AHCI_PCI
156 imply CFI_FLASH
157 imply MTD_NOR_FLASH
158 imply MMC
159 imply MMC_PCI
160 imply MMC_SDHCI
161 imply MMC_SDHCI_SDMA
162 imply PCH_GBE
163 imply PCI
164 imply PCI_XILINX
165 imply PCI_INIT_R
166 imply SCSI
167 imply SCSI_AHCI
168 imply SYS_NS16550
169 imply SYSRESET
170 imply SYSRESET_CMD_POWEROFF
171 imply SYSRESET_SYSCON
172 imply USB
173 imply USB_EHCI_HCD
174 imply USB_EHCI_PCI
175 imply USB_XHCI_HCD
176 imply USB_XHCI_PCI
177 imply CMD_USB
Paul Burtonf5de32a2016-09-08 07:47:39 +0100178
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100179config TARGET_XILFPGA
180 bool "Support Imagination Xilfpga"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200181 select HAS_FIXED_TIMER_FREQUENCY
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100182 select DM
Michal Simek84f3dec2018-07-23 15:55:13 +0200183 select DM_GPIO
184 select DM_SERIAL
Tom Rini3ef67ae2021-08-26 11:47:59 -0400185 select SYS_CACHE_SHIFT_4
Michal Simek84f3dec2018-07-23 15:55:13 +0200186 select OF_CONTROL
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100187 select ROM_EXCEPTION_VECTORS
Michal Simek84f3dec2018-07-23 15:55:13 +0200188 select SUPPORTS_CPU_MIPS32_R1
189 select SUPPORTS_CPU_MIPS32_R2
190 select SUPPORTS_LITTLE_ENDIAN
Michal Simek2e7c8192018-07-23 15:55:14 +0200191 imply CMD_DM
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100192 help
193 This supports IMGTEC MIPSfpga platform
194
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900195endchoice
196
Paul Burtonf5de32a2016-09-08 07:47:39 +0100197source "board/imgtec/boston/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900198source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100199source "board/imgtec/xilfpga/Kconfig"
Wills Wang833a1a82016-03-16 16:59:52 +0800200source "arch/mips/mach-ath79/Kconfig"
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +0100201source "arch/mips/mach-mscc/Kconfig"
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +0200202source "arch/mips/mach-bmips/Kconfig"
Paul Burton96c68472018-12-16 19:25:22 -0300203source "arch/mips/mach-jz47xx/Kconfig"
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530204source "arch/mips/mach-pic32/Kconfig"
developer89f051b2019-04-30 11:13:58 +0800205source "arch/mips/mach-mtmips/Kconfig"
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200206source "arch/mips/mach-octeon/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900207
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100208if MIPS
209
210choice
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100211 prompt "CPU selection"
212 default CPU_MIPS32_R2
213
214config CPU_MIPS32_R1
215 bool "MIPS32 Release 1"
216 depends on SUPPORTS_CPU_MIPS32_R1
217 select 32BIT
218 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100219 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100220 MIPS32 architecture.
221
222config CPU_MIPS32_R2
223 bool "MIPS32 Release 2"
224 depends on SUPPORTS_CPU_MIPS32_R2
225 select 32BIT
226 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100227 Choose this option to build an U-Boot for release 2 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100228 MIPS32 architecture.
229
Paul Burton55e29dd2016-05-16 10:52:12 +0100230config CPU_MIPS32_R6
231 bool "MIPS32 Release 6"
232 depends on SUPPORTS_CPU_MIPS32_R6
233 select 32BIT
234 help
235 Choose this option to build an U-Boot for release 6 or later of the
236 MIPS32 architecture.
237
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100238config CPU_MIPS64_R1
239 bool "MIPS64 Release 1"
240 depends on SUPPORTS_CPU_MIPS64_R1
241 select 64BIT
242 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100243 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100244 MIPS64 architecture.
245
246config CPU_MIPS64_R2
247 bool "MIPS64 Release 2"
248 depends on SUPPORTS_CPU_MIPS64_R2
249 select 64BIT
250 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100251 Choose this option to build a kernel for release 2 through 5 of the
252 MIPS64 architecture.
253
254config CPU_MIPS64_R6
255 bool "MIPS64 Release 6"
256 depends on SUPPORTS_CPU_MIPS64_R6
257 select 64BIT
258 help
259 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100260 MIPS64 architecture.
261
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200262config CPU_MIPS64_OCTEON
263 bool "Marvell Octeon series of CPUs"
264 depends on SUPPORTS_CPU_MIPS64_OCTEON
265 select 64BIT
266 help
267 Choose this option for Marvell Octeon CPUs. These CPUs are between
268 MIPS64 R5 and R6 with other extensions.
269
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100270endchoice
271
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100272menu "General setup"
273
274config ROM_EXCEPTION_VECTORS
275 bool "Build U-Boot image with exception vectors"
276 help
277 Enable this to include exception vectors in the U-Boot image. This is
278 required if the U-Boot entry point is equal to the address of the
279 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
280 U-Boot booted from parallel NOR flash).
281 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
282 In that case the image size will be reduced by 0x500 bytes.
283
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200284config SYS_MIPS_TIMER_FREQ
285 int "Fixed MIPS CPU timer frequency in Hz"
286 depends on HAS_FIXED_TIMER_FREQUENCY
287 help
288 Configures a fixed CPU timer frequency.
289
Paul Burton3d6864a2017-05-12 13:26:11 +0200290config MIPS_CM_BASE
291 hex "MIPS CM GCR Base Address"
292 depends on MIPS_CM
Paul Burtona6ac9652017-04-30 21:22:41 +0200293 default 0x16100000 if TARGET_BOSTON
Paul Burton3d6864a2017-05-12 13:26:11 +0200294 default 0x1fbf8000
295 help
296 The physical base address at which to map the MIPS Coherence Manager
297 Global Configuration Registers (GCRs). This should be set such that
298 the GCRs occupy a region of the physical address space which is
299 otherwise unused, or at minimum that software doesn't need to access.
300
Daniel Schwierzecke3b432d2018-09-07 19:02:05 +0200301config MIPS_CACHE_INDEX_BASE
302 hex "Index base address for cache initialisation"
303 default 0x80000000 if CPU_MIPS32
304 default 0xffffffff80000000 if CPU_MIPS64
305 help
306 This is the base address for a memory block, which is used for
307 initialising the cache lines. This is also the base address of a memory
308 block which is used for loading and filling cache lines when
309 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
310 Normally this is CKSEG0. If the MIPS system needs to move this block
311 to some SRAM or ScratchPad RAM, adapt this option accordingly.
312
Stefan Roesec6f54b42020-06-30 12:33:16 +0200313config MIPS_MACH_EARLY_INIT
314 bool "Enable mach specific very early init code"
315 help
316 Use this to enable the call to mips_mach_early_init() very early
317 from start.S. This function can be used e.g. to do some very early
318 CPU / SoC intitialization or image copying. Its called very early
319 and at this stage the PC might not match the linking address
320 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
321
Daniel Schwierzeckc95e7f12020-07-12 00:45:57 +0200322config MIPS_CACHE_SETUP
323 bool "Allow generic start code to initialize and setup caches"
324 default n if SKIP_LOWLEVEL_INIT
325 default y
326 help
327 This allows the generic start code to invoke the generic initialization
328 of the CPU caches. Disabling this can be useful for RAM boot scenarios
329 (EJTAG, SPL payload) or for machines which don't need cache initialization
330 or which want to provide their own cache implementation.
331
332 If unsure, say yes.
333
334config MIPS_CACHE_DISABLE
335 bool "Allow generic start code to initially disable caches"
336 default n if SKIP_LOWLEVEL_INIT
337 default y
338 help
339 This allows the generic start code to initially disable the CPU caches
340 and run uncached until the caches are initialized and enabled. Disabling
341 this can be useful on machines which don't need cache initialization or
342 which want to provide their own cache implementation.
343
344 If unsure, say yes.
345
Daniel Schwierzeck80132862018-11-01 02:02:21 +0100346config MIPS_RELOCATION_TABLE_SIZE
347 hex "Relocation table size"
348 range 0x100 0x10000
349 default "0x8000"
350 ---help---
351 A table of relocation data will be appended to the U-Boot binary
352 and parsed in relocate_code() to fix up all offsets in the relocated
353 U-Boot.
354
355 This option allows the amount of space reserved for the table to be
356 adjusted in a range from 256 up to 64k. The default is 32k and should
357 be ok in most cases. Reduce this value to shrink the size of U-Boot
358 binary.
359
360 The build will fail and a valid size suggested if this is too small.
361
362 If unsure, leave at the default value.
363
developer5cbbd712020-04-21 09:28:25 +0200364config RESTORE_EXCEPTION_VECTOR_BASE
365 bool "Restore exception vector base before booting linux kernel"
developer5cbbd712020-04-21 09:28:25 +0200366 help
367 In U-Boot the exception vector base will be moved to top of memory,
368 to be used to display register dump when exception occurs.
369 But some old linux kernel does not honor the base set in CP0_EBASE.
370 A modified exception vector base will cause kernel crash.
371
372 This option will restore the exception vector base to its previous
373 value.
374
375 If unsure, say N.
376
377config OVERRIDE_EXCEPTION_VECTOR_BASE
378 bool "Override the exception vector base to be restored"
379 depends on RESTORE_EXCEPTION_VECTOR_BASE
developer5cbbd712020-04-21 09:28:25 +0200380 help
381 Enable this option if you want to use a different exception vector
382 base rather than the previously saved one.
383
384config NEW_EXCEPTION_VECTOR_BASE
385 hex "New exception vector base"
386 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
387 range 0x80000000 0xbffff000
388 default 0x80000000
389 help
390 The exception vector base to be restored before booting linux kernel
391
developer01a28282020-04-21 09:28:33 +0200392config INIT_STACK_WITHOUT_MALLOC_F
393 bool "Do not reserve malloc space on initial stack"
developer01a28282020-04-21 09:28:33 +0200394 help
395 Enable this option if you don't want to reserve malloc space on
396 initial stack. This is useful if the initial stack can't hold large
397 malloc space. Platform should set the malloc_base later when DRAM is
398 ready to use.
399
400config SPL_INIT_STACK_WITHOUT_MALLOC_F
401 bool "Do not reserve malloc space on initial stack in SPL"
developer01a28282020-04-21 09:28:33 +0200402 help
403 Enable this option if you don't want to reserve malloc space on
404 initial stack. This is useful if the initial stack can't hold large
405 malloc space. Platform should set the malloc_base later when DRAM is
406 ready to use.
407
developer25678a02020-04-21 09:28:37 +0200408config SPL_LOADER_SUPPORT
409 bool
developer25678a02020-04-21 09:28:37 +0200410 help
411 Enable this option if you want to use SPL loaders without DM enabled.
412
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100413endmenu
414
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100415menu "OS boot interface"
416
417config MIPS_BOOT_CMDLINE_LEGACY
418 bool "Hand over legacy command line to Linux kernel"
419 default y
420 help
421 Enable this option if you want U-Boot to hand over the Yamon-style
422 command line to the kernel. All bootargs will be prepared as argc/argv
423 compatible list. The argument count (argc) is stored in register $a0.
424 The address of the argument list (argv) is stored in register $a1.
425
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100426config MIPS_BOOT_ENV_LEGACY
427 bool "Hand over legacy environment to Linux kernel"
428 default y
429 help
430 Enable this option if you want U-Boot to hand over the Yamon-style
431 environment to the kernel. Information like memory size, initrd
432 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day8c60f922016-05-04 04:47:31 -0400433 The address of the environment is stored in register $a2.
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100434
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100435config MIPS_BOOT_FDT
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100436 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100437 help
438 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100439 device tree to the kernel. According to UHI register $a0 will be set
440 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100441
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100442endmenu
443
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100444config SUPPORTS_BIG_ENDIAN
445 bool
446
447config SUPPORTS_LITTLE_ENDIAN
448 bool
449
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100450config SUPPORTS_CPU_MIPS32_R1
451 bool
452
453config SUPPORTS_CPU_MIPS32_R2
454 bool
455
Paul Burton55e29dd2016-05-16 10:52:12 +0100456config SUPPORTS_CPU_MIPS32_R6
457 bool
458
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100459config SUPPORTS_CPU_MIPS64_R1
460 bool
461
462config SUPPORTS_CPU_MIPS64_R2
463 bool
464
Paul Burton55e29dd2016-05-16 10:52:12 +0100465config SUPPORTS_CPU_MIPS64_R6
466 bool
467
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200468config SUPPORTS_CPU_MIPS64_OCTEON
469 bool
470
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200471config HAS_FIXED_TIMER_FREQUENCY
472 bool
473
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200474config CPU_CAVIUM_OCTEON
475 bool
476
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100477config CPU_MIPS32
478 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100479 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100480
481config CPU_MIPS64
482 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100483 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200484 default y if CPU_MIPS64_OCTEON
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100485
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100486config MIPS_TUNE_4KC
487 bool
488
489config MIPS_TUNE_14KC
490 bool
491
492config MIPS_TUNE_24KC
493 bool
494
Daniel Schwierzeckc7661d52016-05-27 15:39:39 +0200495config MIPS_TUNE_34KC
496 bool
497
Marek Vasuta9c6e8b2016-05-06 20:10:33 +0200498config MIPS_TUNE_74KC
499 bool
500
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200501config MIPS_TUNE_OCTEON3
502 bool
503
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100504config SWAP_IO_SPACE
505 bool
506
Paul Burton6832bdc2015-01-29 01:28:02 +0000507config SYS_MIPS_CACHE_INIT_RAM_LOAD
508 bool
509
Daniel Schwierzeck41dc35e2016-06-04 16:13:21 +0200510config MIPS_INIT_STACK_IN_SRAM
511 bool
Daniel Schwierzeck41dc35e2016-06-04 16:13:21 +0200512 help
513 Select this if the initial stack frame could be setup in SRAM.
514 Normally the initial stack frame is set up in DRAM which is often
515 only available after lowlevel_init. With this option the initial
516 stack frame and the early C environment is set up before
517 lowlevel_init. Thus lowlevel_init does not need to be implemented
518 in assembler.
519
developereb7d3a22020-04-21 09:28:27 +0200520config MIPS_SRAM_INIT
521 bool
developereb7d3a22020-04-21 09:28:27 +0200522 depends on MIPS_INIT_STACK_IN_SRAM
523 help
524 Select this if the SRAM for initial stack needs to be initialized
525 before it can be used. If enabled, a function mips_sram_init() will
526 be called just before setup_stack_gd.
527
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200528config DMA_ADDR_T_64BIT
529 bool
530 help
531 Select this to enable 64-bit DMA addressing
532
Paul Burton5e511422016-05-27 14:28:04 +0100533config SYS_DCACHE_SIZE
534 int
535 default 0
536 help
537 The total size of the L1 Dcache, if known at compile time.
538
Paul Burton62f13522016-05-27 14:28:05 +0100539config SYS_DCACHE_LINE_SIZE
Paul Burton79e49fd2016-06-09 13:09:52 +0100540 int
Paul Burton62f13522016-05-27 14:28:05 +0100541 default 0
542 help
543 The size of L1 Dcache lines, if known at compile time.
544
Paul Burton5e511422016-05-27 14:28:04 +0100545config SYS_ICACHE_SIZE
546 int
547 default 0
548 help
549 The total size of the L1 ICache, if known at compile time.
550
Paul Burton62f13522016-05-27 14:28:05 +0100551config SYS_ICACHE_LINE_SIZE
Paul Burton5e511422016-05-27 14:28:04 +0100552 int
553 default 0
554 help
Paul Burton62f13522016-05-27 14:28:05 +0100555 The size of L1 Icache lines, if known at compile time.
Paul Burton5e511422016-05-27 14:28:04 +0100556
Ramon Fried7e07e492019-06-10 21:05:26 +0300557config SYS_SCACHE_LINE_SIZE
558 int
559 default 0
560 help
561 The size of L2 cache lines, if known at compile time.
562
563
Paul Burton5e511422016-05-27 14:28:04 +0100564config SYS_CACHE_SIZE_AUTO
565 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Ramon Fried7e07e492019-06-10 21:05:26 +0300566 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
567 SYS_SCACHE_LINE_SIZE = 0
Paul Burton5e511422016-05-27 14:28:04 +0100568 help
569 Select this (or let it be auto-selected by not defining any cache
570 sizes) in order to allow U-Boot to automatically detect the sizes
571 of caches at runtime. This has a small cost in code size & runtime
572 so if you know the cache configuration for your system at compile
573 time it would be beneficial to configure it.
574
Paul Burton81560782016-09-21 11:18:54 +0100575config MIPS_L2_CACHE
576 bool
577 help
578 Select this if your system includes an L2 cache and you want U-Boot
579 to initialise & maintain it.
580
Paul Burton8d6600b2016-01-29 13:54:52 +0000581config DYNAMIC_IO_PORT_BASE
582 bool
583
Paul Burton79ac1742016-09-21 11:18:53 +0100584config MIPS_CM
585 bool
586 help
587 Select this if your system contains a MIPS Coherence Manager and you
588 wish U-Boot to configure it or make use of it to retrieve system
589 information such as cache configuration.
590
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +0200591config MIPS_INSERT_BOOT_CONFIG
592 bool
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +0200593 help
594 Enable this to insert some board-specific boot configuration in
595 the U-Boot binary at offset 0x10.
596
597config MIPS_BOOT_CONFIG_WORD0
598 hex
599 depends on MIPS_INSERT_BOOT_CONFIG
600 default 0x420 if TARGET_MALTA
601 default 0x0
602 help
603 Value which is inserted as boot config word 0.
604
605config MIPS_BOOT_CONFIG_WORD1
606 hex
607 depends on MIPS_INSERT_BOOT_CONFIG
608 default 0x0
609 help
610 Value which is inserted as boot config word 1.
611
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100612endif
613
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900614endmenu