| commit | e3b432d001730cb064a837083933ee4df4a48df3 | [log] [tgz] |
|---|---|---|
| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Fri Sep 07 19:02:05 2018 +0200 |
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | Sat Sep 22 21:02:03 2018 +0200 |
| tree | 779823c3cff6633929662fa5ada75b773cffa7d9 | |
| parent | 5cfb438866d3e42bc838cc0b439ab017d08c1557 [diff] |
MIPS: cache: make index base address configurable The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>