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git01.mediatek.com / filogic / uboot / 79e49fd0e85599a9c01cb74a93087aa2c6d0f757 / . / arch / mips / Kconfig
blob: 21066f0fda69c1649cf981b52e2ae53c13a982d1 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]5 default "mips"
6
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +0100[diff] [blame]7config SYS_CPU
Paul Burton32464372016-05-16 10:52:11 +0100[diff] [blame]8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +0100[diff] [blame]10
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]11choice
12 prompt "Target select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]13 optional
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]14
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeck94384d12014-10-26 14:14:07 +0100[diff] [blame]21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]23
24config TARGET_MALTA
25 bool "Support malta"
Paul Burtona31a3df2016-05-17 07:43:28 +0100[diff] [blame]26 select DM
27 select DM_SERIAL
Paul Burton8d6600b2016-01-29 13:54:52 +0000[diff] [blame]28 select DYNAMIC_IO_PORT_BASE
Paul Burtona31a3df2016-05-17 07:43:28 +0100[diff] [blame]29 select OF_CONTROL
30 select OF_ISA_BUS
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]31 select SUPPORTS_BIG_ENDIAN
32 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]33 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
Paul Burton1c10e0d2016-05-16 10:52:14 +0100[diff] [blame]35 select SUPPORTS_CPU_MIPS32_R6
Paul Burton825cfbd2016-05-26 14:49:36 +0100[diff] [blame]36 select SUPPORTS_CPU_MIPS64_R1
37 select SUPPORTS_CPU_MIPS64_R2
38 select SUPPORTS_CPU_MIPS64_R6
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100[diff] [blame]39 select SWAP_IO_SPACE
Daniel Schwierzeck02ca55e2016-01-09 17:32:50 +0100[diff] [blame]40 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]41
42config TARGET_VCT
43 bool "Support vct"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]44 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]45 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]47 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]48
49config TARGET_DBAU1X00
50 bool "Support dbau1x00"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]51 select SUPPORTS_BIG_ENDIAN
52 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]53 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]55 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100[diff] [blame]56 select MIPS_TUNE_4KC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]57
58config TARGET_PB1X00
59 bool "Support pb1x00"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]60 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]61 select SUPPORTS_CPU_MIPS32_R1
62 select SUPPORTS_CPU_MIPS32_R2
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]63 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100[diff] [blame]64 select MIPS_TUNE_4KC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]65
Wills Wang833a1a82016-03-16 16:59:52 +0800[diff] [blame]66config ARCH_ATH79
67 bool "Support QCA/Atheros ath79"
68 select OF_CONTROL
69 select DM
70
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530[diff] [blame]71config MACH_PIC32
72 bool "Support Microchip PIC32"
73 select OF_CONTROL
74 select DM
75
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]76endchoice
77
78source "board/dbau1x00/Kconfig"
79source "board/imgtec/malta/Kconfig"
80source "board/micronas/vct/Kconfig"
81source "board/pb1x00/Kconfig"
82source "board/qemu-mips/Kconfig"
Wills Wang833a1a82016-03-16 16:59:52 +0800[diff] [blame]83source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530[diff] [blame]84source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]85
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]86if MIPS
87
88choice
89 prompt "Endianness selection"
90 help
91 Some MIPS boards can be configured for either little or big endian
92 byte order. These modes require different U-Boot images. In general there
93 is one preferred byteorder for a particular system but some systems are
94 just as commonly used in the one or the other endianness.
95
96config SYS_BIG_ENDIAN
97 bool "Big endian"
98 depends on SUPPORTS_BIG_ENDIAN
99
100config SYS_LITTLE_ENDIAN
101 bool "Little endian"
102 depends on SUPPORTS_LITTLE_ENDIAN
103
104endchoice
105
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]106choice
107 prompt "CPU selection"
108 default CPU_MIPS32_R2
109
110config CPU_MIPS32_R1
111 bool "MIPS32 Release 1"
112 depends on SUPPORTS_CPU_MIPS32_R1
113 select 32BIT
114 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]115 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]116 MIPS32 architecture.
117
118config CPU_MIPS32_R2
119 bool "MIPS32 Release 2"
120 depends on SUPPORTS_CPU_MIPS32_R2
121 select 32BIT
122 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]123 Choose this option to build an U-Boot for release 2 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]124 MIPS32 architecture.
125
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]126config CPU_MIPS32_R6
127 bool "MIPS32 Release 6"
128 depends on SUPPORTS_CPU_MIPS32_R6
129 select 32BIT
130 help
131 Choose this option to build an U-Boot for release 6 or later of the
132 MIPS32 architecture.
133
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]134config CPU_MIPS64_R1
135 bool "MIPS64 Release 1"
136 depends on SUPPORTS_CPU_MIPS64_R1
137 select 64BIT
138 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]139 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]140 MIPS64 architecture.
141
142config CPU_MIPS64_R2
143 bool "MIPS64 Release 2"
144 depends on SUPPORTS_CPU_MIPS64_R2
145 select 64BIT
146 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]147 Choose this option to build a kernel for release 2 through 5 of the
148 MIPS64 architecture.
149
150config CPU_MIPS64_R6
151 bool "MIPS64 Release 6"
152 depends on SUPPORTS_CPU_MIPS64_R6
153 select 64BIT
154 help
155 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]156 MIPS64 architecture.
157
158endchoice
159
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100[diff] [blame]160menu "OS boot interface"
161
162config MIPS_BOOT_CMDLINE_LEGACY
163 bool "Hand over legacy command line to Linux kernel"
164 default y
165 help
166 Enable this option if you want U-Boot to hand over the Yamon-style
167 command line to the kernel. All bootargs will be prepared as argc/argv
168 compatible list. The argument count (argc) is stored in register $a0.
169 The address of the argument list (argv) is stored in register $a1.
170
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100[diff] [blame]171config MIPS_BOOT_ENV_LEGACY
172 bool "Hand over legacy environment to Linux kernel"
173 default y
174 help
175 Enable this option if you want U-Boot to hand over the Yamon-style
176 environment to the kernel. Information like memory size, initrd
177 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day8c60f922016-05-04 04:47:31 -0400[diff] [blame]178 The address of the environment is stored in register $a2.
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100[diff] [blame]179
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100[diff] [blame]180config MIPS_BOOT_FDT
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100[diff] [blame]181 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100[diff] [blame]182 default n
183 help
184 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100[diff] [blame]185 device tree to the kernel. According to UHI register $a0 will be set
186 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100[diff] [blame]187
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100[diff] [blame]188endmenu
189
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]190config SUPPORTS_BIG_ENDIAN
191 bool
192
193config SUPPORTS_LITTLE_ENDIAN
194 bool
195
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]196config SUPPORTS_CPU_MIPS32_R1
197 bool
198
199config SUPPORTS_CPU_MIPS32_R2
200 bool
201
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]202config SUPPORTS_CPU_MIPS32_R6
203 bool
204
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]205config SUPPORTS_CPU_MIPS64_R1
206 bool
207
208config SUPPORTS_CPU_MIPS64_R2
209 bool
210
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]211config SUPPORTS_CPU_MIPS64_R6
212 bool
213
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100[diff] [blame]214config CPU_MIPS32
215 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]216 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100[diff] [blame]217
218config CPU_MIPS64
219 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame]220 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100[diff] [blame]221
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100[diff] [blame]222config MIPS_TUNE_4KC
223 bool
224
225config MIPS_TUNE_14KC
226 bool
227
228config MIPS_TUNE_24KC
229 bool
230
Daniel Schwierzeckc7661d52016-05-27 15:39:39 +0200[diff] [blame]231config MIPS_TUNE_34KC
232 bool
233
Marek Vasuta9c6e8b2016-05-06 20:10:33 +0200[diff] [blame]234config MIPS_TUNE_74KC
235 bool
236
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]237config 32BIT
238 bool
239
240config 64BIT
241 bool
242
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100[diff] [blame]243config SWAP_IO_SPACE
244 bool
245
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]246config SYS_MIPS_CACHE_INIT_RAM_LOAD
247 bool
248
Paul Burton5e511422016-05-27 14:28:04 +0100[diff] [blame]249config SYS_DCACHE_SIZE
250 int
251 default 0
252 help
253 The total size of the L1 Dcache, if known at compile time.
254
Paul Burton62f13522016-05-27 14:28:05 +0100[diff] [blame]255config SYS_DCACHE_LINE_SIZE
Paul Burton79e49fd2016-06-09 13:09:52 +0100[diff] [blame^]256 int
Paul Burton62f13522016-05-27 14:28:05 +0100[diff] [blame]257 default 0
258 help
259 The size of L1 Dcache lines, if known at compile time.
260
Paul Burton5e511422016-05-27 14:28:04 +0100[diff] [blame]261config SYS_ICACHE_SIZE
262 int
263 default 0
264 help
265 The total size of the L1 ICache, if known at compile time.
266
Paul Burton62f13522016-05-27 14:28:05 +0100[diff] [blame]267config SYS_ICACHE_LINE_SIZE
Paul Burton5e511422016-05-27 14:28:04 +0100[diff] [blame]268 int
269 default 0
270 help
Paul Burton62f13522016-05-27 14:28:05 +0100[diff] [blame]271 The size of L1 Icache lines, if known at compile time.
Paul Burton5e511422016-05-27 14:28:04 +0100[diff] [blame]272
273config SYS_CACHE_SIZE_AUTO
274 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Paul Burton62f13522016-05-27 14:28:05 +0100[diff] [blame]275 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
Paul Burton5e511422016-05-27 14:28:04 +0100[diff] [blame]276 help
277 Select this (or let it be auto-selected by not defining any cache
278 sizes) in order to allow U-Boot to automatically detect the sizes
279 of caches at runtime. This has a small cost in code size & runtime
280 so if you know the cache configuration for your system at compile
281 time it would be beneficial to configure it.
282
Daniel Schwierzeck02ca55e2016-01-09 17:32:50 +0100[diff] [blame]283config MIPS_L1_CACHE_SHIFT_4
284 bool
285
286config MIPS_L1_CACHE_SHIFT_5
287 bool
288
289config MIPS_L1_CACHE_SHIFT_6
290 bool
291
292config MIPS_L1_CACHE_SHIFT_7
293 bool
294
295config MIPS_L1_CACHE_SHIFT
296 int
297 default "7" if MIPS_L1_CACHE_SHIFT_7
298 default "6" if MIPS_L1_CACHE_SHIFT_6
299 default "5" if MIPS_L1_CACHE_SHIFT_5
300 default "4" if MIPS_L1_CACHE_SHIFT_4
301 default "5"
302
Paul Burton8d6600b2016-01-29 13:54:52 +0000[diff] [blame]303config DYNAMIC_IO_PORT_BASE
304 bool
305
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]306endif
307
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]308endmenu