MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a79224e..5c30ae9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -252,21 +252,27 @@
help
The total size of the L1 Dcache, if known at compile time.
+config SYS_DCACHE_LINE_SIZE
+ hex
+ default 0
+ help
+ The size of L1 Dcache lines, if known at compile time.
+
config SYS_ICACHE_SIZE
int
default 0
help
The total size of the L1 ICache, if known at compile time.
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
int
default 0
help
- The size of L1 cache lines, if known at compile time.
+ The size of L1 Icache lines, if known at compile time.
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
- SYS_CACHELINE_SIZE = 0
+ SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes