MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a79224e..5c30ae9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -252,21 +252,27 @@
help
The total size of the L1 Dcache, if known at compile time.
+config SYS_DCACHE_LINE_SIZE
+ hex
+ default 0
+ help
+ The size of L1 Dcache lines, if known at compile time.
+
config SYS_ICACHE_SIZE
int
default 0
help
The total size of the L1 ICache, if known at compile time.
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
int
default 0
help
- The size of L1 cache lines, if known at compile time.
+ The size of L1 Icache lines, if known at compile time.
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
- SYS_CACHELINE_SIZE = 0
+ SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 806bd26..0cea581 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -12,4 +12,11 @@
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
+/*
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index fbaafee..19a42ff 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,23 +9,13 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
-#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
-
static inline unsigned long icache_line_size(void)
{
- return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
- return CONFIG_SYS_CACHELINE_SIZE;
-}
+ unsigned long conf1, il;
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+ if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+ return CONFIG_SYS_ICACHE_LINE_SIZE;
-static inline unsigned long icache_line_size(void)
-{
- unsigned long conf1, il;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
@@ -36,6 +26,10 @@
static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
+
+ if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+ return CONFIG_SYS_DCACHE_LINE_SIZE;
+
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
@@ -43,8 +37,6 @@
return 2 << dl;
}
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
-
void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 4bb9a17..bc8ab27 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -101,14 +101,14 @@
LEAF(mips_cache_reset)
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
- li t8, CONFIG_SYS_CACHELINE_SIZE
+ li t8, CONFIG_SYS_ICACHE_LINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
- li t9, CONFIG_SYS_CACHELINE_SIZE
+ li t9, CONFIG_SYS_DCACHE_LINE_SIZE
#else
l1_info t3, t9, MIPS_CONF1_DA_SHF
#endif