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git01.mediatek.com / filogic / uboot / 55e29dd3b1a7a2c02f523aa0a7532495b5c424fa / . / arch / mips / Kconfig
blob: 994168c27066870e78d877fef1d681043183417c [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]5 default "mips"
6
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +0100[diff] [blame]7config SYS_CPU
Paul Burton32464372016-05-16 10:52:11 +0100[diff] [blame]8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +0100[diff] [blame]10
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]11choice
12 prompt "Target select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]13 optional
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]14
15config TARGET_QEMU_MIPS
16 bool "Support qemu-mips"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]17 select SUPPORTS_BIG_ENDIAN
18 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]19 select SUPPORTS_CPU_MIPS32_R1
20 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeck94384d12014-10-26 14:14:07 +0100[diff] [blame]21 select SUPPORTS_CPU_MIPS64_R1
22 select SUPPORTS_CPU_MIPS64_R2
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]23
24config TARGET_MALTA
25 bool "Support malta"
Paul Burton8d6600b2016-01-29 13:54:52 +0000[diff] [blame]26 select DYNAMIC_IO_PORT_BASE
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]27 select SUPPORTS_BIG_ENDIAN
28 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]29 select SUPPORTS_CPU_MIPS32_R1
30 select SUPPORTS_CPU_MIPS32_R2
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100[diff] [blame]31 select SWAP_IO_SPACE
Daniel Schwierzeck02ca55e2016-01-09 17:32:50 +0100[diff] [blame]32 select MIPS_L1_CACHE_SHIFT_6
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]33
34config TARGET_VCT
35 bool "Support vct"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]36 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]37 select SUPPORTS_CPU_MIPS32_R1
38 select SUPPORTS_CPU_MIPS32_R2
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]39 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]40
41config TARGET_DBAU1X00
42 bool "Support dbau1x00"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]43 select SUPPORTS_BIG_ENDIAN
44 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]45 select SUPPORTS_CPU_MIPS32_R1
46 select SUPPORTS_CPU_MIPS32_R2
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]47 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100[diff] [blame]48 select MIPS_TUNE_4KC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]49
50config TARGET_PB1X00
51 bool "Support pb1x00"
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]52 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]53 select SUPPORTS_CPU_MIPS32_R1
54 select SUPPORTS_CPU_MIPS32_R2
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]55 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100[diff] [blame]56 select MIPS_TUNE_4KC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]57
Wills Wang833a1a82016-03-16 16:59:52 +0800[diff] [blame]58config ARCH_ATH79
59 bool "Support QCA/Atheros ath79"
60 select OF_CONTROL
61 select DM
62
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530[diff] [blame]63config MACH_PIC32
64 bool "Support Microchip PIC32"
65 select OF_CONTROL
66 select DM
67
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]68endchoice
69
70source "board/dbau1x00/Kconfig"
71source "board/imgtec/malta/Kconfig"
72source "board/micronas/vct/Kconfig"
73source "board/pb1x00/Kconfig"
74source "board/qemu-mips/Kconfig"
Wills Wang833a1a82016-03-16 16:59:52 +0800[diff] [blame]75source "arch/mips/mach-ath79/Kconfig"
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530[diff] [blame]76source "arch/mips/mach-pic32/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]77
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]78if MIPS
79
80choice
81 prompt "Endianness selection"
82 help
83 Some MIPS boards can be configured for either little or big endian
84 byte order. These modes require different U-Boot images. In general there
85 is one preferred byteorder for a particular system but some systems are
86 just as commonly used in the one or the other endianness.
87
88config SYS_BIG_ENDIAN
89 bool "Big endian"
90 depends on SUPPORTS_BIG_ENDIAN
91
92config SYS_LITTLE_ENDIAN
93 bool "Little endian"
94 depends on SUPPORTS_LITTLE_ENDIAN
95
96endchoice
97
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]98choice
99 prompt "CPU selection"
100 default CPU_MIPS32_R2
101
102config CPU_MIPS32_R1
103 bool "MIPS32 Release 1"
104 depends on SUPPORTS_CPU_MIPS32_R1
105 select 32BIT
106 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]107 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]108 MIPS32 architecture.
109
110config CPU_MIPS32_R2
111 bool "MIPS32 Release 2"
112 depends on SUPPORTS_CPU_MIPS32_R2
113 select 32BIT
114 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]115 Choose this option to build an U-Boot for release 2 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]116 MIPS32 architecture.
117
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]118config CPU_MIPS32_R6
119 bool "MIPS32 Release 6"
120 depends on SUPPORTS_CPU_MIPS32_R6
121 select 32BIT
122 help
123 Choose this option to build an U-Boot for release 6 or later of the
124 MIPS32 architecture.
125
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]126config CPU_MIPS64_R1
127 bool "MIPS64 Release 1"
128 depends on SUPPORTS_CPU_MIPS64_R1
129 select 64BIT
130 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]131 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]132 MIPS64 architecture.
133
134config CPU_MIPS64_R2
135 bool "MIPS64 Release 2"
136 depends on SUPPORTS_CPU_MIPS64_R2
137 select 64BIT
138 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]139 Choose this option to build a kernel for release 2 through 5 of the
140 MIPS64 architecture.
141
142config CPU_MIPS64_R6
143 bool "MIPS64 Release 6"
144 depends on SUPPORTS_CPU_MIPS64_R6
145 select 64BIT
146 help
147 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]148 MIPS64 architecture.
149
150endchoice
151
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100[diff] [blame]152menu "OS boot interface"
153
154config MIPS_BOOT_CMDLINE_LEGACY
155 bool "Hand over legacy command line to Linux kernel"
156 default y
157 help
158 Enable this option if you want U-Boot to hand over the Yamon-style
159 command line to the kernel. All bootargs will be prepared as argc/argv
160 compatible list. The argument count (argc) is stored in register $a0.
161 The address of the argument list (argv) is stored in register $a1.
162
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100[diff] [blame]163config MIPS_BOOT_ENV_LEGACY
164 bool "Hand over legacy environment to Linux kernel"
165 default y
166 help
167 Enable this option if you want U-Boot to hand over the Yamon-style
168 environment to the kernel. Information like memory size, initrd
169 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day8c60f922016-05-04 04:47:31 -0400[diff] [blame]170 The address of the environment is stored in register $a2.
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100[diff] [blame]171
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100[diff] [blame]172config MIPS_BOOT_FDT
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100[diff] [blame]173 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100[diff] [blame]174 default n
175 help
176 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100[diff] [blame]177 device tree to the kernel. According to UHI register $a0 will be set
178 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100[diff] [blame]179
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100[diff] [blame]180endmenu
181
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]182config SUPPORTS_BIG_ENDIAN
183 bool
184
185config SUPPORTS_LITTLE_ENDIAN
186 bool
187
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]188config SUPPORTS_CPU_MIPS32_R1
189 bool
190
191config SUPPORTS_CPU_MIPS32_R2
192 bool
193
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]194config SUPPORTS_CPU_MIPS32_R6
195 bool
196
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]197config SUPPORTS_CPU_MIPS64_R1
198 bool
199
200config SUPPORTS_CPU_MIPS64_R2
201 bool
202
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]203config SUPPORTS_CPU_MIPS64_R6
204 bool
205
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100[diff] [blame]206config CPU_MIPS32
207 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]208 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100[diff] [blame]209
210config CPU_MIPS64
211 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100[diff] [blame^]212 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100[diff] [blame]213
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100[diff] [blame]214config MIPS_TUNE_4KC
215 bool
216
217config MIPS_TUNE_14KC
218 bool
219
220config MIPS_TUNE_24KC
221 bool
222
Marek Vasuta9c6e8b2016-05-06 20:10:33 +0200[diff] [blame]223config MIPS_TUNE_74KC
224 bool
225
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100[diff] [blame]226config 32BIT
227 bool
228
229config 64BIT
230 bool
231
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100[diff] [blame]232config SWAP_IO_SPACE
233 bool
234
Paul Burton6832bdc2015-01-29 01:28:02 +0000[diff] [blame]235config SYS_MIPS_CACHE_INIT_RAM_LOAD
236 bool
237
Daniel Schwierzeck02ca55e2016-01-09 17:32:50 +0100[diff] [blame]238config MIPS_L1_CACHE_SHIFT_4
239 bool
240
241config MIPS_L1_CACHE_SHIFT_5
242 bool
243
244config MIPS_L1_CACHE_SHIFT_6
245 bool
246
247config MIPS_L1_CACHE_SHIFT_7
248 bool
249
250config MIPS_L1_CACHE_SHIFT
251 int
252 default "7" if MIPS_L1_CACHE_SHIFT_7
253 default "6" if MIPS_L1_CACHE_SHIFT_6
254 default "5" if MIPS_L1_CACHE_SHIFT_5
255 default "4" if MIPS_L1_CACHE_SHIFT_4
256 default "5"
257
Paul Burton8d6600b2016-01-29 13:54:52 +0000[diff] [blame]258config DYNAMIC_IO_PORT_BASE
259 bool
260
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100[diff] [blame]261endif
262
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]263endmenu