blob: 748b5175b2ebbc4e092c52aa2c9d886e75db8135 [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadad3ae6782014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton32464372016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeck99e7af22014-10-26 14:14:07 +010010
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergerf0699602015-05-12 14:46:23 -050013 optional
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090014
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090015config TARGET_MALTA
16 bool "Support malta"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020017 select HAS_FIXED_TIMER_FREQUENCY
Daniel Schwierzeck45f78be2021-07-15 20:54:01 +020018 select BOARD_EARLY_INIT_R
Paul Burtona31a3df2016-05-17 07:43:28 +010019 select DM
20 select DM_SERIAL
Simon Glass3933d292021-08-01 18:54:44 -060021 select PCI
Paul Burton8d6600b2016-01-29 13:54:52 +000022 select DYNAMIC_IO_PORT_BASE
Paul Burton59a4c8b2016-09-21 11:18:56 +010023 select MIPS_CM
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +020024 select MIPS_INSERT_BOOT_CONFIG
Tom Rini3ef67ae2021-08-26 11:47:59 -040025 select SYS_CACHE_SHIFT_6
Paul Burton59a4c8b2016-09-21 11:18:56 +010026 select MIPS_L2_CACHE
Paul Burtona31a3df2016-05-17 07:43:28 +010027 select OF_CONTROL
28 select OF_ISA_BUS
Daniel Schwierzeck45f78be2021-07-15 20:54:01 +020029 select PCI_MAP_SYSTEM_MEMORY
Michal Simek84f3dec2018-07-23 15:55:13 +020030 select ROM_EXCEPTION_VECTORS
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +010031 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck256034d2014-10-26 14:14:07 +010032 select SUPPORTS_CPU_MIPS32_R1
33 select SUPPORTS_CPU_MIPS32_R2
Paul Burton1c10e0d2016-05-16 10:52:14 +010034 select SUPPORTS_CPU_MIPS32_R6
Paul Burton825cfbd2016-05-26 14:49:36 +010035 select SUPPORTS_CPU_MIPS64_R1
36 select SUPPORTS_CPU_MIPS64_R2
37 select SUPPORTS_CPU_MIPS64_R6
Michal Simek84f3dec2018-07-23 15:55:13 +020038 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +010039 select SWAP_IO_SPACE
Michal Simek2e7c8192018-07-23 15:55:14 +020040 imply CMD_DM
Masahiro Yamadad3ae6782014-07-30 14:08:14 +090041
Wills Wang833a1a82016-03-16 16:59:52 +080042config ARCH_ATH79
43 bool "Support QCA/Atheros ath79"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020044 select HAS_FIXED_TIMER_FREQUENCY
Wills Wang833a1a82016-03-16 16:59:52 +080045 select DM
Michal Simek84f3dec2018-07-23 15:55:13 +020046 select OF_CONTROL
Michal Simek2e7c8192018-07-23 15:55:14 +020047 imply CMD_DM
Wills Wang833a1a82016-03-16 16:59:52 +080048
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010049config ARCH_MSCC
50 bool "Support MSCC VCore-III"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020051 select HAS_FIXED_TIMER_FREQUENCY
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010052 select OF_CONTROL
53 select DM
54
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020055config ARCH_BMIPS
56 bool "Support BMIPS SoCs"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020057 select HAS_FIXED_TIMER_FREQUENCY
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020058 select CLK
59 select CPU
Michal Simek84f3dec2018-07-23 15:55:13 +020060 select DM
61 select OF_CONTROL
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020062 select RAM
63 select SYSRESET
Michal Simek2e7c8192018-07-23 15:55:14 +020064 imply CMD_DM
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +020065
developer89f051b2019-04-30 11:13:58 +080066config ARCH_MTMIPS
67 bool "Support MediaTek MIPS platforms"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020068 select HAS_FIXED_TIMER_FREQUENCY
developer591826e2019-09-25 17:45:43 +080069 select CLK
Stefan Roese65da15e2018-09-05 15:12:35 +020070 imply CMD_DM
71 select DISPLAY_CPUINFO
72 select DM
Stefan Roese8bbb6bf2018-10-09 08:59:09 +020073 imply DM_GPIO
developer591826e2019-09-25 17:45:43 +080074 select DM_RESET
Stefan Roese65da15e2018-09-05 15:12:35 +020075 select DM_SERIAL
developer591826e2019-09-25 17:45:43 +080076 select PINCTRL
77 select PINMUX
78 select PINCONF
79 select RESET_MTMIPS
Tom Riniddb1ec12024-01-10 13:46:10 -050080 imply MTD
Stefan Roese65da15e2018-09-05 15:12:35 +020081 imply DM_SPI
82 imply DM_SPI_FLASH
Stefan Roese17679e42019-05-28 08:11:37 +020083 select LAST_STAGE_INIT
Stefan Roese65da15e2018-09-05 15:12:35 +020084 select MIPS_TUNE_24KC
85 select OF_CONTROL
86 select ROM_EXCEPTION_VECTORS
87 select SUPPORTS_CPU_MIPS32_R1
88 select SUPPORTS_CPU_MIPS32_R2
89 select SUPPORTS_LITTLE_ENDIAN
developer19d572e2020-04-21 09:28:47 +020090 select SUPPORT_SPL
Stefan Roese65da15e2018-09-05 15:12:35 +020091
Paul Burton96c68472018-12-16 19:25:22 -030092config ARCH_JZ47XX
93 bool "Support Ingenic JZ47xx"
94 select SUPPORT_SPL
Daniel Schwierzeckff21b842022-07-10 17:15:14 +020095 select HAS_FIXED_TIMER_FREQUENCY
Paul Burton96c68472018-12-16 19:25:22 -030096 select OF_CONTROL
97 select DM
98
Aaron Williamsb2ea8182020-06-30 12:08:56 +020099config ARCH_OCTEON
100 bool "Support Marvell Octeon CN7xxx platforms"
Stefan Roese59735ef2022-04-07 09:11:46 +0200101 select ARCH_EARLY_INIT_R
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200102 select CPU_CAVIUM_OCTEON
103 select DISPLAY_CPUINFO
104 select DMA_ADDR_T_64BIT
105 select DM
Stefan Roese67b9edb2020-07-30 13:56:21 +0200106 select DM_GPIO
107 select DM_I2C
108 select DM_SERIAL
109 select DM_SPI
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200110 select MIPS_L2_CACHE
Stefan Roese15ba8022020-06-30 12:33:17 +0200111 select MIPS_MACH_EARLY_INIT
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200112 select MIPS_TUNE_OCTEON3
Tom Riniddb1ec12024-01-10 13:46:10 -0500113 select MTD
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200114 select ROM_EXCEPTION_VECTORS
115 select SUPPORTS_BIG_ENDIAN
116 select SUPPORTS_CPU_MIPS64_OCTEON
117 select PHYS_64BIT
118 select OF_CONTROL
119 select OF_LIVE
120 imply CMD_DM
121
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530122config MACH_PIC32
123 bool "Support Microchip PIC32"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200124 select HAS_FIXED_TIMER_FREQUENCY
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530125 select DM
Tom Rini7d3684a2023-01-16 15:46:49 -0500126 select DM_EVENT
Michal Simek84f3dec2018-07-23 15:55:13 +0200127 select OF_CONTROL
Michal Simek2e7c8192018-07-23 15:55:14 +0200128 imply CMD_DM
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530129
Paul Burtonf5de32a2016-09-08 07:47:39 +0100130config TARGET_BOSTON
131 bool "Support Boston"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200132 select HAS_FIXED_TIMER_FREQUENCY
Paul Burtonf5de32a2016-09-08 07:47:39 +0100133 select DM
134 select DM_SERIAL
Paul Burtonf5de32a2016-09-08 07:47:39 +0100135 select MIPS_CM
Tom Rini3ef67ae2021-08-26 11:47:59 -0400136 select SYS_CACHE_SHIFT_6
Paul Burtonf5de32a2016-09-08 07:47:39 +0100137 select MIPS_L2_CACHE
Paul Burtona315bcd2017-04-30 21:22:42 +0200138 select OF_BOARD_SETUP
Michal Simek84f3dec2018-07-23 15:55:13 +0200139 select OF_CONTROL
140 select ROM_EXCEPTION_VECTORS
Paul Burtonf5de32a2016-09-08 07:47:39 +0100141 select SUPPORTS_BIG_ENDIAN
Paul Burtonf5de32a2016-09-08 07:47:39 +0100142 select SUPPORTS_CPU_MIPS32_R1
143 select SUPPORTS_CPU_MIPS32_R2
144 select SUPPORTS_CPU_MIPS32_R6
145 select SUPPORTS_CPU_MIPS64_R1
146 select SUPPORTS_CPU_MIPS64_R2
147 select SUPPORTS_CPU_MIPS64_R6
Michal Simek84f3dec2018-07-23 15:55:13 +0200148 select SUPPORTS_LITTLE_ENDIAN
Jiaxun Yang40ecb902024-05-17 19:14:55 +0100149 imply BOOTSTD_FULL
150 imply CLK
151 imply CLK_BOSTON
Michal Simek2e7c8192018-07-23 15:55:14 +0200152 imply CMD_DM
Jiaxun Yang40ecb902024-05-17 19:14:55 +0100153 imply AHCI
154 imply AHCI_PCI
155 imply CFI_FLASH
156 imply MTD_NOR_FLASH
157 imply MMC
158 imply MMC_PCI
159 imply MMC_SDHCI
160 imply MMC_SDHCI_SDMA
161 imply PCH_GBE
162 imply PCI
163 imply PCI_XILINX
164 imply PCI_INIT_R
165 imply SCSI
166 imply SCSI_AHCI
167 imply SYS_NS16550
168 imply SYSRESET
169 imply SYSRESET_CMD_POWEROFF
170 imply SYSRESET_SYSCON
171 imply USB
172 imply USB_EHCI_HCD
173 imply USB_EHCI_PCI
174 imply USB_XHCI_HCD
175 imply USB_XHCI_PCI
176 imply CMD_USB
Paul Burtonf5de32a2016-09-08 07:47:39 +0100177
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100178config TARGET_XILFPGA
179 bool "Support Imagination Xilfpga"
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200180 select HAS_FIXED_TIMER_FREQUENCY
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100181 select DM
Michal Simek84f3dec2018-07-23 15:55:13 +0200182 select DM_GPIO
183 select DM_SERIAL
Tom Rini3ef67ae2021-08-26 11:47:59 -0400184 select SYS_CACHE_SHIFT_4
Michal Simek84f3dec2018-07-23 15:55:13 +0200185 select OF_CONTROL
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100186 select ROM_EXCEPTION_VECTORS
Michal Simek84f3dec2018-07-23 15:55:13 +0200187 select SUPPORTS_CPU_MIPS32_R1
188 select SUPPORTS_CPU_MIPS32_R2
189 select SUPPORTS_LITTLE_ENDIAN
Michal Simek2e7c8192018-07-23 15:55:14 +0200190 imply CMD_DM
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100191 help
192 This supports IMGTEC MIPSfpga platform
193
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900194endchoice
195
Paul Burtonf5de32a2016-09-08 07:47:39 +0100196source "board/imgtec/boston/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900197source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +0100198source "board/imgtec/xilfpga/Kconfig"
Wills Wang833a1a82016-03-16 16:59:52 +0800199source "arch/mips/mach-ath79/Kconfig"
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +0100200source "arch/mips/mach-mscc/Kconfig"
Álvaro Fernández Rojas98a97a82017-04-25 00:39:20 +0200201source "arch/mips/mach-bmips/Kconfig"
Paul Burton96c68472018-12-16 19:25:22 -0300202source "arch/mips/mach-jz47xx/Kconfig"
Purna Chandra Mandal825b3212016-01-28 15:30:10 +0530203source "arch/mips/mach-pic32/Kconfig"
developer89f051b2019-04-30 11:13:58 +0800204source "arch/mips/mach-mtmips/Kconfig"
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200205source "arch/mips/mach-octeon/Kconfig"
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900206
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100207if MIPS
208
209choice
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100210 prompt "CPU selection"
211 default CPU_MIPS32_R2
212
213config CPU_MIPS32_R1
214 bool "MIPS32 Release 1"
215 depends on SUPPORTS_CPU_MIPS32_R1
216 select 32BIT
217 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100218 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100219 MIPS32 architecture.
220
221config CPU_MIPS32_R2
222 bool "MIPS32 Release 2"
223 depends on SUPPORTS_CPU_MIPS32_R2
224 select 32BIT
225 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100226 Choose this option to build an U-Boot for release 2 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100227 MIPS32 architecture.
228
Paul Burton55e29dd2016-05-16 10:52:12 +0100229config CPU_MIPS32_R6
230 bool "MIPS32 Release 6"
231 depends on SUPPORTS_CPU_MIPS32_R6
232 select 32BIT
233 help
234 Choose this option to build an U-Boot for release 6 or later of the
235 MIPS32 architecture.
236
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100237config CPU_MIPS64_R1
238 bool "MIPS64 Release 1"
239 depends on SUPPORTS_CPU_MIPS64_R1
240 select 64BIT
241 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100242 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100243 MIPS64 architecture.
244
245config CPU_MIPS64_R2
246 bool "MIPS64 Release 2"
247 depends on SUPPORTS_CPU_MIPS64_R2
248 select 64BIT
249 help
Paul Burton55e29dd2016-05-16 10:52:12 +0100250 Choose this option to build a kernel for release 2 through 5 of the
251 MIPS64 architecture.
252
253config CPU_MIPS64_R6
254 bool "MIPS64 Release 6"
255 depends on SUPPORTS_CPU_MIPS64_R6
256 select 64BIT
257 help
258 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100259 MIPS64 architecture.
260
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200261config CPU_MIPS64_OCTEON
262 bool "Marvell Octeon series of CPUs"
263 depends on SUPPORTS_CPU_MIPS64_OCTEON
264 select 64BIT
265 help
266 Choose this option for Marvell Octeon CPUs. These CPUs are between
267 MIPS64 R5 and R6 with other extensions.
268
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100269endchoice
270
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100271menu "General setup"
272
273config ROM_EXCEPTION_VECTORS
274 bool "Build U-Boot image with exception vectors"
275 help
276 Enable this to include exception vectors in the U-Boot image. This is
277 required if the U-Boot entry point is equal to the address of the
278 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
279 U-Boot booted from parallel NOR flash).
280 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
281 In that case the image size will be reduced by 0x500 bytes.
282
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200283config SYS_MIPS_TIMER_FREQ
284 int "Fixed MIPS CPU timer frequency in Hz"
285 depends on HAS_FIXED_TIMER_FREQUENCY
286 help
287 Configures a fixed CPU timer frequency.
288
Paul Burton3d6864a2017-05-12 13:26:11 +0200289config MIPS_CM_BASE
290 hex "MIPS CM GCR Base Address"
291 depends on MIPS_CM
Paul Burtona6ac9652017-04-30 21:22:41 +0200292 default 0x16100000 if TARGET_BOSTON
Paul Burton3d6864a2017-05-12 13:26:11 +0200293 default 0x1fbf8000
294 help
295 The physical base address at which to map the MIPS Coherence Manager
296 Global Configuration Registers (GCRs). This should be set such that
297 the GCRs occupy a region of the physical address space which is
298 otherwise unused, or at minimum that software doesn't need to access.
299
Daniel Schwierzecke3b432d2018-09-07 19:02:05 +0200300config MIPS_CACHE_INDEX_BASE
301 hex "Index base address for cache initialisation"
302 default 0x80000000 if CPU_MIPS32
303 default 0xffffffff80000000 if CPU_MIPS64
304 help
305 This is the base address for a memory block, which is used for
306 initialising the cache lines. This is also the base address of a memory
307 block which is used for loading and filling cache lines when
308 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
309 Normally this is CKSEG0. If the MIPS system needs to move this block
310 to some SRAM or ScratchPad RAM, adapt this option accordingly.
311
Stefan Roesec6f54b42020-06-30 12:33:16 +0200312config MIPS_MACH_EARLY_INIT
313 bool "Enable mach specific very early init code"
314 help
315 Use this to enable the call to mips_mach_early_init() very early
316 from start.S. This function can be used e.g. to do some very early
317 CPU / SoC intitialization or image copying. Its called very early
318 and at this stage the PC might not match the linking address
319 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
320
Daniel Schwierzeckc95e7f12020-07-12 00:45:57 +0200321config MIPS_CACHE_SETUP
322 bool "Allow generic start code to initialize and setup caches"
323 default n if SKIP_LOWLEVEL_INIT
324 default y
325 help
326 This allows the generic start code to invoke the generic initialization
327 of the CPU caches. Disabling this can be useful for RAM boot scenarios
328 (EJTAG, SPL payload) or for machines which don't need cache initialization
329 or which want to provide their own cache implementation.
330
331 If unsure, say yes.
332
333config MIPS_CACHE_DISABLE
334 bool "Allow generic start code to initially disable caches"
335 default n if SKIP_LOWLEVEL_INIT
336 default y
337 help
338 This allows the generic start code to initially disable the CPU caches
339 and run uncached until the caches are initialized and enabled. Disabling
340 this can be useful on machines which don't need cache initialization or
341 which want to provide their own cache implementation.
342
343 If unsure, say yes.
344
Daniel Schwierzeck80132862018-11-01 02:02:21 +0100345config MIPS_RELOCATION_TABLE_SIZE
346 hex "Relocation table size"
347 range 0x100 0x10000
348 default "0x8000"
349 ---help---
350 A table of relocation data will be appended to the U-Boot binary
351 and parsed in relocate_code() to fix up all offsets in the relocated
352 U-Boot.
353
354 This option allows the amount of space reserved for the table to be
355 adjusted in a range from 256 up to 64k. The default is 32k and should
356 be ok in most cases. Reduce this value to shrink the size of U-Boot
357 binary.
358
359 The build will fail and a valid size suggested if this is too small.
360
361 If unsure, leave at the default value.
362
developer5cbbd712020-04-21 09:28:25 +0200363config RESTORE_EXCEPTION_VECTOR_BASE
364 bool "Restore exception vector base before booting linux kernel"
developer5cbbd712020-04-21 09:28:25 +0200365 help
366 In U-Boot the exception vector base will be moved to top of memory,
367 to be used to display register dump when exception occurs.
368 But some old linux kernel does not honor the base set in CP0_EBASE.
369 A modified exception vector base will cause kernel crash.
370
371 This option will restore the exception vector base to its previous
372 value.
373
374 If unsure, say N.
375
376config OVERRIDE_EXCEPTION_VECTOR_BASE
377 bool "Override the exception vector base to be restored"
378 depends on RESTORE_EXCEPTION_VECTOR_BASE
developer5cbbd712020-04-21 09:28:25 +0200379 help
380 Enable this option if you want to use a different exception vector
381 base rather than the previously saved one.
382
383config NEW_EXCEPTION_VECTOR_BASE
384 hex "New exception vector base"
385 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
386 range 0x80000000 0xbffff000
387 default 0x80000000
388 help
389 The exception vector base to be restored before booting linux kernel
390
developer01a28282020-04-21 09:28:33 +0200391config INIT_STACK_WITHOUT_MALLOC_F
392 bool "Do not reserve malloc space on initial stack"
developer01a28282020-04-21 09:28:33 +0200393 help
394 Enable this option if you don't want to reserve malloc space on
395 initial stack. This is useful if the initial stack can't hold large
396 malloc space. Platform should set the malloc_base later when DRAM is
397 ready to use.
398
399config SPL_INIT_STACK_WITHOUT_MALLOC_F
400 bool "Do not reserve malloc space on initial stack in SPL"
developer01a28282020-04-21 09:28:33 +0200401 help
402 Enable this option if you don't want to reserve malloc space on
403 initial stack. This is useful if the initial stack can't hold large
404 malloc space. Platform should set the malloc_base later when DRAM is
405 ready to use.
406
developer25678a02020-04-21 09:28:37 +0200407config SPL_LOADER_SUPPORT
408 bool
developer25678a02020-04-21 09:28:37 +0200409 help
410 Enable this option if you want to use SPL loaders without DM enabled.
411
Daniel Schwierzeck754cd052016-02-14 18:52:57 +0100412endmenu
413
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100414menu "OS boot interface"
415
416config MIPS_BOOT_CMDLINE_LEGACY
417 bool "Hand over legacy command line to Linux kernel"
418 default y
419 help
420 Enable this option if you want U-Boot to hand over the Yamon-style
421 command line to the kernel. All bootargs will be prepared as argc/argv
422 compatible list. The argument count (argc) is stored in register $a0.
423 The address of the argument list (argv) is stored in register $a1.
424
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100425config MIPS_BOOT_ENV_LEGACY
426 bool "Hand over legacy environment to Linux kernel"
427 default y
428 help
429 Enable this option if you want U-Boot to hand over the Yamon-style
430 environment to the kernel. Information like memory size, initrd
431 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day8c60f922016-05-04 04:47:31 -0400432 The address of the environment is stored in register $a2.
Daniel Schwierzeckc07dc602015-01-14 21:44:13 +0100433
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100434config MIPS_BOOT_FDT
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100435 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100436 help
437 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeckd1b29d22015-02-22 16:58:30 +0100438 device tree to the kernel. According to UHI register $a0 will be set
439 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck8d7ff4d2015-01-14 21:44:13 +0100440
Daniel Schwierzeckf9749fa2015-01-14 21:44:13 +0100441endmenu
442
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100443config SUPPORTS_BIG_ENDIAN
444 bool
445
446config SUPPORTS_LITTLE_ENDIAN
447 bool
448
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100449config SUPPORTS_CPU_MIPS32_R1
450 bool
451
452config SUPPORTS_CPU_MIPS32_R2
453 bool
454
Paul Burton55e29dd2016-05-16 10:52:12 +0100455config SUPPORTS_CPU_MIPS32_R6
456 bool
457
Daniel Schwierzeck256034d2014-10-26 14:14:07 +0100458config SUPPORTS_CPU_MIPS64_R1
459 bool
460
461config SUPPORTS_CPU_MIPS64_R2
462 bool
463
Paul Burton55e29dd2016-05-16 10:52:12 +0100464config SUPPORTS_CPU_MIPS64_R6
465 bool
466
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200467config SUPPORTS_CPU_MIPS64_OCTEON
468 bool
469
Daniel Schwierzeckff21b842022-07-10 17:15:14 +0200470config HAS_FIXED_TIMER_FREQUENCY
471 bool
472
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200473config CPU_CAVIUM_OCTEON
474 bool
475
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100476config CPU_MIPS32
477 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100478 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100479
480config CPU_MIPS64
481 bool
Paul Burton55e29dd2016-05-16 10:52:12 +0100482 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200483 default y if CPU_MIPS64_OCTEON
Daniel Schwierzeckdfbad0f2015-01-18 21:59:35 +0100484
Daniel Schwierzeckaadd3322015-12-26 19:55:37 +0100485config MIPS_TUNE_4KC
486 bool
487
488config MIPS_TUNE_14KC
489 bool
490
491config MIPS_TUNE_24KC
492 bool
493
Daniel Schwierzeckc7661d52016-05-27 15:39:39 +0200494config MIPS_TUNE_34KC
495 bool
496
Marek Vasuta9c6e8b2016-05-06 20:10:33 +0200497config MIPS_TUNE_74KC
498 bool
499
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200500config MIPS_TUNE_OCTEON3
501 bool
502
Daniel Schwierzeck7dca6862015-01-18 22:00:18 +0100503config SWAP_IO_SPACE
504 bool
505
Paul Burton6832bdc2015-01-29 01:28:02 +0000506config SYS_MIPS_CACHE_INIT_RAM_LOAD
507 bool
508
Daniel Schwierzeck41dc35e2016-06-04 16:13:21 +0200509config MIPS_INIT_STACK_IN_SRAM
510 bool
Daniel Schwierzeck41dc35e2016-06-04 16:13:21 +0200511 help
512 Select this if the initial stack frame could be setup in SRAM.
513 Normally the initial stack frame is set up in DRAM which is often
514 only available after lowlevel_init. With this option the initial
515 stack frame and the early C environment is set up before
516 lowlevel_init. Thus lowlevel_init does not need to be implemented
517 in assembler.
518
developereb7d3a22020-04-21 09:28:27 +0200519config MIPS_SRAM_INIT
520 bool
developereb7d3a22020-04-21 09:28:27 +0200521 depends on MIPS_INIT_STACK_IN_SRAM
522 help
523 Select this if the SRAM for initial stack needs to be initialized
524 before it can be used. If enabled, a function mips_sram_init() will
525 be called just before setup_stack_gd.
526
Aaron Williamsb2ea8182020-06-30 12:08:56 +0200527config DMA_ADDR_T_64BIT
528 bool
529 help
530 Select this to enable 64-bit DMA addressing
531
Paul Burton5e511422016-05-27 14:28:04 +0100532config SYS_DCACHE_SIZE
533 int
534 default 0
535 help
536 The total size of the L1 Dcache, if known at compile time.
537
Paul Burton62f13522016-05-27 14:28:05 +0100538config SYS_DCACHE_LINE_SIZE
Paul Burton79e49fd2016-06-09 13:09:52 +0100539 int
Paul Burton62f13522016-05-27 14:28:05 +0100540 default 0
541 help
542 The size of L1 Dcache lines, if known at compile time.
543
Paul Burton5e511422016-05-27 14:28:04 +0100544config SYS_ICACHE_SIZE
545 int
546 default 0
547 help
548 The total size of the L1 ICache, if known at compile time.
549
Paul Burton62f13522016-05-27 14:28:05 +0100550config SYS_ICACHE_LINE_SIZE
Paul Burton5e511422016-05-27 14:28:04 +0100551 int
552 default 0
553 help
Paul Burton62f13522016-05-27 14:28:05 +0100554 The size of L1 Icache lines, if known at compile time.
Paul Burton5e511422016-05-27 14:28:04 +0100555
Ramon Fried7e07e492019-06-10 21:05:26 +0300556config SYS_SCACHE_LINE_SIZE
557 int
558 default 0
559 help
560 The size of L2 cache lines, if known at compile time.
561
562
Paul Burton5e511422016-05-27 14:28:04 +0100563config SYS_CACHE_SIZE_AUTO
564 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Ramon Fried7e07e492019-06-10 21:05:26 +0300565 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
566 SYS_SCACHE_LINE_SIZE = 0
Paul Burton5e511422016-05-27 14:28:04 +0100567 help
568 Select this (or let it be auto-selected by not defining any cache
569 sizes) in order to allow U-Boot to automatically detect the sizes
570 of caches at runtime. This has a small cost in code size & runtime
571 so if you know the cache configuration for your system at compile
572 time it would be beneficial to configure it.
573
Paul Burton81560782016-09-21 11:18:54 +0100574config MIPS_L2_CACHE
575 bool
576 help
577 Select this if your system includes an L2 cache and you want U-Boot
578 to initialise & maintain it.
579
Paul Burton8d6600b2016-01-29 13:54:52 +0000580config DYNAMIC_IO_PORT_BASE
581 bool
582
Paul Burton79ac1742016-09-21 11:18:53 +0100583config MIPS_CM
584 bool
585 help
586 Select this if your system contains a MIPS Coherence Manager and you
587 wish U-Boot to configure it or make use of it to retrieve system
588 information such as cache configuration.
589
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +0200590config MIPS_INSERT_BOOT_CONFIG
591 bool
Daniel Schwierzeck2cc9a772018-09-07 19:18:44 +0200592 help
593 Enable this to insert some board-specific boot configuration in
594 the U-Boot binary at offset 0x10.
595
596config MIPS_BOOT_CONFIG_WORD0
597 hex
598 depends on MIPS_INSERT_BOOT_CONFIG
599 default 0x420 if TARGET_MALTA
600 default 0x0
601 help
602 Value which is inserted as boot config word 0.
603
604config MIPS_BOOT_CONFIG_WORD1
605 hex
606 depends on MIPS_INSERT_BOOT_CONFIG
607 default 0x0
608 help
609 Value which is inserted as boot config word 1.
610
Daniel Schwierzecka4c242b2014-10-26 14:14:07 +0100611endif
612
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900613endmenu