Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Masahiro Yamada | 0b67e56 | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 2 | * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Masahiro Yamada | c5864d8 | 2020-04-22 10:50:12 +0900 | [diff] [blame] | 7 | /* |
| 8 | * The .data section gets copied from ROM to RAM at runtime. |
| 9 | * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes |
| 10 | * aligned regions in it. |
| 11 | * Its VMA must be page-aligned as it marks the first read/write page. |
| 12 | */ |
| 13 | #define DATA_ALIGN 16 |
| 14 | |
Masahiro Yamada | 0b67e56 | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 15 | #include <common/bl_common.ld.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 17 | |
| 18 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 19 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 20 | ENTRY(bl1_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 21 | |
| 22 | MEMORY { |
Juan Castillo | fd8c077 | 2014-09-16 10:40:35 +0100 | [diff] [blame] | 23 | ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE |
| 24 | RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 25 | } |
| 26 | |
| 27 | SECTIONS |
| 28 | { |
Sandrine Bailleux | f748806 | 2014-05-22 15:21:35 +0100 | [diff] [blame] | 29 | . = BL1_RO_BASE; |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 30 | ASSERT(. == ALIGN(PAGE_SIZE), |
Sandrine Bailleux | f748806 | 2014-05-22 15:21:35 +0100 | [diff] [blame] | 31 | "BL1_RO_BASE address is not aligned on a page boundary.") |
| 32 | |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 33 | #if SEPARATE_CODE_AND_RODATA |
| 34 | .text . : { |
| 35 | __TEXT_START__ = .; |
| 36 | *bl1_entrypoint.o(.text*) |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 37 | *(SORT_BY_ALIGNMENT(.text*)) |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 38 | *(.vectors) |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 39 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 40 | __TEXT_END__ = .; |
Jorge Troncoso | da284d5 | 2022-10-20 21:42:06 -0700 | [diff] [blame] | 41 | } >ROM |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 42 | |
Jorge Troncoso | da284d5 | 2022-10-20 21:42:06 -0700 | [diff] [blame] | 43 | /* .ARM.extab and .ARM.exidx are only added because Clang need them */ |
| 44 | .ARM.extab . : { |
Roberto Vargas | 1d04c63 | 2018-05-10 11:01:16 +0100 | [diff] [blame] | 45 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
Jorge Troncoso | da284d5 | 2022-10-20 21:42:06 -0700 | [diff] [blame] | 46 | } >ROM |
Roberto Vargas | 1d04c63 | 2018-05-10 11:01:16 +0100 | [diff] [blame] | 47 | |
Jorge Troncoso | da284d5 | 2022-10-20 21:42:06 -0700 | [diff] [blame] | 48 | .ARM.exidx . : { |
Roberto Vargas | 1d04c63 | 2018-05-10 11:01:16 +0100 | [diff] [blame] | 49 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
Jorge Troncoso | da284d5 | 2022-10-20 21:42:06 -0700 | [diff] [blame] | 50 | } >ROM |
Roberto Vargas | 1d04c63 | 2018-05-10 11:01:16 +0100 | [diff] [blame] | 51 | |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 52 | .rodata . : { |
| 53 | __RODATA_START__ = .; |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 54 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 55 | |
Masahiro Yamada | 583f8dd | 2020-03-26 10:57:12 +0900 | [diff] [blame] | 56 | RODATA_COMMON |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * No need to pad out the .rodata section to a page boundary. Next is |
| 60 | * the .data section, which can mapped in ROM with the same memory |
| 61 | * attributes as the .rodata section. |
Arve Hjønnevåg | 1488cbe | 2020-02-07 14:12:35 -0800 | [diff] [blame] | 62 | * |
| 63 | * Pad out to 16 bytes though as .data section needs to be 16 byte |
| 64 | * aligned and lld does not align the LMA to the aligment specified |
| 65 | * on the .data section. |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 66 | */ |
| 67 | __RODATA_END__ = .; |
Arve Hjønnevåg | 1488cbe | 2020-02-07 14:12:35 -0800 | [diff] [blame] | 68 | . = ALIGN(16); |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 69 | } >ROM |
| 70 | #else |
Sandrine Bailleux | f748806 | 2014-05-22 15:21:35 +0100 | [diff] [blame] | 71 | ro . : { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 72 | __RO_START__ = .; |
Andrew Thoelke | e01ea34 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 73 | *bl1_entrypoint.o(.text*) |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 74 | *(SORT_BY_ALIGNMENT(.text*)) |
| 75 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 76 | |
Masahiro Yamada | 583f8dd | 2020-03-26 10:57:12 +0900 | [diff] [blame] | 77 | RODATA_COMMON |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 78 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 79 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 80 | __RO_END__ = .; |
Arve Hjønnevåg | 1488cbe | 2020-02-07 14:12:35 -0800 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * Pad out to 16 bytes as .data section needs to be 16 byte aligned and |
| 84 | * lld does not align the LMA to the aligment specified on the .data |
| 85 | * section. |
| 86 | */ |
| 87 | . = ALIGN(16); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 88 | } >ROM |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 89 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 90 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 91 | ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, |
| 92 | "cpu_ops not defined for this platform.") |
| 93 | |
Douglas Raillard | 306593d | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 94 | . = BL1_RW_BASE; |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 95 | ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), |
Douglas Raillard | 306593d | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 96 | "BL1_RW_BASE address is not aligned on a page boundary.") |
| 97 | |
Masahiro Yamada | c5864d8 | 2020-04-22 10:50:12 +0900 | [diff] [blame] | 98 | DATA_SECTION >RAM AT>ROM |
| 99 | __DATA_RAM_START__ = __DATA_START__; |
| 100 | __DATA_RAM_END__ = __DATA_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | |
Masahiro Yamada | 403990e | 2020-04-07 13:04:24 +0900 | [diff] [blame] | 102 | STACK_SECTION >RAM |
Masahiro Yamada | dd053b6 | 2020-03-26 13:16:33 +0900 | [diff] [blame] | 103 | BSS_SECTION >RAM |
Masahiro Yamada | 0b67e56 | 2020-03-09 17:39:48 +0900 | [diff] [blame] | 104 | XLAT_TABLE_SECTION >RAM |
Jeenu Viswambharan | 74cbb83 | 2014-02-17 17:26:51 +0000 | [diff] [blame] | 105 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 106 | #if USE_COHERENT_MEM |
Jeenu Viswambharan | 74cbb83 | 2014-02-17 17:26:51 +0000 | [diff] [blame] | 107 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 108 | * The base address of the coherent memory section must be page-aligned (4K) |
| 109 | * to guarantee that the coherent data are stored on their own pages and |
| 110 | * are not mixed with normal data. This is required to set up the correct |
| 111 | * memory attributes for the coherent data page tables. |
| 112 | */ |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 113 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 114 | __COHERENT_RAM_START__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | *(tzfw_coherent_mem) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 116 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 117 | /* |
| 118 | * Memory page(s) mapped to this section will be marked |
| 119 | * as device memory. No other unexpected data must creep in. |
| 120 | * Ensure the rest of the current memory page is unused. |
| 121 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 122 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 123 | __COHERENT_RAM_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 124 | } >RAM |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 125 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 126 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 127 | __BL1_RAM_START__ = ADDR(.data); |
| 128 | __BL1_RAM_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 129 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 130 | __DATA_ROM_START__ = LOADADDR(.data); |
| 131 | __DATA_SIZE__ = SIZEOF(.data); |
Sandrine Bailleux | 6c2daed | 2016-06-15 13:53:50 +0100 | [diff] [blame] | 132 | |
Sandrine Bailleux | 6c8b359 | 2014-05-22 15:28:26 +0100 | [diff] [blame] | 133 | /* |
| 134 | * The .data section is the last PROGBITS section so its end marks the end |
Sandrine Bailleux | 6c2daed | 2016-06-15 13:53:50 +0100 | [diff] [blame] | 135 | * of BL1's actual content in Trusted ROM. |
Sandrine Bailleux | 6c8b359 | 2014-05-22 15:28:26 +0100 | [diff] [blame] | 136 | */ |
Sandrine Bailleux | 6c2daed | 2016-06-15 13:53:50 +0100 | [diff] [blame] | 137 | __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; |
| 138 | ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, |
| 139 | "BL1's ROM content has exceeded its limit.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 140 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 141 | __BSS_SIZE__ = SIZEOF(.bss); |
| 142 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 143 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 144 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 145 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 146 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 147 | |
Sandrine Bailleux | 6c8b359 | 2014-05-22 15:28:26 +0100 | [diff] [blame] | 148 | ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | } |