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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37MEMORY {
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
40}
41
42SECTIONS
43{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000044 ro : {
45 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000046 *bl1_entrypoint.o(.text*)
47 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048 *(.rodata*)
Achin Guptab739f222014-01-18 16:50:09 +000049 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000050 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 } >ROM
52
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000053 /*
54 * The .data section gets copied from ROM to RAM at runtime.
55 * Its LMA and VMA must be 16-byte aligned.
56 */
57 . = NEXT(16); /* Align LMA */
58 .data : ALIGN(16) { /* Align VMA */
Achin Gupta4f6ad662013-10-25 09:08:21 +010059 __DATA_RAM_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000060 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000061 __DATA_RAM_END__ = .;
62 } >RAM AT>ROM
Achin Gupta4f6ad662013-10-25 09:08:21 +010063
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000064 stacks (NOLOAD) : {
65 __STACKS_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010066 *(tzfw_normal_stacks)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000067 __STACKS_END__ = .;
68 } >RAM
69
70 /*
71 * The .bss section gets initialised to 0 at runtime.
72 * Its base address must be 16-byte aligned.
73 */
74 .bss : ALIGN(16) {
75 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000076 *(.bss*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000077 *(COMMON)
78 __BSS_END__ = .;
79 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +010080
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000081 /*
Achin Guptaa0cd9892014-02-09 13:30:38 +000082 * The xlat_table section is for full, aligned page tables (4K).
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +000083 * Removing them from .bss avoids forcing 4K alignment on
84 * the .bss section and eliminates the unecessary zero init
85 */
86 xlat_table (NOLOAD) : {
87 *(xlat_table)
88 } >RAM
89
90 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000091 * The base address of the coherent memory section must be page-aligned (4K)
92 * to guarantee that the coherent data are stored on their own pages and
93 * are not mixed with normal data. This is required to set up the correct
94 * memory attributes for the coherent data page tables.
95 */
96 coherent_ram (NOLOAD) : ALIGN(4096) {
97 __COHERENT_RAM_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010098 *(tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000099 __COHERENT_RAM_END_UNALIGNED__ = .;
100 /*
101 * Memory page(s) mapped to this section will be marked
102 * as device memory. No other unexpected data must creep in.
103 * Ensure the rest of the current memory page is unused.
104 */
105 . = NEXT(4096);
106 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 } >RAM
108
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000109 __BL1_RAM_START__ = ADDR(.data);
110 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000112 __DATA_ROM_START__ = LOADADDR(.data);
113 __DATA_SIZE__ = SIZEOF(.data);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000115 __BSS_SIZE__ = SIZEOF(.bss);
116
117 __COHERENT_RAM_UNALIGNED_SIZE__ =
118 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119
Achin Guptae4d084e2014-02-19 17:18:23 +0000120 ASSERT(. <= BL31_BASE, "BL1 image overlaps BL31 image.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121}