| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <platform.h> |
| 32 | |
| 33 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 34 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
| 35 | |
| 36 | MEMORY { |
| 37 | /* ROM is read-only and executable */ |
| 38 | ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE |
| 39 | /* RAM is read/write and Initialised */ |
| 40 | RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE |
| 41 | } |
| 42 | |
| 43 | SECTIONS |
| 44 | { |
| 45 | FIRMWARE_ROM : { |
| 46 | *(reset_code) |
| 47 | *(.text) |
| 48 | *(.rodata) |
| 49 | } >ROM |
| 50 | |
| 51 | .bss : { |
| 52 | __BSS_RAM_START__ = .; |
| 53 | *(.bss) |
| 54 | *(COMMON) |
| 55 | __BSS_RAM_STOP__ = .; |
| 56 | } >RAM AT>ROM |
| 57 | |
| 58 | .data : { |
| 59 | __DATA_RAM_START__ = .; |
| 60 | *(.data) |
| 61 | __DATA_RAM_STOP__ = .; |
| 62 | } >RAM AT>ROM |
| 63 | |
| 64 | FIRMWARE_RAM_STACKS ALIGN (PLATFORM_CACHE_LINE_SIZE) : { |
| 65 | . += 0x1000; |
| 66 | *(tzfw_normal_stacks) |
| 67 | . = ALIGN(4096); |
| 68 | } >RAM AT>ROM |
| 69 | |
| 70 | FIRMWARE_RAM_COHERENT ALIGN (4096): { |
| 71 | *(tzfw_coherent_mem) |
| 72 | /* . += 0x1000;*/ |
| 73 | /* Do we need to make sure this is at least 4k? */ |
| 74 | . = ALIGN(4096); |
| 75 | } >RAM |
| 76 | |
| 77 | __FIRMWARE_ROM_START__ = LOADADDR(FIRMWARE_ROM); |
| 78 | __FIRMWARE_ROM_SIZE__ = SIZEOF(FIRMWARE_ROM); |
| 79 | |
| 80 | __FIRMWARE_DATA_START__ = LOADADDR(.data); |
| 81 | __FIRMWARE_DATA_SIZE__ = SIZEOF(.data); |
| 82 | |
| 83 | __FIRMWARE_BSS_START__ = LOADADDR(.bss); |
| 84 | __FIRMWARE_BSS_SIZE__ = SIZEOF(.bss); |
| 85 | |
| 86 | __FIRMWARE_RAM_STACKS_START__ = LOADADDR(FIRMWARE_RAM_STACKS); |
| 87 | __FIRMWARE_RAM_STACKS_SIZE__ = SIZEOF(FIRMWARE_RAM_STACKS); |
| 88 | __FIRMWARE_RAM_COHERENT_START__ = LOADADDR(FIRMWARE_RAM_COHERENT); |
| 89 | __FIRMWARE_RAM_COHERENT_SIZE__ = SIZEOF(FIRMWARE_RAM_COHERENT); |
| 90 | } |