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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Chris Kay33bfc5e2023-02-14 11:30:04 +00002 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Masahiro Yamadac5864d82020-04-22 10:50:12 +09007/*
Chris Kay4b7660a2022-09-29 14:36:53 +01008 * The .data section gets copied from ROM to RAM at runtime. Its LMA should be
9 * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it.
Masahiro Yamadac5864d82020-04-22 10:50:12 +090010 * Its VMA must be page-aligned as it marks the first read/write page.
11 */
12#define DATA_ALIGN 16
13
Masahiro Yamada0b67e562020-03-09 17:39:48 +090014#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010016
17OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
18OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000019ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
21MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010022 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
23 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010024}
25
Chris Kay4b7660a2022-09-29 14:36:53 +010026SECTIONS {
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010027 . = BL1_RO_BASE;
Chris Kay4b7660a2022-09-29 14:36:53 +010028
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000029 ASSERT(. == ALIGN(PAGE_SIZE),
Chris Kay4b7660a2022-09-29 14:36:53 +010030 "BL1_RO_BASE address is not aligned on a page boundary.")
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010031
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032#if SEPARATE_CODE_AND_RODATA
33 .text . : {
34 __TEXT_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010035
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010036 *bl1_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050037 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010038 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010039
Roberto Vargasd93fde32018-04-11 11:53:31 +010040 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010041
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010042 __TEXT_END__ = .;
Jorge Troncosoda284d52022-10-20 21:42:06 -070043 } >ROM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010044
Chris Kay4b7660a2022-09-29 14:36:53 +010045 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
Jorge Troncosoda284d52022-10-20 21:42:06 -070046 .ARM.extab . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010047 *(.ARM.extab* .gnu.linkonce.armextab.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070048 } >ROM
Roberto Vargas1d04c632018-05-10 11:01:16 +010049
Jorge Troncosoda284d52022-10-20 21:42:06 -070050 .ARM.exidx . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010051 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070052 } >ROM
Roberto Vargas1d04c632018-05-10 11:01:16 +010053
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010054 .rodata . : {
55 __RODATA_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010056
Samuel Holland23f5e542019-10-20 16:11:25 -050057 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010058
Chris Kay4b7660a2022-09-29 14:36:53 +010059 RODATA_COMMON
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010060
61 /*
62 * No need to pad out the .rodata section to a page boundary. Next is
63 * the .data section, which can mapped in ROM with the same memory
64 * attributes as the .rodata section.
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080065 *
Chris Kay4b7660a2022-09-29 14:36:53 +010066 * Pad out to 16 bytes though as .data section needs to be 16-byte
67 * aligned and lld does not align the LMA to the alignment specified
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080068 * on the .data section.
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010069 */
70 __RODATA_END__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010071
72 . = ALIGN(16);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010073 } >ROM
Chris Kay4b7660a2022-09-29 14:36:53 +010074#else /* SEPARATE_CODE_AND_RODATA */
Chris Kay33bfc5e2023-02-14 11:30:04 +000075 .ro . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000076 __RO_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010077
Andrew Thoelkee01ea342014-03-18 07:13:52 +000078 *bl1_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050079 *(SORT_BY_ALIGNMENT(.text*))
80 *(SORT_BY_ALIGNMENT(.rodata*))
Soby Mathewc704cbc2014-08-14 11:33:56 +010081
Chris Kay4b7660a2022-09-29 14:36:53 +010082 RODATA_COMMON
Soby Mathewc704cbc2014-08-14 11:33:56 +010083
Achin Guptab739f222014-01-18 16:50:09 +000084 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010085
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000086 __RO_END__ = .;
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080087
88 /*
Chris Kay4b7660a2022-09-29 14:36:53 +010089 * Pad out to 16 bytes as the .data section needs to be 16-byte aligned
90 * and lld does not align the LMA to the alignment specified on the
91 * .data section.
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080092 */
Chris Kay4b7660a2022-09-29 14:36:53 +010093 . = ALIGN(16);
Achin Gupta4f6ad662013-10-25 09:08:21 +010094 } >ROM
Chris Kay4b7660a2022-09-29 14:36:53 +010095#endif /* SEPARATE_CODE_AND_RODATA */
Achin Gupta4f6ad662013-10-25 09:08:21 +010096
Soby Mathewc704cbc2014-08-14 11:33:56 +010097 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
Chris Kay4b7660a2022-09-29 14:36:53 +010098 "cpu_ops not defined for this platform.")
Soby Mathewc704cbc2014-08-14 11:33:56 +010099
Douglas Raillard306593d2017-02-24 18:14:15 +0000100 . = BL1_RW_BASE;
Chris Kay4b7660a2022-09-29 14:36:53 +0100101
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000102 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
Chris Kay4b7660a2022-09-29 14:36:53 +0100103 "BL1_RW_BASE address is not aligned on a page boundary.")
Douglas Raillard306593d2017-02-24 18:14:15 +0000104
Masahiro Yamadac5864d82020-04-22 10:50:12 +0900105 DATA_SECTION >RAM AT>ROM
Chris Kay4b7660a2022-09-29 14:36:53 +0100106
Masahiro Yamadac5864d82020-04-22 10:50:12 +0900107 __DATA_RAM_START__ = __DATA_START__;
108 __DATA_RAM_END__ = __DATA_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109
Masahiro Yamada403990e2020-04-07 13:04:24 +0900110 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +0900111 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +0900112 XLAT_TABLE_SECTION >RAM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000113
Soby Mathew2ae20432015-01-08 18:02:44 +0000114#if USE_COHERENT_MEM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000115 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100116 * The base address of the coherent memory section must be page-aligned to
117 * guarantee that the coherent data are stored on their own pages and are
118 * not mixed with normal data. This is required to set up the correct memory
119 * attributes for the coherent data page tables.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000120 */
Chris Kay33bfc5e2023-02-14 11:30:04 +0000121 .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000122 __COHERENT_RAM_START__ = .;
Chris Kay33bfc5e2023-02-14 11:30:04 +0000123 *(.tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000124 __COHERENT_RAM_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +0100125
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000126 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100127 * Memory page(s) mapped to this section will be marked as device
128 * memory. No other unexpected data must creep in. Ensure the rest of
129 * the current memory page is unused.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000130 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100131 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +0100132
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000133 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +0100135#endif /* USE_COHERENT_MEM */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000137 __BL1_RAM_START__ = ADDR(.data);
138 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000140 __DATA_ROM_START__ = LOADADDR(.data);
141 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100142
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100143 /*
144 * The .data section is the last PROGBITS section so its end marks the end
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100145 * of BL1's actual content in Trusted ROM.
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100146 */
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100147 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
Chris Kay4b7660a2022-09-29 14:36:53 +0100148
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100149 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
Chris Kay4b7660a2022-09-29 14:36:53 +0100150 "BL1's ROM content has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000152 __BSS_SIZE__ = SIZEOF(.bss);
153
Soby Mathew2ae20432015-01-08 18:02:44 +0000154#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000155 __COHERENT_RAM_UNALIGNED_SIZE__ =
156 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Chris Kay4b7660a2022-09-29 14:36:53 +0100157#endif /* USE_COHERENT_MEM */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100159 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160}