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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Vijayenthiran Subramaniam884cc022023-12-21 17:34:05 +05302 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -06007#include <assert.h>
8#include <common/debug.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <drivers/arm/smmu_v3.h>
laurenw-arm9656a302020-06-10 16:33:18 -050010#include <fconf_hw_config_getter.h>
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -060011#include <lib/fconf/fconf.h>
Manish V Badarkhe8717e032020-05-30 17:40:44 +010012#include <lib/fconf/fconf_dyn_cfg_getter.h>
laurenw-arm9656a302020-06-10 16:33:18 -050013#include <lib/mmio.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/arm_config.h>
15#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/platform.h>
17
Dan Handleyed6ff952014-05-14 17:44:19 +010018#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
Manish V Badarkhe86854e72022-03-15 16:05:58 +000020static const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
21
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +010022void __init bl31_early_platform_setup2(u_register_t arg0,
23 u_register_t arg1, u_register_t arg2, u_register_t arg3)
Achin Gupta4f6ad662013-10-25 09:08:21 +010024{
Juan Pablo Condeb36eca12022-02-01 15:19:58 -050025 /* Initialize the console to provide early debug support */
26 arm_console_boot_init();
27
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060028#if !RESET_TO_BL31 && !RESET_TO_BL2
Manish V Badarkhe8717e032020-05-30 17:40:44 +010029 const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
30
31 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
32 /* Fill the properties struct with the info from the config dtb */
33 fconf_populate("FW_CONFIG", arg1);
34
35 soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID);
36 if (soc_fw_config_info != NULL) {
37 arg1 = soc_fw_config_info->config_addr;
38 }
Manish V Badarkhe86854e72022-03-15 16:05:58 +000039
40 /*
41 * arg2 is currently holding the 'secure' address of HW_CONFIG.
42 * But arm_bl31_early_platform_setup() below expects the 'non-secure'
43 * address of HW_CONFIG (which it will pass to BL33).
44 * This why we need to override arg2 here.
45 */
46 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
47 assert(hw_config_info != NULL);
Manish V Badarkheb2e34ff2023-02-07 11:26:38 +000048 assert(hw_config_info->secondary_config_addr != 0UL);
49 arg2 = hw_config_info->secondary_config_addr;
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060050#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 */
Manish V Badarkhe8717e032020-05-30 17:40:44 +010051
Soby Mathew7d5a2e72018-01-10 15:59:31 +000052 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000053
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010055 fvp_config_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +010056
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010057 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000058 * Initialize the correct interconnect for this cluster during cold
59 * boot. No need for locks as no other CPU is active.
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010060 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000061 fvp_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010062
Dan Handley2b6b5742015-03-19 19:17:53 +000063 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000064 * Enable coherency in interconnect for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010065 * Earlier bootloader stages might already do this (e.g. Trusted
66 * Firmware's BL1 does it) but we can't assume so. There is no harm in
67 * executing this code twice anyway.
Dan Handley2b6b5742015-03-19 19:17:53 +000068 * FVP PSCI code will enable coherency for other clusters.
69 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000070 fvp_interconnect_enable();
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +010071
Alexei Fedorov7131d832019-08-16 14:15:59 +010072 /* Initialize System level generic or SP804 timer */
73 fvp_timer_init();
74
Alexei Fedorov6b4a5f02019-04-26 12:07:07 +010075 /* On FVP RevC, initialize SMMUv3 */
Vijayenthiran Subramaniam884cc022023-12-21 17:34:05 +053076 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) {
77 if (smmuv3_security_init(PLAT_FVP_SMMUV3_BASE) != 0) {
78 /*
79 * Don't proceed for smmuv3 initialization if the
80 * security init failed.
81 */
82 return;
83 }
84 /* SMMUv3 initialization failure is not fatal */
85 if (smmuv3_init(PLAT_FVP_SMMUV3_BASE) != 0) {
86 WARN("Failed initializing SMMU.\n");
87 }
88 }
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -060089}
90
91void __init bl31_plat_arch_setup(void)
92{
Manish V Badarkhe86854e72022-03-15 16:05:58 +000093 int rc __unused;
94 uintptr_t hw_config_base_align __unused;
95 size_t mapped_size_align __unused;
96
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -060097 arm_bl31_plat_arch_setup();
98
99 /*
100 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run.
101 * So there is no BL2 to load the HW_CONFIG dtb into memory before
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000102 * control is passed to BL31. The code below relies on dynamic mapping
103 * capability, which is not supported by xlat tables lib V1.
104 * TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support
105 * gets deprecated.
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600106 */
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600107#if !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1
Manish V Badarkhe8717e032020-05-30 17:40:44 +0100108 assert(hw_config_info != NULL);
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000109 assert(hw_config_info->config_addr != 0UL);
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600110
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000111 /* Page aligned address and size if necessary */
112 hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);
113 mapped_size_align = page_align(hw_config_info->config_max_size, UP);
114
115 if ((hw_config_info->config_addr != hw_config_base_align) &&
116 (hw_config_info->config_max_size == mapped_size_align)) {
117 mapped_size_align += PAGE_SIZE;
118 }
119
120 /*
121 * map dynamically HW config region with its aligned base address and
122 * size
123 */
124 rc = mmap_add_dynamic_region((unsigned long long)hw_config_base_align,
125 hw_config_base_align,
126 mapped_size_align,
127 MT_RO_DATA);
128 if (rc != 0) {
129 ERROR("Error while mapping HW_CONFIG device tree (%d).\n", rc);
130 panic();
131 }
132
133 /* Populate HW_CONFIG device tree with the mapped address */
Manish V Badarkhe8717e032020-05-30 17:40:44 +0100134 fconf_populate("HW_CONFIG", hw_config_info->config_addr);
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000135
136 /* unmap the HW_CONFIG memory region */
137 rc = mmap_remove_dynamic_region(hw_config_base_align, mapped_size_align);
138 if (rc != 0) {
139 ERROR("Error while unmapping HW_CONFIG device tree (%d).\n",
140 rc);
141 panic();
142 }
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600143#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144}
laurenw-arm9656a302020-06-10 16:33:18 -0500145
146unsigned int plat_get_syscnt_freq2(void)
147{
148 unsigned int counter_base_frequency;
149
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600150#if !RESET_TO_BL31 && !RESET_TO_BL2
laurenw-arm9656a302020-06-10 16:33:18 -0500151 /* Get the frequency through FCONF API for HW_CONFIG */
152 counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq);
153 if (counter_base_frequency > 0U) {
154 return counter_base_frequency;
155 }
156#endif
157
158 /* Read the frequency from Frequency modes table */
159 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
160
161 /* The first entry of the frequency modes table must not be 0 */
162 if (counter_base_frequency == 0U) {
163 panic();
164 }
165
166 return counter_base_frequency;
167}