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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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29 */
30
Dan Handley2b6b5742015-03-19 19:17:53 +000031#include <plat_arm.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010032#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
Vikram Kanigirida567432014-04-15 18:08:08 +010035void bl31_early_platform_setup(bl31_params_t *from_bl2,
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010036 void *plat_params_from_bl2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010037{
Dan Handley2b6b5742015-03-19 19:17:53 +000038 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000039
Achin Gupta4f6ad662013-10-25 09:08:21 +010040 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010041 fvp_config_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +010042
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010043 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000044 * Initialize the correct interconnect for this cluster during cold
45 * boot. No need for locks as no other CPU is active.
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010046 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000047 fvp_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010048
Dan Handley2b6b5742015-03-19 19:17:53 +000049 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000050 * Enable coherency in interconnect for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010051 * Earlier bootloader stages might already do this (e.g. Trusted
52 * Firmware's BL1 does it) but we can't assume so. There is no harm in
53 * executing this code twice anyway.
Dan Handley2b6b5742015-03-19 19:17:53 +000054 * FVP PSCI code will enable coherency for other clusters.
55 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000056 fvp_interconnect_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +010057}