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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <drivers/arm/smmu_v3.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +00008#include <plat/arm/common/arm_config.h>
9#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <plat/common/platform.h>
11
Dan Handleyed6ff952014-05-14 17:44:19 +010012#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +010014void __init bl31_early_platform_setup2(u_register_t arg0,
15 u_register_t arg1, u_register_t arg2, u_register_t arg3)
Achin Gupta4f6ad662013-10-25 09:08:21 +010016{
Soby Mathew7d5a2e72018-01-10 15:59:31 +000017 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000018
Achin Gupta4f6ad662013-10-25 09:08:21 +010019 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010020 fvp_config_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +010021
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010022 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000023 * Initialize the correct interconnect for this cluster during cold
24 * boot. No need for locks as no other CPU is active.
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010025 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000026 fvp_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010027
Dan Handley2b6b5742015-03-19 19:17:53 +000028 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000029 * Enable coherency in interconnect for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010030 * Earlier bootloader stages might already do this (e.g. Trusted
31 * Firmware's BL1 does it) but we can't assume so. There is no harm in
32 * executing this code twice anyway.
Dan Handley2b6b5742015-03-19 19:17:53 +000033 * FVP PSCI code will enable coherency for other clusters.
34 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000035 fvp_interconnect_enable();
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +010036
37 /* On FVP RevC, intialize SMMUv3 */
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +010038 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +010039 smmuv3_init(PLAT_FVP_SMMUV3_BASE);
Achin Gupta4f6ad662013-10-25 09:08:21 +010040}