blob: 4d2079d23a723802fe4fb3a39c20627aaca8464a [file] [log] [blame]
Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +00002 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Varun Wadekarcc238bb2022-09-13 12:38:47 +01003 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00006 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9#include <stdbool.h>
10#include <string.h>
11
12#include <platform_def.h>
13
Achin Gupta27b895e2014-05-04 18:38:28 +010014#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000015#include <arch_helpers.h>
Soby Mathew830f0ad2019-07-12 09:23:38 +010016#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <bl31/interrupt_mgmt.h>
18#include <common/bl_common.h>
Claus Pedersen785e66c2022-09-12 22:42:58 +000019#include <common/debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010020#include <context.h>
Zelalem Awekef92c0cb2022-01-31 16:59:42 -060021#include <drivers/arm/gicv3.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <lib/el3_runtime/context_mgmt.h>
23#include <lib/el3_runtime/pubsub_events.h>
24#include <lib/extensions/amu.h>
johpow0181865962022-01-28 17:06:20 -060025#include <lib/extensions/brbe.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000026#include <lib/extensions/mpam.h>
johpow019baade32021-07-08 14:14:00 -050027#include <lib/extensions/sme.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028#include <lib/extensions/spe.h>
29#include <lib/extensions/sve.h>
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010030#include <lib/extensions/sys_reg_trace.h>
Manish V Badarkhe20df29c2021-07-02 09:10:56 +010031#include <lib/extensions/trbe.h>
Manish V Badarkhe51a97112021-07-08 09:33:18 +010032#include <lib/extensions/trf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000033#include <lib/utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000034
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010035#if ENABLE_FEAT_TWED
36/* Make sure delay value fits within the range(0-15) */
37CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
38#endif /* ENABLE_FEAT_TWED */
Achin Gupta7aea9082014-02-01 07:51:28 +000039
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010040static void manage_extensions_secure(cpu_context_t *ctx);
Zelalem Aweke20126002022-04-08 16:48:05 -050041
42static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
43{
44 u_register_t sctlr_elx, actlr_elx;
45
46 /*
47 * Initialise SCTLR_EL1 to the reset value corresponding to the target
48 * execution state setting all fields rather than relying on the hw.
49 * Some fields have architecturally UNKNOWN reset values and these are
50 * set to zero.
51 *
52 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
53 *
54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
55 * required by PSCI specification)
56 */
57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
58 if (GET_RW(ep->spsr) == MODE_RW_64) {
59 sctlr_elx |= SCTLR_EL1_RES1;
60 } else {
61 /*
62 * If the target execution state is AArch32 then the following
63 * fields need to be set.
64 *
65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
66 * instructions are not trapped to EL1.
67 *
68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
69 * instructions are not trapped to EL1.
70 *
71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
72 * CP15DMB, CP15DSB, and CP15ISB instructions.
73 */
74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
76 }
77
78#if ERRATA_A75_764081
79 /*
80 * If workaround of errata 764081 for Cortex-A75 is used then set
81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
82 */
83 sctlr_elx |= SCTLR_IESB_BIT;
84#endif
85 /* Store the initialised SCTLR_EL1 value in the cpu_context */
86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
87
88 /*
89 * Base the context ACTLR_EL1 on the current value, as it is
90 * implementation defined. The context restore process will write
91 * the value from the context to the actual register and can cause
92 * problems for processor cores that don't expect certain bits to
93 * be zero.
94 */
95 actlr_elx = read_actlr_el1();
96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
97}
98
Zelalem Aweke42401112022-01-05 17:12:24 -060099/******************************************************************************
100 * This function performs initializations that are specific to SECURE state
101 * and updates the cpu context specified by 'ctx'.
102 *****************************************************************************/
103static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
Achin Gupta7aea9082014-02-01 07:51:28 +0000104{
Zelalem Aweke42401112022-01-05 17:12:24 -0600105 u_register_t scr_el3;
106 el3_state_t *state;
107
108 state = get_el3state_ctx(ctx);
109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
110
111#if defined(IMAGE_BL31) && !defined(SPD_spmd)
Achin Gupta7aea9082014-02-01 07:51:28 +0000112 /*
Zelalem Aweke42401112022-01-05 17:12:24 -0600113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
114 * indicated by the interrupt routing model for BL31.
115 */
116 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
117#endif
118
119#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
120 /* Get Memory Tagging Extension support level */
121 unsigned int mte = get_armv8_5_mte_support();
122#endif
123 /*
124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS
125 * is set, or when MTE is only implemented at EL0.
Achin Gupta7aea9082014-02-01 07:51:28 +0000126 */
Zelalem Aweke42401112022-01-05 17:12:24 -0600127#if CTX_INCLUDE_MTE_REGS
128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
129 scr_el3 |= SCR_ATA_BIT;
130#else
131 if (mte == MTE_IMPLEMENTED_EL0) {
132 scr_el3 |= SCR_ATA_BIT;
133 }
134#endif /* CTX_INCLUDE_MTE_REGS */
135
136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
138 if (GET_RW(ep->spsr) != MODE_RW_64) {
139 ERROR("S-EL2 can not be used in AArch32\n.");
140 panic();
141 }
142
143 scr_el3 |= SCR_EEL2_BIT;
144 }
145
146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
147
Zelalem Aweke20126002022-04-08 16:48:05 -0500148 /*
149 * Initialize EL1 context registers unless SPMC is running
150 * at S-EL2.
151 */
152#if !SPMD_SPM_AT_SEL2
153 setup_el1_context(ctx, ep);
154#endif
155
Zelalem Aweke42401112022-01-05 17:12:24 -0600156 manage_extensions_secure(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000157}
158
Zelalem Aweke42401112022-01-05 17:12:24 -0600159#if ENABLE_RME
160/******************************************************************************
161 * This function performs initializations that are specific to REALM state
162 * and updates the cpu context specified by 'ctx'.
163 *****************************************************************************/
164static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
165{
166 u_register_t scr_el3;
167 el3_state_t *state;
168
169 state = get_el3state_ctx(ctx);
170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
171
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +0000172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
173
174#if ENABLE_FEAT_CSV2_2
175 /* Enable access to the SCXTNUM_ELx registers. */
176 scr_el3 |= SCR_EnSCXT_BIT;
177#endif
Zelalem Aweke42401112022-01-05 17:12:24 -0600178
179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
180}
181#endif /* ENABLE_RME */
182
183/******************************************************************************
184 * This function performs initializations that are specific to NON-SECURE state
185 * and updates the cpu context specified by 'ctx'.
186 *****************************************************************************/
187static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
188{
189 u_register_t scr_el3;
190 el3_state_t *state;
191
192 state = get_el3state_ctx(ctx);
193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
194
195 /* SCR_NS: Set the NS bit */
196 scr_el3 |= SCR_NS_BIT;
197
198#if !CTX_INCLUDE_PAUTH_REGS
199 /*
200 * If the pointer authentication registers aren't saved during world
201 * switches the value of the registers can be leaked from the Secure to
202 * the Non-secure world. To prevent this, rather than enabling pointer
203 * authentication everywhere, we only enable it in the Non-secure world.
204 *
205 * If the Secure world wants to use pointer authentication,
206 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
207 */
208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
209#endif /* !CTX_INCLUDE_PAUTH_REGS */
210
211 /* Allow access to Allocation Tags when MTE is implemented. */
212 scr_el3 |= SCR_ATA_BIT;
213
Manish Pandey0e3379d2022-10-10 11:43:08 +0100214#if HANDLE_EA_EL3_FIRST_NS
215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
216 scr_el3 |= SCR_EA_BIT;
217#endif
218
Manish Pandey7c6fcb42022-09-27 14:30:34 +0100219#if RAS_TRAP_NS_ERR_REC_ACCESS
220 /*
221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
222 * and RAS ERX registers from EL1 and EL2(from any security state)
223 * are trapped to EL3.
224 * Set here to trap only for NS EL1/EL2
225 *
226 */
227 scr_el3 |= SCR_TERR_BIT;
228#endif
229
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +0000230#if ENABLE_FEAT_CSV2_2
231 /* Enable access to the SCXTNUM_ELx registers. */
232 scr_el3 |= SCR_EnSCXT_BIT;
233#endif
234
Zelalem Aweke42401112022-01-05 17:12:24 -0600235#ifdef IMAGE_BL31
236 /*
237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
238 * indicated by the interrupt routing model for BL31.
239 */
240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
241#endif
242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600243
Zelalem Aweke20126002022-04-08 16:48:05 -0500244 /* Initialize EL1 context registers */
245 setup_el1_context(ctx, ep);
246
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600247 /* Initialize EL2 context registers */
248#if CTX_INCLUDE_EL2_REGS
249
250 /*
251 * Initialize SCTLR_EL2 context register using Endianness value
252 * taken from the entrypoint attribute.
253 */
254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
255 sctlr_el2 |= SCTLR_EL2_RES1;
256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2,
257 sctlr_el2);
258
259 /*
Varun Wadekarcc238bb2022-09-13 12:38:47 +0100260 * Program the ICC_SRE_EL2 to make sure the correct bits are set
261 * when restoring NS context.
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600262 */
Varun Wadekarcc238bb2022-09-13 12:38:47 +0100263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2,
266 icc_sre_el2);
Boyan Karatotevecd9f082022-10-26 15:10:39 +0100267
268 /*
269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't
270 * throw anyone off who expects this to be sensible.
271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be
272 * unified with the proper PMU implementation
273 */
274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) &
275 PMCR_EL0_N_MASK);
276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2);
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600277#endif /* CTX_INCLUDE_EL2_REGS */
Zelalem Aweke42401112022-01-05 17:12:24 -0600278}
279
Achin Gupta7aea9082014-02-01 07:51:28 +0000280/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600281 * The following function performs initialization of the cpu_context 'ctx'
282 * for first use that is common to all security states, and sets the
283 * initial entrypoint state as specified by the entry_point_info structure.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100284 *
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000285 * The EE and ST attributes are used to configure the endianness and secure
Soby Mathewb0082d22015-04-09 13:40:55 +0100286 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100287 ******************************************************************************/
Zelalem Aweke42401112022-01-05 17:12:24 -0600288static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100289{
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000290 u_register_t scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100291 el3_state_t *state;
292 gp_regs_t *gp_regs;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100293
Andrew Thoelke4e126072014-06-04 21:10:52 +0100294 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000295 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100296
297 /*
David Cunadofee86532017-04-13 22:38:29 +0100298 * SCR_EL3 was initialised during reset sequence in macro
299 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
300 * affect the next EL.
301 *
302 * The following fields are initially set to zero and then updated to
303 * the required value depending on the state of the SPSR_EL3 and the
304 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100305 */
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000306 scr_el3 = read_scr();
Manish Pandey0e3379d2022-10-10 11:43:08 +0100307 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
Zelalem Aweke42401112022-01-05 17:12:24 -0600308 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT);
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500309
David Cunadofee86532017-04-13 22:38:29 +0100310 /*
311 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
312 * Exception level as specified by SPSR.
313 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500314 if (GET_RW(ep->spsr) == MODE_RW_64) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100315 scr_el3 |= SCR_RW_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500316 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600317
David Cunadofee86532017-04-13 22:38:29 +0100318 /*
319 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
Zelalem Aweke20126002022-04-08 16:48:05 -0500320 * Secure timer registers to EL3, from AArch64 state only, if specified
321 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
322 * bit always behaves as 1 (i.e. secure physical timer register access
323 * is not trapped)
David Cunadofee86532017-04-13 22:38:29 +0100324 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500325 if (EP_GET_ST(ep->h.attr) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100326 scr_el3 |= SCR_ST_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500327 }
Andrew Thoelke4e126072014-06-04 21:10:52 +0100328
johpow01f91e59f2021-08-04 19:38:18 -0500329 /*
330 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
331 * SCR_EL3.HXEn.
332 */
Andre Przywara1d8795e2022-11-15 11:45:19 +0000333 if (is_feat_hcx_supported()) {
334 scr_el3 |= SCR_HXEn_BIT;
335 }
johpow01f91e59f2021-08-04 19:38:18 -0500336
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400337 /*
338 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
339 * registers are trapped to EL3.
340 */
341#if ENABLE_FEAT_RNG_TRAP
342 scr_el3 |= SCR_TRNDR_BIT;
343#endif
344
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000345#if FAULT_INJECTION_SUPPORT
346 /* Enable fault injection from lower ELs */
347 scr_el3 |= SCR_FIEN_BIT;
348#endif
349
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000350 /*
Zelalem Aweke42401112022-01-05 17:12:24 -0600351 * CPTR_EL3 was initialized out of reset, copy that value to the
352 * context register.
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000353 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100354 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
Max Shvetsovc4502772021-03-22 11:59:37 +0000355
Andrew Thoelke4e126072014-06-04 21:10:52 +0100356 /*
David Cunadofee86532017-04-13 22:38:29 +0100357 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
358 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
359 * next mode is Hyp.
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500360 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
361 * same conditions as HVC instructions and when the processor supports
362 * ARMv8.6-FGT.
Jimmy Brisson83573892020-04-16 10:48:02 -0500363 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
364 * CNTPOFF_EL2 register under the same conditions as HVC instructions
365 * and when the processor supports ECV.
David Cunadofee86532017-04-13 22:38:29 +0100366 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000367 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
368 || ((GET_RW(ep->spsr) != MODE_RW_64)
369 && (GET_M32(ep->spsr) == MODE32_hyp))) {
David Cunadofee86532017-04-13 22:38:29 +0100370 scr_el3 |= SCR_HCE_BIT;
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500371
Andre Przywarae8920f62022-11-10 14:28:01 +0000372 if (is_feat_fgt_supported()) {
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500373 scr_el3 |= SCR_FGTEN_BIT;
374 }
Jimmy Brisson83573892020-04-16 10:48:02 -0500375
376 if (get_armv8_6_ecv_support()
377 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
378 scr_el3 |= SCR_ECVEN_BIT;
379 }
David Cunadofee86532017-04-13 22:38:29 +0100380 }
381
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100382#if ENABLE_FEAT_TWED
johpow013e24c162020-04-22 14:05:13 -0500383 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100384 /* Set delay in SCR_EL3 */
385 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
386 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
387 << SCR_TWEDEL_SHIFT);
johpow013e24c162020-04-22 14:05:13 -0500388
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100389 /* Enable WFE delay */
390 scr_el3 |= SCR_TWEDEn_BIT;
391#endif /* ENABLE_FEAT_TWED */
johpow013e24c162020-04-22 14:05:13 -0500392
David Cunadofee86532017-04-13 22:38:29 +0100393 /*
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100394 * Populate EL3 state so that we've the right context
395 * before doing ERET
396 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100397 state = get_el3state_ctx(ctx);
398 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
399 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
400 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
401
402 /*
403 * Store the X0-X7 value from the entrypoint into the context
404 * Use memcpy as we are in control of the layout of the structures
405 */
406 gp_regs = get_gpregs_ctx(ctx);
407 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
408}
409
410/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600411 * Context management library initialization routine. This library is used by
412 * runtime services to share pointers to 'cpu_context' structures for secure
413 * non-secure and realm states. Management of the structures and their associated
414 * memory is not done by the context management library e.g. the PSCI service
415 * manages the cpu context used for entry from and exit to the non-secure state.
416 * The Secure payload dispatcher service manages the context(s) corresponding to
417 * the secure state. It also uses this library to get access to the non-secure
418 * state cpu context pointers.
419 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
420 * which will be used for programming an entry into a lower EL. The same context
421 * will be used to save state upon exception entry from that EL.
422 ******************************************************************************/
423void __init cm_init(void)
424{
425 /*
426 * The context management library has only global data to intialize, but
427 * that will be done when the BSS is zeroed out.
428 */
429}
430
431/*******************************************************************************
432 * This is the high-level function used to initialize the cpu_context 'ctx' for
433 * first use. It performs initializations that are common to all security states
434 * and initializations specific to the security state specified in 'ep'
435 ******************************************************************************/
436void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
437{
438 unsigned int security_state;
439
440 assert(ctx != NULL);
441
442 /*
443 * Perform initializations that are common
444 * to all security states
445 */
446 setup_context_common(ctx, ep);
447
448 security_state = GET_SECURITY_STATE(ep->h.attr);
449
450 /* Perform security state specific initializations */
451 switch (security_state) {
452 case SECURE:
453 setup_secure_context(ctx, ep);
454 break;
455#if ENABLE_RME
456 case REALM:
457 setup_realm_context(ctx, ep);
458 break;
459#endif
460 case NON_SECURE:
461 setup_ns_context(ctx, ep);
462 break;
463 default:
464 ERROR("Invalid security state\n");
465 panic();
466 break;
467 }
468}
469
470/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000471 * Enable architecture extensions on first entry to Non-secure world.
472 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
473 * it is zero.
474 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -0500475static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000476{
477#if IMAGE_BL31
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100478#if ENABLE_SPE_FOR_LOWER_ELS
479 spe_enable(el2_unused);
480#endif
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100481
482#if ENABLE_AMU
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100483 amu_enable(el2_unused, ctx);
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100484#endif
David Cunadoce88eee2017-10-20 11:30:57 +0100485
johpow019baade32021-07-08 14:14:00 -0500486#if ENABLE_SME_FOR_NS
487 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */
488 sme_enable(ctx);
489#elif ENABLE_SVE_FOR_NS
490 /* Enable SVE and FPU/SIMD for non-secure world. */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100491 sve_enable(ctx);
492#endif
493
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100494#if ENABLE_MPAM_FOR_LOWER_ELS
495 mpam_enable(el2_unused);
496#endif
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100497
Andre Przywara191eff62022-11-17 16:42:09 +0000498 if (is_feat_trbe_supported()) {
499 trbe_enable();
500 }
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100501
Andre Przywarac97c5512022-11-17 16:42:09 +0000502 if (is_feat_brbe_supported()) {
503 brbe_enable();
504 }
johpow0181865962022-01-28 17:06:20 -0600505
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100506#if ENABLE_SYS_REG_TRACE_FOR_NS
507 sys_reg_trace_enable(ctx);
508#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
509
Andre Przywara06ea44e2022-11-17 17:30:43 +0000510 if (is_feat_trf_supported()) {
511 trf_enable();
512 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000513#endif
514}
515
516/*******************************************************************************
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100517 * Enable architecture extensions on first entry to Secure world.
518 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -0500519static void manage_extensions_secure(cpu_context_t *ctx)
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100520{
521#if IMAGE_BL31
johpow019baade32021-07-08 14:14:00 -0500522 #if ENABLE_SME_FOR_NS
523 #if ENABLE_SME_FOR_SWD
524 /*
525 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must
526 * ensure SME, SVE, and FPU/SIMD context properly managed.
527 */
528 sme_enable(ctx);
529 #else /* ENABLE_SME_FOR_SWD */
530 /*
531 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can
532 * safely use the associated registers.
533 */
534 sme_disable(ctx);
535 #endif /* ENABLE_SME_FOR_SWD */
536 #elif ENABLE_SVE_FOR_NS
537 #if ENABLE_SVE_FOR_SWD
538 /*
539 * Enable SVE and FPU in secure context, secure manager must ensure that
540 * the SVE and FPU register contexts are properly managed.
541 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100542 sve_enable(ctx);
johpow019baade32021-07-08 14:14:00 -0500543 #else /* ENABLE_SVE_FOR_SWD */
544 /*
545 * Disable SVE and FPU in secure context so non-secure world can safely
546 * use them.
547 */
548 sve_disable(ctx);
549 #endif /* ENABLE_SVE_FOR_SWD */
550 #endif /* ENABLE_SVE_FOR_NS */
551#endif /* IMAGE_BL31 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100552}
553
554/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100555 * The following function initializes the cpu_context for a CPU specified by
556 * its `cpu_idx` for first use, and sets the initial entrypoint state as
557 * specified by the entry_point_info structure.
558 ******************************************************************************/
559void cm_init_context_by_index(unsigned int cpu_idx,
560 const entry_point_info_t *ep)
561{
562 cpu_context_t *ctx;
563 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100564 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100565}
566
567/*******************************************************************************
568 * The following function initializes the cpu_context for the current CPU
569 * for first use, and sets the initial entrypoint state as specified by the
570 * entry_point_info structure.
571 ******************************************************************************/
572void cm_init_my_context(const entry_point_info_t *ep)
573{
574 cpu_context_t *ctx;
575 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100576 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100577}
578
579/*******************************************************************************
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500580 * Prepare the CPU system registers for first entry into realm, secure, or
581 * normal world.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100582 *
583 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
584 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
585 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
586 * For all entries, the EL1 registers are initialized from the cpu_context
587 ******************************************************************************/
588void cm_prepare_el3_exit(uint32_t security_state)
589{
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000590 u_register_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100591 cpu_context_t *ctx = cm_get_context(security_state);
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100592 bool el2_unused = false;
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000593 uint64_t hcr_el2 = 0U;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100594
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000595 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100596
597 if (security_state == NON_SECURE) {
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000598 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000599 CTX_SCR_EL3);
600 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100601 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000602 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000603 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800604 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100605 sctlr_elx |= SCTLR_EL2_RES1;
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000606#if ERRATA_A75_764081
607 /*
608 * If workaround of errata 764081 for Cortex-A75 is used
609 * then set SCTLR_EL2.IESB to enable Implicit Error
610 * Synchronization Barrier.
611 */
612 sctlr_elx |= SCTLR_IESB_BIT;
613#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100614 write_sctlr_el2(sctlr_elx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000615 } else if (el_implemented(2) != EL_IMPL_NONE) {
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100616 el2_unused = true;
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000617
David Cunadofee86532017-04-13 22:38:29 +0100618 /*
619 * EL2 present but unused, need to disable safely.
620 * SCTLR_EL2 can be ignored in this case.
621 *
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100622 * Set EL2 register width appropriately: Set HCR_EL2
623 * field to match SCR_EL3.RW.
David Cunadofee86532017-04-13 22:38:29 +0100624 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000625 if ((scr_el3 & SCR_RW_BIT) != 0U)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100626 hcr_el2 |= HCR_RW_BIT;
627
628 /*
629 * For Armv8.3 pointer authentication feature, disable
630 * traps to EL2 when accessing key registers or using
631 * pointer authentication instructions from lower ELs.
632 */
633 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
634
635 write_hcr_el2(hcr_el2);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100636
David Cunadofee86532017-04-13 22:38:29 +0100637 /*
638 * Initialise CPTR_EL2 setting all fields rather than
639 * relying on the hw. All fields have architecturally
640 * UNKNOWN reset values.
641 *
642 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
643 * accesses to the CPACR_EL1 or CPACR from both
644 * Execution states do not trap to EL2.
645 *
646 * CPTR_EL2.TTA: Set to zero so that Non-secure System
647 * register accesses to the trace registers from both
648 * Execution states do not trap to EL2.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100649 * If PE trace unit System registers are not implemented
650 * then this bit is reserved, and must be set to zero.
David Cunadofee86532017-04-13 22:38:29 +0100651 *
652 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
653 * to SIMD and floating-point functionality from both
654 * Execution states do not trap to EL2.
655 */
656 write_cptr_el2(CPTR_EL2_RESET_VAL &
657 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
658 | CPTR_EL2_TFP_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100659
David Cunadofee86532017-04-13 22:38:29 +0100660 /*
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000661 * Initialise CNTHCTL_EL2. All fields are
David Cunadofee86532017-04-13 22:38:29 +0100662 * architecturally UNKNOWN on reset and are set to zero
663 * except for field(s) listed below.
664 *
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500665 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to
David Cunadofee86532017-04-13 22:38:29 +0100666 * Hyp mode of Non-secure EL0 and EL1 accesses to the
667 * physical timer registers.
668 *
669 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
670 * Hyp mode of Non-secure EL0 and EL1 accesses to the
671 * physical counter registers.
672 */
673 write_cnthctl_el2(CNTHCTL_RESET_VAL |
674 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100675
David Cunadofee86532017-04-13 22:38:29 +0100676 /*
677 * Initialise CNTVOFF_EL2 to zero as it resets to an
678 * architecturally UNKNOWN value.
679 */
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100680 write_cntvoff_el2(0);
681
David Cunadofee86532017-04-13 22:38:29 +0100682 /*
683 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
684 * MPIDR_EL1 respectively.
685 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100686 write_vpidr_el2(read_midr_el1());
687 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000688
689 /*
David Cunadofee86532017-04-13 22:38:29 +0100690 * Initialise VTTBR_EL2. All fields are architecturally
691 * UNKNOWN on reset.
692 *
693 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
694 * 2 address translation is disabled, cache maintenance
695 * operations depend on the VMID.
696 *
697 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
698 * translation is disabled.
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000699 */
David Cunadofee86532017-04-13 22:38:29 +0100700 write_vttbr_el2(VTTBR_RESET_VAL &
701 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
702 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
703
David Cunado5f55e282016-10-31 17:37:34 +0000704 /*
David Cunadofee86532017-04-13 22:38:29 +0100705 * Initialise MDCR_EL2, setting all fields rather than
706 * relying on hw. Some fields are architecturally
707 * UNKNOWN on reset.
708 *
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100709 * MDCR_EL2.HLP: Set to one so that event counter
710 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
711 * occurs on the increment that changes
712 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
713 * implemented. This bit is RES0 in versions of the
714 * architecture earlier than ARMv8.5, setting it to 1
715 * doesn't have any effect on them.
716 *
717 * MDCR_EL2.TTRF: Set to zero so that access to Trace
718 * Filter Control register TRFCR_EL1 at EL1 is not
719 * trapped to EL2. This bit is RES0 in versions of
720 * the architecture earlier than ARMv8.4.
721 *
722 * MDCR_EL2.HPMD: Set to one so that event counting is
723 * prohibited at EL2. This bit is RES0 in versions of
724 * the architecture earlier than ARMv8.1, setting it
725 * to 1 doesn't have any effect on them.
726 *
727 * MDCR_EL2.TPMS: Set to zero so that accesses to
728 * Statistical Profiling control registers from EL1
729 * do not trap to EL2. This bit is RES0 when SPE is
730 * not implemented.
731 *
David Cunadofee86532017-04-13 22:38:29 +0100732 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
733 * EL1 System register accesses to the Debug ROM
734 * registers are not trapped to EL2.
735 *
736 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
737 * System register accesses to the powerdown debug
738 * registers are not trapped to EL2.
739 *
740 * MDCR_EL2.TDA: Set to zero so that System register
741 * accesses to the debug registers do not trap to EL2.
742 *
743 * MDCR_EL2.TDE: Set to zero so that debug exceptions
744 * are not routed to EL2.
745 *
746 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
747 * Monitors.
748 *
749 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
750 * EL1 accesses to all Performance Monitors registers
751 * are not trapped to EL2.
752 *
753 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
754 * and EL1 accesses to the PMCR_EL0 or PMCR are not
755 * trapped to EL2.
756 *
757 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
758 * architecturally-defined reset value.
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100759 *
760 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
761 * owning exception level is NS-EL1 and, tracing is
762 * prohibited at NS-EL2. These bits are RES0 when
763 * FEAT_TRBE is not implemented.
David Cunado5f55e282016-10-31 17:37:34 +0000764 */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100765 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
766 MDCR_EL2_HPMD) |
767 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
768 >> PMCR_EL0_N_SHIFT)) &
769 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
770 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
771 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
772 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100773 MDCR_EL2_TPMCR_BIT |
774 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
dp-armee3457b2017-05-23 09:32:49 +0100775
dp-armee3457b2017-05-23 09:32:49 +0100776 write_mdcr_el2(mdcr_el2);
777
David Cunadoc14b08e2016-11-25 00:21:59 +0000778 /*
David Cunadofee86532017-04-13 22:38:29 +0100779 * Initialise HSTR_EL2. All fields are architecturally
780 * UNKNOWN on reset.
781 *
782 * HSTR_EL2.T<n>: Set all these fields to zero so that
783 * Non-secure EL0 or EL1 accesses to System registers
784 * do not trap to EL2.
David Cunadoc14b08e2016-11-25 00:21:59 +0000785 */
David Cunadofee86532017-04-13 22:38:29 +0100786 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunadoc14b08e2016-11-25 00:21:59 +0000787 /*
David Cunadofee86532017-04-13 22:38:29 +0100788 * Initialise CNTHP_CTL_EL2. All fields are
789 * architecturally UNKNOWN on reset.
790 *
791 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
792 * physical timer and prevent timer interrupts.
David Cunadoc14b08e2016-11-25 00:21:59 +0000793 */
David Cunadofee86532017-04-13 22:38:29 +0100794 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
795 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100796 }
johpow019baade32021-07-08 14:14:00 -0500797 manage_extensions_nonsecure(el2_unused, ctx);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100798 }
799
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100800 cm_el1_sysregs_context_restore(security_state);
801 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100802}
803
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000804#if CTX_INCLUDE_EL2_REGS
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000805
806static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
807{
Andre Przywara8258f142023-02-15 15:56:15 +0000808 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2());
809 if (is_feat_amu_supported()) {
810 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2());
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000811 }
Andre Przywara8258f142023-02-15 15:56:15 +0000812 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2());
813 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2());
814 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2());
815 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2());
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000816}
817
818static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
819{
Andre Przywara8258f142023-02-15 15:56:15 +0000820 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2));
821 if (is_feat_amu_supported()) {
822 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2));
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000823 }
Andre Przywara8258f142023-02-15 15:56:15 +0000824 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2));
825 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2));
826 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2));
827 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000828}
829
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000830/*******************************************************************************
831 * Save EL2 sysreg context
832 ******************************************************************************/
833void cm_el2_sysregs_context_save(uint32_t security_state)
834{
835 u_register_t scr_el3 = read_scr();
836
837 /*
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500838 * Always save the non-secure and realm EL2 context, only save the
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000839 * S-EL2 context if S-EL2 is enabled.
840 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500841 if ((security_state != SECURE) ||
Ruari Phipps4283ed12020-07-28 11:26:29 +0100842 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000843 cpu_context_t *ctx;
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500844 el2_sysregs_t *el2_sysregs_ctx;
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000845
846 ctx = cm_get_context(security_state);
847 assert(ctx != NULL);
848
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500849 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
850
851 el2_sysregs_context_save_common(el2_sysregs_ctx);
852#if ENABLE_SPE_FOR_LOWER_ELS
853 el2_sysregs_context_save_spe(el2_sysregs_ctx);
854#endif
855#if CTX_INCLUDE_MTE_REGS
856 el2_sysregs_context_save_mte(el2_sysregs_ctx);
857#endif
858#if ENABLE_MPAM_FOR_LOWER_ELS
859 el2_sysregs_context_save_mpam(el2_sysregs_ctx);
860#endif
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000861
Andre Przywara8258f142023-02-15 15:56:15 +0000862 if (is_feat_fgt_supported()) {
863 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
864 }
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000865
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500866#if ENABLE_FEAT_ECV
867 el2_sysregs_context_save_ecv(el2_sysregs_ctx);
868#endif
869#if ENABLE_FEAT_VHE
870 el2_sysregs_context_save_vhe(el2_sysregs_ctx);
871#endif
872#if RAS_EXTENSION
873 el2_sysregs_context_save_ras(el2_sysregs_ctx);
874#endif
875#if CTX_INCLUDE_NEVE_REGS
876 el2_sysregs_context_save_nv2(el2_sysregs_ctx);
877#endif
Andre Przywara06ea44e2022-11-17 17:30:43 +0000878 if (is_feat_trf_supported()) {
879 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
880 }
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500881#if ENABLE_FEAT_CSV2_2
882 el2_sysregs_context_save_csv2(el2_sysregs_ctx);
883#endif
Andre Przywara1d8795e2022-11-15 11:45:19 +0000884 if (is_feat_hcx_supported()) {
885 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2());
886 }
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000887 }
888}
889
890/*******************************************************************************
891 * Restore EL2 sysreg context
892 ******************************************************************************/
893void cm_el2_sysregs_context_restore(uint32_t security_state)
894{
895 u_register_t scr_el3 = read_scr();
896
897 /*
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500898 * Always restore the non-secure and realm EL2 context, only restore the
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000899 * S-EL2 context if S-EL2 is enabled.
900 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500901 if ((security_state != SECURE) ||
Ruari Phipps4283ed12020-07-28 11:26:29 +0100902 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000903 cpu_context_t *ctx;
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500904 el2_sysregs_t *el2_sysregs_ctx;
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000905
906 ctx = cm_get_context(security_state);
907 assert(ctx != NULL);
908
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500909 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
910
911 el2_sysregs_context_restore_common(el2_sysregs_ctx);
912#if ENABLE_SPE_FOR_LOWER_ELS
913 el2_sysregs_context_restore_spe(el2_sysregs_ctx);
914#endif
915#if CTX_INCLUDE_MTE_REGS
916 el2_sysregs_context_restore_mte(el2_sysregs_ctx);
917#endif
918#if ENABLE_MPAM_FOR_LOWER_ELS
919 el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
920#endif
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000921
Andre Przywara8258f142023-02-15 15:56:15 +0000922 if (is_feat_fgt_supported()) {
923 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
924 }
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000925
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500926#if ENABLE_FEAT_ECV
927 el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
928#endif
929#if ENABLE_FEAT_VHE
930 el2_sysregs_context_restore_vhe(el2_sysregs_ctx);
931#endif
932#if RAS_EXTENSION
933 el2_sysregs_context_restore_ras(el2_sysregs_ctx);
934#endif
935#if CTX_INCLUDE_NEVE_REGS
936 el2_sysregs_context_restore_nv2(el2_sysregs_ctx);
937#endif
Andre Przywara06ea44e2022-11-17 17:30:43 +0000938 if (is_feat_trf_supported()) {
939 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
940 }
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500941#if ENABLE_FEAT_CSV2_2
942 el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
943#endif
Andre Przywara1d8795e2022-11-15 11:45:19 +0000944 if (is_feat_hcx_supported()) {
945 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2));
946 }
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000947 }
948}
949#endif /* CTX_INCLUDE_EL2_REGS */
950
Andrew Thoelke4e126072014-06-04 21:10:52 +0100951/*******************************************************************************
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600952 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
953 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
954 * updating EL1 and EL2 registers. Otherwise, it calls the generic
955 * cm_prepare_el3_exit function.
956 ******************************************************************************/
957void cm_prepare_el3_exit_ns(void)
958{
959#if CTX_INCLUDE_EL2_REGS
960 cpu_context_t *ctx = cm_get_context(NON_SECURE);
961 assert(ctx != NULL);
962
Zelalem Aweke20126002022-04-08 16:48:05 -0500963 /* Assert that EL2 is used. */
964#if ENABLE_ASSERTIONS
965 el3_state_t *state = get_el3state_ctx(ctx);
966 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
967#endif
968 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
969 (el_implemented(2U) != EL_IMPL_NONE));
970
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600971 /*
972 * Currently some extensions are configured using
973 * direct register updates. Therefore, do this here
974 * instead of when setting up context.
975 */
976 manage_extensions_nonsecure(0, ctx);
977
978 /*
979 * Set the NS bit to be able to access the ICC_SRE_EL2
980 * register when restoring context.
981 */
982 write_scr_el3(read_scr_el3() | SCR_NS_BIT);
983
Olivier Depreze4793dd2022-05-09 17:34:02 +0200984 /*
985 * Ensure the NS bit change is committed before the EL2/EL1
986 * state restoration.
987 */
988 isb();
989
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600990 /* Restore EL2 and EL1 sysreg contexts */
991 cm_el2_sysregs_context_restore(NON_SECURE);
992 cm_el1_sysregs_context_restore(NON_SECURE);
993 cm_set_next_eret_context(NON_SECURE);
994#else
995 cm_prepare_el3_exit(NON_SECURE);
996#endif /* CTX_INCLUDE_EL2_REGS */
997}
998
999/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +01001000 * The next four functions are used by runtime services to save and restore
1001 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +00001002 * state.
1003 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +00001004void cm_el1_sysregs_context_save(uint32_t security_state)
1005{
Dan Handleye2712bc2014-04-10 15:37:22 +01001006 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +00001007
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001008 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001009 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001010
Max Shvetsovc9e2c922020-02-17 16:15:47 +00001011 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001012
1013#if IMAGE_BL31
1014 if (security_state == SECURE)
1015 PUBLISH_EVENT(cm_exited_secure_world);
1016 else
1017 PUBLISH_EVENT(cm_exited_normal_world);
1018#endif
Achin Gupta7aea9082014-02-01 07:51:28 +00001019}
1020
1021void cm_el1_sysregs_context_restore(uint32_t security_state)
1022{
Dan Handleye2712bc2014-04-10 15:37:22 +01001023 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +00001024
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001025 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001026 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001027
Max Shvetsovc9e2c922020-02-17 16:15:47 +00001028 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001029
1030#if IMAGE_BL31
1031 if (security_state == SECURE)
1032 PUBLISH_EVENT(cm_entering_secure_world);
1033 else
1034 PUBLISH_EVENT(cm_entering_normal_world);
1035#endif
Achin Gupta7aea9082014-02-01 07:51:28 +00001036}
1037
1038/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +01001039 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
1040 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001041 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +01001042void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001043{
Dan Handleye2712bc2014-04-10 15:37:22 +01001044 cpu_context_t *ctx;
1045 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001046
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001047 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001048 assert(ctx != NULL);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001049
Andrew Thoelke4e126072014-06-04 21:10:52 +01001050 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001051 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001052 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001053}
1054
1055/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +01001056 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
1057 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +00001058 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +01001059void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +01001060 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +00001061{
Dan Handleye2712bc2014-04-10 15:37:22 +01001062 cpu_context_t *ctx;
1063 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +00001064
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001065 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001066 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +00001067
1068 /* Populate EL3 state so that ERET jumps to the correct entry */
1069 state = get_el3state_ctx(ctx);
1070 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +01001071 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +00001072}
1073
1074/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +01001075 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
1076 * pertaining to the given security state using the value and bit position
1077 * specified in the parameters. It preserves all other bits.
1078 ******************************************************************************/
1079void cm_write_scr_el3_bit(uint32_t security_state,
1080 uint32_t bit_pos,
1081 uint32_t value)
1082{
1083 cpu_context_t *ctx;
1084 el3_state_t *state;
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001085 u_register_t scr_el3;
Achin Gupta27b895e2014-05-04 18:38:28 +01001086
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001087 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001088 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +01001089
1090 /* Ensure that the bit position is a valid one */
Jimmy Brissoned202072020-08-04 16:18:52 -05001091 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Gupta27b895e2014-05-04 18:38:28 +01001092
1093 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001094 assert(value <= 1U);
Achin Gupta27b895e2014-05-04 18:38:28 +01001095
1096 /*
1097 * Get the SCR_EL3 value from the cpu context, clear the desired bit
1098 * and set it to its new value.
1099 */
1100 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001101 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
Jimmy Brissoned202072020-08-04 16:18:52 -05001102 scr_el3 &= ~(1UL << bit_pos);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001103 scr_el3 |= (u_register_t)value << bit_pos;
Achin Gupta27b895e2014-05-04 18:38:28 +01001104 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
1105}
1106
1107/*******************************************************************************
1108 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
1109 * given security state.
1110 ******************************************************************************/
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001111u_register_t cm_get_scr_el3(uint32_t security_state)
Achin Gupta27b895e2014-05-04 18:38:28 +01001112{
1113 cpu_context_t *ctx;
1114 el3_state_t *state;
1115
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001116 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001117 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +01001118
1119 /* Populate EL3 state so that ERET jumps to the correct entry */
1120 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001121 return read_ctx_reg(state, CTX_SCR_EL3);
Achin Gupta27b895e2014-05-04 18:38:28 +01001122}
1123
1124/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001125 * This function is used to program the context that's used for exception
1126 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
1127 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +00001128 ******************************************************************************/
1129void cm_set_next_eret_context(uint32_t security_state)
1130{
Dan Handleye2712bc2014-04-10 15:37:22 +01001131 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001132
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001133 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001134 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001135
Andrew Thoelke4e126072014-06-04 21:10:52 +01001136 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +00001137}