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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00002 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Varun Wadekar423045d2022-05-25 12:45:22 +01003 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
Florian Lugoud4e25032021-09-08 12:40:24 +020082#define ICC_ASGI1R S3_0_C12_C11_6
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000083#define ICC_SRE_EL1 S3_0_C12_C12_5
84#define ICC_SRE_EL2 S3_4_C12_C9_5
85#define ICC_SRE_EL3 S3_6_C12_C12_5
86#define ICC_CTLR_EL1 S3_0_C12_C12_4
87#define ICC_CTLR_EL3 S3_6_C12_C12_4
88#define ICC_PMR_EL1 S3_0_C4_C6_0
89#define ICC_RPR_EL1 S3_0_C12_C11_3
90#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
91#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
92#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
93#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
94#define ICC_IAR0_EL1 S3_0_c12_c8_0
95#define ICC_IAR1_EL1 S3_0_c12_c12_0
96#define ICC_EOIR0_EL1 S3_0_c12_c8_1
97#define ICC_EOIR1_EL1 S3_0_c12_c12_1
98#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010099
100/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000101 * Definitions for EL2 system registers for save/restore routine
102 ******************************************************************************/
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Varun Wadekar423045d2022-05-25 12:45:22 +0100112#define MPAMVPM0_EL2 S3_4_C10_C6_0
113#define MPAMVPM1_EL2 S3_4_C10_C6_1
114#define MPAMVPM2_EL2 S3_4_C10_C6_2
115#define MPAMVPM3_EL2 S3_4_C10_C6_3
116#define MPAMVPM4_EL2 S3_4_C10_C6_4
117#define MPAMVPM5_EL2 S3_4_C10_C6_5
118#define MPAMVPM6_EL2 S3_4_C10_C6_6
119#define MPAMVPM7_EL2 S3_4_C10_C6_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
Andre Przywaraedc449d2023-01-27 14:09:20 +0000122#define VNCR_EL2 S3_4_C2_C2_0
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000123#define PMSCR_EL2 S3_4_C9_C9_0
124#define TFSR_EL2 S3_4_C5_C6_0
Andre Przywara98908b32022-11-17 16:42:09 +0000125#define CONTEXTIDR_EL2 S3_4_C13_C0_1
126#define TTBR1_EL2 S3_4_C2_C0_1
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000127
128/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000129 * Generic timer memory mapped registers & offsets
130 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700131#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200132#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700133#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000134
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700135#define CNTCR_EN (U(1) << 0)
136#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100137#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000138
139/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140 * System register bit definitions
141 ******************************************************************************/
142/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define LOUIS_SHIFT U(21)
144#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100145#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
148/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100151/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700152#define DCISW U(0x0)
153#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000154#if ERRATA_A53_827319
155#define DCCSW DCCISW
156#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700157#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000158#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159
Andre Przywara0dda4242023-04-18 16:58:36 +0100160#define ID_REG_FIELD_MASK ULL(0xf)
161
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162/* ID_AA64PFR0_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000163#define ID_AA64PFR0_EL0_SHIFT U(0)
164#define ID_AA64PFR0_EL1_SHIFT U(4)
165#define ID_AA64PFR0_EL2_SHIFT U(8)
166#define ID_AA64PFR0_EL3_SHIFT U(12)
167
168#define ID_AA64PFR0_AMU_SHIFT U(44)
169#define ID_AA64PFR0_AMU_MASK ULL(0xf)
170#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
171#define ID_AA64PFR0_AMU_V1 ULL(0x1)
172#define ID_AA64PFR0_AMU_V1P1 U(0x2)
173
174#define ID_AA64PFR0_ELX_MASK ULL(0xf)
175
176#define ID_AA64PFR0_GIC_SHIFT U(24)
177#define ID_AA64PFR0_GIC_WIDTH U(4)
178#define ID_AA64PFR0_GIC_MASK ULL(0xf)
179
180#define ID_AA64PFR0_SVE_SHIFT U(32)
181#define ID_AA64PFR0_SVE_MASK ULL(0xf)
182#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
183#define ID_AA64PFR0_SVE_LENGTH U(4)
184
185#define ID_AA64PFR0_SEL2_SHIFT U(36)
186#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
187
188#define ID_AA64PFR0_MPAM_SHIFT U(40)
189#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
190
191#define ID_AA64PFR0_DIT_SHIFT U(48)
192#define ID_AA64PFR0_DIT_MASK ULL(0xf)
193#define ID_AA64PFR0_DIT_LENGTH U(4)
194#define ID_AA64PFR0_DIT_SUPPORTED U(1)
195
196#define ID_AA64PFR0_CSV2_SHIFT U(56)
197#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
198#define ID_AA64PFR0_CSV2_LENGTH U(4)
199#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
200
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500201#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
202#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
203#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
204#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
205#define ID_AA64PFR0_FEAT_RME_V1 U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000207#define ID_AA64PFR0_RAS_SHIFT U(28)
208#define ID_AA64PFR0_RAS_MASK ULL(0xf)
209#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
210#define ID_AA64PFR0_RAS_LENGTH U(4)
211
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100212/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100213#define EL_IMPL_NONE ULL(0)
214#define EL_IMPL_A64ONLY ULL(1)
215#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000216
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100217/* ID_AA64DFR0_EL1.TraceVer definitions */
218#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
219#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
220#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
221#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100222#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
223#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
224#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
225#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000226#define ID_AA64DFR0_PMUVER_LENGTH U(4)
227#define ID_AA64DFR0_PMUVER_SHIFT U(8)
228#define ID_AA64DFR0_PMUVER_MASK U(0xf)
229#define ID_AA64DFR0_PMUVER_PMUV3 U(1)
230#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
231#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100232
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100233/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000234#define ID_AA64DFR0_PMS_SHIFT U(32)
235#define ID_AA64DFR0_PMS_MASK ULL(0xf)
236#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
237#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
Achin Gupta92712a52015-09-03 14:18:02 +0100238
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100239/* ID_AA64DFR0_EL1.TraceBuffer definitions */
240#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
241#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
242#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
243
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000244/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
245#define ID_AA64DFR0_MTPMU_SHIFT U(48)
246#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
247#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000248#define ID_AA64DFR0_MTPMU_DISABLED ULL(15)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000249
johpow0181865962022-01-28 17:06:20 -0600250/* ID_AA64DFR0_EL1.BRBE definitions */
251#define ID_AA64DFR0_BRBE_SHIFT U(52)
252#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
253#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
254
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000255/* ID_AA64ISAR0_EL1 definitions */
johpow019baade32021-07-08 14:14:00 -0500256#define ID_AA64ISAR0_RNDR_SHIFT U(60)
257#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000258
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000259/* ID_AA64ISAR1_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000260#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
261
262#define ID_AA64ISAR1_GPI_SHIFT U(28)
263#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
264#define ID_AA64ISAR1_GPA_SHIFT U(24)
265#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
266
267#define ID_AA64ISAR1_API_SHIFT U(8)
268#define ID_AA64ISAR1_API_MASK ULL(0xf)
269#define ID_AA64ISAR1_APA_SHIFT U(4)
270#define ID_AA64ISAR1_APA_MASK ULL(0xf)
271
272#define ID_AA64ISAR1_SB_SHIFT U(36)
273#define ID_AA64ISAR1_SB_MASK ULL(0xf)
274#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
275#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000276
Juan Pablo Condee089a172022-06-29 17:44:43 -0400277/* ID_AA64ISAR2_EL1 definitions */
278#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
279
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000280/* ID_AA64PFR2_EL1 definitions */
281#define ID_AA64PFR2_EL1 S3_0_C0_C4_2
282
Juan Pablo Condee089a172022-06-29 17:44:43 -0400283#define ID_AA64ISAR2_GPA3_SHIFT U(8)
284#define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
285
286#define ID_AA64ISAR2_APA3_SHIFT U(12)
287#define ID_AA64ISAR2_APA3_MASK ULL(0xf)
288
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000289/* ID_AA64MMFR0_EL1 definitions */
290#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
291#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
292
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700293#define PARANGE_0000 U(32)
294#define PARANGE_0001 U(36)
295#define PARANGE_0010 U(40)
296#define PARANGE_0011 U(42)
297#define PARANGE_0100 U(44)
298#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000299#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000300
Jimmy Brisson83573892020-04-16 10:48:02 -0500301#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
302#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
303#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
304#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
305#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
306
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500307#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
308#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
309#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
310#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
311
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100312#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100313#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
314#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100315#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100316#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100317
318#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100319#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
320#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
321#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100322
323#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100324#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
325#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
326#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100327#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100328
johpow013e24c162020-04-22 14:05:13 -0500329/* ID_AA64MMFR1_EL1 definitions */
330#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
331#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
332#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
333#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
334
Alexei Fedorovc082f032020-11-25 14:07:05 +0000335#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
336#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
337#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
338#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
339#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
340#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
341
Daniel Boulby44b43332020-11-25 16:36:46 +0000342#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
343#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
344
johpow019baade32021-07-08 14:14:00 -0500345#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
346#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
347#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
348#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -0500349
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000350/* ID_AA64MMFR2_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000351#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000352
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000353#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
354#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
Sathees Balya74155972019-01-25 11:36:01 +0000355
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000356#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
357#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
358#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
359
360#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
361#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
johpow0174b7e442021-12-01 13:18:30 -0600362
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000363#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
364#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
365#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
366#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
367#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000368
Mark Brownc37eee72023-03-14 20:13:03 +0000369/* ID_AA64MMFR3_EL1 definitions */
370#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
371
Mark Brown293a6612023-03-14 20:48:43 +0000372#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20)
373#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf)
374
375#define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16)
376#define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf)
377
378#define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12)
379#define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf)
380
381#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8)
382#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf)
383
Mark Brownc37eee72023-03-14 20:13:03 +0000384#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
385#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
386
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000387/* ID_AA64PFR1_EL1 definitions */
Mark Brown326f2952023-03-14 21:33:04 +0000388#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
389#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
390
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000391#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
392#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
393
394#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
395
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100396#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
397#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
398
399#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
400
Soby Mathew830f0ad2019-07-12 09:23:38 +0100401#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
402#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
403
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400404#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
405#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
406
407#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
408#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
409
Maksims Svecovsdf4ad842023-03-24 13:05:09 +0000410/* ID_AA64PFR2_EL1 definitions */
411#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
412#define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf)
413
414#define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4)
415#define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf)
416
417#define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8)
418#define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf)
419
Andre Przywara870627e2023-01-27 12:25:49 +0000420#define VDISR_EL2 S3_4_C12_C1_1
421#define VSESR_EL2 S3_4_C5_C2_3
422
Alexei Fedorovaf54f6e2020-12-01 13:22:25 +0000423/* Memory Tagging Extension is not implemented */
424#define MTE_UNIMPLEMENTED U(0)
425/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
426#define MTE_IMPLEMENTED_EL0 U(1)
427/* FEAT_MTE2: Full MTE is implemented */
428#define MTE_IMPLEMENTED_ELX U(2)
429/*
430 * FEAT_MTE3: MTE is implemented with support for
431 * asymmetric Tag Check Fault handling
432 */
433#define MTE_IMPLEMENTED_ASY U(3)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100434
Alexei Fedorov19933552020-05-26 13:16:41 +0100435#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
436#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
437
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000438#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
439#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
Juan Pablo Condeefdfe362023-08-14 16:20:52 -0500440#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000441#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
442#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000443#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
johpow019baade32021-07-08 14:14:00 -0500444
Achin Gupta4f6ad662013-10-25 09:08:21 +0100445/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700446#define ID_PFR1_VIRTEXT_SHIFT U(12)
447#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100448#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100449 & ID_PFR1_VIRTEXT_MASK)
450
451/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100452#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700453 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
454 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100455
John Powella5c66362020-03-20 14:21:05 -0500456#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
457 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Alexei Fedorovc082f032020-11-25 14:07:05 +0000458
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200459#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700460 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
461 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200462
David Cunadofee86532017-04-13 22:38:29 +0100463#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
464 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
465 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
466
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000467#define SCTLR_M_BIT (ULL(1) << 0)
468#define SCTLR_A_BIT (ULL(1) << 1)
469#define SCTLR_C_BIT (ULL(1) << 2)
470#define SCTLR_SA_BIT (ULL(1) << 3)
471#define SCTLR_SA0_BIT (ULL(1) << 4)
472#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000473#define SCTLR_nAA_BIT (ULL(1) << 6)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000474#define SCTLR_ITD_BIT (ULL(1) << 7)
475#define SCTLR_SED_BIT (ULL(1) << 8)
476#define SCTLR_UMA_BIT (ULL(1) << 9)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000477#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
478#define SCTLR_EOS_BIT (ULL(1) << 11)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000479#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100480#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000481#define SCTLR_DZE_BIT (ULL(1) << 14)
482#define SCTLR_UCT_BIT (ULL(1) << 15)
483#define SCTLR_NTWI_BIT (ULL(1) << 16)
484#define SCTLR_NTWE_BIT (ULL(1) << 18)
485#define SCTLR_WXN_BIT (ULL(1) << 19)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000486#define SCTLR_TSCXT_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000487#define SCTLR_IESB_BIT (ULL(1) << 21)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000488#define SCTLR_EIS_BIT (ULL(1) << 22)
489#define SCTLR_SPAN_BIT (ULL(1) << 23)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000490#define SCTLR_E0E_BIT (ULL(1) << 24)
491#define SCTLR_EE_BIT (ULL(1) << 25)
492#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100493#define SCTLR_EnDA_BIT (ULL(1) << 27)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000494#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
495#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100496#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000497#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100498#define SCTLR_BT0_BIT (ULL(1) << 35)
499#define SCTLR_BT1_BIT (ULL(1) << 36)
500#define SCTLR_BT_BIT (ULL(1) << 36)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000501#define SCTLR_ITFSB_BIT (ULL(1) << 37)
502#define SCTLR_TCF0_SHIFT U(38)
503#define SCTLR_TCF0_MASK ULL(3)
johpow019baade32021-07-08 14:14:00 -0500504#define SCTLR_ENTP2_BIT (ULL(1) << 60)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000505
506/* Tag Check Faults in EL0 have no effect on the PE */
507#define SCTLR_TCF0_NO_EFFECT U(0)
508/* Tag Check Faults in EL0 cause a synchronous exception */
509#define SCTLR_TCF0_SYNC U(1)
510/* Tag Check Faults in EL0 are asynchronously accumulated */
511#define SCTLR_TCF0_ASYNC U(2)
512/*
513 * Tag Check Faults in EL0 cause a synchronous exception on reads,
514 * and are asynchronously accumulated on writes
515 */
516#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
517
518#define SCTLR_TCF_SHIFT U(40)
519#define SCTLR_TCF_MASK ULL(3)
520
521/* Tag Check Faults in EL1 have no effect on the PE */
522#define SCTLR_TCF_NO_EFFECT U(0)
523/* Tag Check Faults in EL1 cause a synchronous exception */
524#define SCTLR_TCF_SYNC U(1)
525/* Tag Check Faults in EL1 are asynchronously accumulated */
526#define SCTLR_TCF_ASYNC U(2)
527/*
528 * Tag Check Faults in EL1 cause a synchronous exception on reads,
529 * and are asynchronously accumulated on writes
530 */
531#define SCTLR_TCF_SYNCR_ASYNCW U(3)
532
533#define SCTLR_ATA0_BIT (ULL(1) << 42)
534#define SCTLR_ATA_BIT (ULL(1) << 43)
Daniel Boulby44b43332020-11-25 16:36:46 +0000535#define SCTLR_DSSBS_SHIFT U(44)
536#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000537#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
538#define SCTLR_TWEDEL_SHIFT U(46)
539#define SCTLR_TWEDEL_MASK ULL(0xf)
540#define SCTLR_EnASR_BIT (ULL(1) << 54)
541#define SCTLR_EnAS0_BIT (ULL(1) << 55)
542#define SCTLR_EnALS_BIT (ULL(1) << 56)
543#define SCTLR_EPAN_BIT (ULL(1) << 57)
David Cunadofee86532017-04-13 22:38:29 +0100544#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100545
Alexei Fedorovc082f032020-11-25 14:07:05 +0000546/* CPACR_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700547#define CPACR_EL1_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500548#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
549#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
550#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000551#define CPACR_EL1_SMEN_SHIFT U(24)
552#define CPACR_EL1_SMEN_MASK ULL(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100553
554/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700555#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500556#define SCR_NSE_SHIFT U(62)
557#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
558#define SCR_GPF_BIT (UL(1) << 48)
johpow013e24c162020-04-22 14:05:13 -0500559#define SCR_TWEDEL_SHIFT U(30)
560#define SCR_TWEDEL_MASK ULL(0xf)
Mark Brown293a6612023-03-14 20:48:43 +0000561#define SCR_PIEN_BIT (UL(1) << 45)
Mark Brownc37eee72023-03-14 20:13:03 +0000562#define SCR_TCR2EN_BIT (UL(1) << 43)
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400563#define SCR_TRNDR_BIT (UL(1) << 40)
Mark Brown326f2952023-03-14 21:33:04 +0000564#define SCR_GCSEn_BIT (UL(1) << 39)
johpow019baade32021-07-08 14:14:00 -0500565#define SCR_HXEn_BIT (UL(1) << 38)
566#define SCR_ENTP2_SHIFT U(41)
567#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT)
John Powellcc799272022-03-29 00:25:59 -0500568#define SCR_AMVOFFEN_SHIFT U(35)
569#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT)
johpow013e24c162020-04-22 14:05:13 -0500570#define SCR_TWEDEn_BIT (UL(1) << 29)
johpow01fa59c6f2020-10-02 13:41:11 -0500571#define SCR_ECVEN_BIT (UL(1) << 28)
572#define SCR_FGTEN_BIT (UL(1) << 27)
Jimmy Brissoned202072020-08-04 16:18:52 -0500573#define SCR_ATA_BIT (UL(1) << 26)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500574#define SCR_EnSCXT_BIT (UL(1) << 25)
Jimmy Brissoned202072020-08-04 16:18:52 -0500575#define SCR_FIEN_BIT (UL(1) << 21)
576#define SCR_EEL2_BIT (UL(1) << 18)
577#define SCR_API_BIT (UL(1) << 17)
578#define SCR_APK_BIT (UL(1) << 16)
579#define SCR_TERR_BIT (UL(1) << 15)
580#define SCR_TWE_BIT (UL(1) << 13)
581#define SCR_TWI_BIT (UL(1) << 12)
582#define SCR_ST_BIT (UL(1) << 11)
583#define SCR_RW_BIT (UL(1) << 10)
584#define SCR_SIF_BIT (UL(1) << 9)
585#define SCR_HCE_BIT (UL(1) << 8)
586#define SCR_SMD_BIT (UL(1) << 7)
587#define SCR_EA_BIT (UL(1) << 3)
588#define SCR_FIQ_BIT (UL(1) << 2)
589#define SCR_IRQ_BIT (UL(1) << 1)
590#define SCR_NS_BIT (UL(1) << 0)
johpow019baade32021-07-08 14:14:00 -0500591#define SCR_VALID_BIT_MASK U(0x24000002F8F)
David Cunadofee86532017-04-13 22:38:29 +0100592#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100593
David Cunadofee86532017-04-13 22:38:29 +0100594/* MDCR_EL3 definitions */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100595#define MDCR_EnPMSN_BIT (ULL(1) << 36)
596#define MDCR_MPMX_BIT (ULL(1) << 35)
597#define MDCR_MCCD_BIT (ULL(1) << 34)
johpow0181865962022-01-28 17:06:20 -0600598#define MDCR_SBRBE_SHIFT U(32)
599#define MDCR_SBRBE_MASK ULL(0x3)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100600#define MDCR_NSTB(x) ((x) << 24)
601#define MDCR_NSTB_EL1 ULL(0x3)
Boyan Karatotev919d3c82023-02-13 16:32:47 +0000602#define MDCR_NSTBE_BIT (ULL(1) << 26)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000603#define MDCR_MTPME_BIT (ULL(1) << 28)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100604#define MDCR_TDCC_BIT (ULL(1) << 27)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100605#define MDCR_SCCD_BIT (ULL(1) << 23)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100606#define MDCR_EPMAD_BIT (ULL(1) << 21)
607#define MDCR_EDAD_BIT (ULL(1) << 20)
608#define MDCR_TTRF_BIT (ULL(1) << 19)
609#define MDCR_STE_BIT (ULL(1) << 18)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100610#define MDCR_SPME_BIT (ULL(1) << 17)
611#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000612#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000613#define MDCR_SPD32_LEGACY ULL(0x0)
614#define MDCR_SPD32_DISABLE ULL(0x2)
615#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100616#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000617#define MDCR_NSPB_EL1 ULL(0x3)
Boyan Karatotev6e2fd8b2023-02-13 16:38:37 +0000618#define MDCR_NSPBE_BIT (ULL(1) << 11)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000619#define MDCR_TDOSA_BIT (ULL(1) << 10)
620#define MDCR_TDA_BIT (ULL(1) << 9)
621#define MDCR_TPM_BIT (ULL(1) << 6)
Boyan Karatotevb7e74432023-06-15 14:46:20 +0100622#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT
dp-arm595d0d52017-02-08 11:51:50 +0000623
David Cunadofee86532017-04-13 22:38:29 +0100624/* MDCR_EL2 definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000625#define MDCR_EL2_MTPME (U(1) << 28)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000626#define MDCR_EL2_HLP_BIT (U(1) << 26)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100627#define MDCR_EL2_E2TB(x) ((x) << 24)
628#define MDCR_EL2_E2TB_EL1 U(0x3)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000629#define MDCR_EL2_HCCD_BIT (U(1) << 23)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100630#define MDCR_EL2_TTRF (U(1) << 19)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000631#define MDCR_EL2_HPMD_BIT (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100632#define MDCR_EL2_TPMS (U(1) << 14)
633#define MDCR_EL2_E2PB(x) ((x) << 12)
634#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100635#define MDCR_EL2_TDRA_BIT (U(1) << 11)
636#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
637#define MDCR_EL2_TDA_BIT (U(1) << 9)
638#define MDCR_EL2_TDE_BIT (U(1) << 8)
639#define MDCR_EL2_HPME_BIT (U(1) << 7)
640#define MDCR_EL2_TPM_BIT (U(1) << 6)
641#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000642#define MDCR_EL2_HPMN_MASK U(0x1f)
David Cunadofee86532017-04-13 22:38:29 +0100643#define MDCR_EL2_RESET_VAL U(0x0)
644
645/* HSTR_EL2 definitions */
646#define HSTR_EL2_RESET_VAL U(0x0)
647#define HSTR_EL2_T_MASK U(0xff)
648
649/* CNTHP_CTL_EL2 definitions */
650#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
651#define CNTHP_CTL_RESET_VAL U(0x0)
652
653/* VTTBR_EL2 definitions */
654#define VTTBR_RESET_VAL ULL(0x0)
655#define VTTBR_VMID_MASK ULL(0xff)
656#define VTTBR_VMID_SHIFT U(48)
657#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
658#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000659
Achin Gupta4f6ad662013-10-25 09:08:21 +0100660/* HCR definitions */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600661#define HCR_RESET_VAL ULL(0x0)
Chris Kaya5fde282021-05-26 11:58:23 +0100662#define HCR_AMVOFFEN_SHIFT U(51)
663#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600664#define HCR_TEA_BIT (ULL(1) << 47)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100665#define HCR_API_BIT (ULL(1) << 41)
666#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100667#define HCR_E2H_BIT (ULL(1) << 34)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600668#define HCR_HCD_BIT (ULL(1) << 29)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000669#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700670#define HCR_RW_SHIFT U(31)
671#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600672#define HCR_TWE_BIT (ULL(1) << 14)
673#define HCR_TWI_BIT (ULL(1) << 13)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100674#define HCR_AMO_BIT (ULL(1) << 5)
675#define HCR_IMO_BIT (ULL(1) << 4)
676#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100677
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100678/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700679#define ISR_A_SHIFT U(8)
680#define ISR_I_SHIFT U(7)
681#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100682
Achin Gupta4f6ad662013-10-25 09:08:21 +0100683/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100684#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700685#define EVNTEN_BIT (U(1) << 2)
686#define EL1PCEN_BIT (U(1) << 1)
687#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100688
689/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700690#define EL0PTEN_BIT (U(1) << 9)
691#define EL0VTEN_BIT (U(1) << 8)
692#define EL0PCTEN_BIT (U(1) << 0)
693#define EL0VCTEN_BIT (U(1) << 1)
694#define EVNTEN_BIT (U(1) << 2)
695#define EVNTDIR_BIT (U(1) << 3)
696#define EVNTI_SHIFT U(4)
697#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100698
699/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700700#define TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100701#define TAM_SHIFT U(30)
702#define TAM_BIT (U(1) << TAM_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700703#define TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500704#define ESM_BIT (U(1) << 12)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700705#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100706#define CPTR_EZ_BIT (U(1) << 8)
johpow019baade32021-07-08 14:14:00 -0500707#define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \
708 ~(CPTR_EZ_BIT | ESM_BIT))
David Cunadofee86532017-04-13 22:38:29 +0100709
710/* CPTR_EL2 definitions */
711#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
712#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100713#define CPTR_EL2_TAM_SHIFT U(30)
714#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
johpow019baade32021-07-08 14:14:00 -0500715#define CPTR_EL2_SMEN_MASK ULL(0x3)
716#define CPTR_EL2_SMEN_SHIFT U(24)
David Cunadofee86532017-04-13 22:38:29 +0100717#define CPTR_EL2_TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500718#define CPTR_EL2_TSM_BIT (U(1) << 12)
David Cunadofee86532017-04-13 22:38:29 +0100719#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100720#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100721#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100722
Manish Pandey5693afe2021-10-06 17:28:09 +0100723/* VTCR_EL2 definitions */
johpow019baade32021-07-08 14:14:00 -0500724#define VTCR_RESET_VAL U(0x0)
725#define VTCR_EL2_MSA (U(1) << 31)
Manish Pandey5693afe2021-10-06 17:28:09 +0100726
Achin Gupta4f6ad662013-10-25 09:08:21 +0100727/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700728#define DAIF_FIQ_BIT (U(1) << 0)
729#define DAIF_IRQ_BIT (U(1) << 1)
730#define DAIF_ABT_BIT (U(1) << 2)
731#define DAIF_DBG_BIT (U(1) << 3)
732#define SPSR_DAIF_SHIFT U(6)
733#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100734
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700735#define SPSR_AIF_SHIFT U(6)
736#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100737
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700738#define SPSR_E_SHIFT U(9)
739#define SPSR_E_MASK U(0x1)
740#define SPSR_E_LITTLE U(0x0)
741#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100742
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700743#define SPSR_T_SHIFT U(5)
744#define SPSR_T_MASK U(0x1)
745#define SPSR_T_ARM U(0x0)
746#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100747
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000748#define SPSR_M_SHIFT U(4)
749#define SPSR_M_MASK U(0x1)
750#define SPSR_M_AARCH64 U(0x0)
751#define SPSR_M_AARCH32 U(0x1)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500752#define SPSR_M_EL2H U(0x9)
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000753
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000754#define SPSR_EL_SHIFT U(2)
755#define SPSR_EL_WIDTH U(2)
756
Daniel Boulby44b43332020-11-25 16:36:46 +0000757#define SPSR_SSBS_SHIFT_AARCH64 U(12)
758#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
759#define SPSR_SSBS_SHIFT_AARCH32 U(23)
760#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
761
762#define SPSR_PAN_BIT BIT_64(22)
763
764#define SPSR_DIT_BIT BIT(24)
765
766#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
John Tsichritzis55534172019-07-23 11:12:41 +0100767
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100768#define DISABLE_ALL_EXCEPTIONS \
769 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
770
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000771#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
772
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000773/*
774 * RMR_EL3 definitions
775 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700776#define RMR_EL3_RR_BIT (U(1) << 1)
777#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000778
779/*
780 * HI-VECTOR address for AArch32 state
781 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000782#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100783
784/*
Elyes Haouas2be03c02023-02-13 09:14:48 +0100785 * TCR definitions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100786 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000787#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100788#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700789#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100790#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700791#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700792
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100793#define TCR_TxSZ_MIN ULL(16)
794#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000795#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100796
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000797#define TCR_T0SZ_SHIFT U(0)
798#define TCR_T1SZ_SHIFT U(16)
799
Lin Ma741a3822014-06-27 16:56:30 -0700800/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100801#define TCR_PS_BITS_4GB ULL(0x0)
802#define TCR_PS_BITS_64GB ULL(0x1)
803#define TCR_PS_BITS_1TB ULL(0x2)
804#define TCR_PS_BITS_4TB ULL(0x3)
805#define TCR_PS_BITS_16TB ULL(0x4)
806#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100807
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700808#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
809#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
810#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
811#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
812#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
813#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100814
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100815#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
816#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
817#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
818#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100819
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100820#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
821#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
822#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
823#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100824
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100825#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
826#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
827#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100828
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000829#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
830#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
831#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
832#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
833
834#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
835#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
836#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
837#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
838
839#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
840#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
841#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
842
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100843#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100844#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100845#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
846#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
847#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
848
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000849#define TCR_TG1_SHIFT U(30)
850#define TCR_TG1_MASK ULL(3)
851#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
852#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
853#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
854
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100855#define TCR_EPD0_BIT (ULL(1) << 7)
856#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100857
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700858#define MODE_SP_SHIFT U(0x0)
859#define MODE_SP_MASK U(0x1)
860#define MODE_SP_EL0 U(0x0)
861#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100862
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700863#define MODE_RW_SHIFT U(0x4)
864#define MODE_RW_MASK U(0x1)
865#define MODE_RW_64 U(0x0)
866#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100867
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700868#define MODE_EL_SHIFT U(0x2)
869#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000870#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700871#define MODE_EL3 U(0x3)
872#define MODE_EL2 U(0x2)
873#define MODE_EL1 U(0x1)
874#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100875
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700876#define MODE32_SHIFT U(0)
877#define MODE32_MASK U(0xf)
878#define MODE32_usr U(0x0)
879#define MODE32_fiq U(0x1)
880#define MODE32_irq U(0x2)
881#define MODE32_svc U(0x3)
882#define MODE32_mon U(0x6)
883#define MODE32_abt U(0x7)
884#define MODE32_hyp U(0xa)
885#define MODE32_und U(0xb)
886#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100887
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100888#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
889#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
890#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
891#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100892
John Tsichritzis55534172019-07-23 11:12:41 +0100893#define SPSR_64(el, sp, daif) \
894 (((MODE_RW_64 << MODE_RW_SHIFT) | \
895 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
896 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
897 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
898 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100899
900#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100901 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700902 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
903 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
904 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100905 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
906 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100907
Dan Handley0cdebbd2015-03-30 17:15:16 +0100908/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100909 * TTBR Definitions
910 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100911#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100912
913/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100914 * CTR_EL0 definitions
915 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700916#define CTR_CWG_SHIFT U(24)
917#define CTR_CWG_MASK U(0xf)
918#define CTR_ERG_SHIFT U(20)
919#define CTR_ERG_MASK U(0xf)
920#define CTR_DMINLINE_SHIFT U(16)
921#define CTR_DMINLINE_MASK U(0xf)
922#define CTR_L1IP_SHIFT U(14)
923#define CTR_L1IP_MASK U(0x3)
924#define CTR_IMINLINE_SHIFT U(0)
925#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100926
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700927#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100928
Achin Gupta405406d2014-05-09 12:00:17 +0100929/* Physical timer control register bit fields shifts and masks */
johpow01fa59c6f2020-10-02 13:41:11 -0500930#define CNTP_CTL_ENABLE_SHIFT U(0)
931#define CNTP_CTL_IMASK_SHIFT U(1)
932#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100933
johpow01fa59c6f2020-10-02 13:41:11 -0500934#define CNTP_CTL_ENABLE_MASK U(1)
935#define CNTP_CTL_IMASK_MASK U(1)
936#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100937
Varun Wadekar787a1292018-06-18 16:15:51 -0700938/* Physical timer control macros */
939#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
940#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
941
Achin Gupta4f6ad662013-10-25 09:08:21 +0100942/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700943#define ESR_EC_SHIFT U(26)
944#define ESR_EC_MASK U(0x3f)
945#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100946#define ESR_ISS_SHIFT U(0)
947#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700948#define EC_UNKNOWN U(0x0)
949#define EC_WFE_WFI U(0x1)
950#define EC_AARCH32_CP15_MRC_MCR U(0x3)
951#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
952#define EC_AARCH32_CP14_MRC_MCR U(0x5)
953#define EC_AARCH32_CP14_LDC_STC U(0x6)
954#define EC_FP_SIMD U(0x7)
955#define EC_AARCH32_CP10_MRC U(0x8)
956#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
957#define EC_ILLEGAL U(0xe)
958#define EC_AARCH32_SVC U(0x11)
959#define EC_AARCH32_HVC U(0x12)
960#define EC_AARCH32_SMC U(0x13)
961#define EC_AARCH64_SVC U(0x15)
962#define EC_AARCH64_HVC U(0x16)
963#define EC_AARCH64_SMC U(0x17)
964#define EC_AARCH64_SYS U(0x18)
965#define EC_IABORT_LOWER_EL U(0x20)
966#define EC_IABORT_CUR_EL U(0x21)
967#define EC_PC_ALIGN U(0x22)
968#define EC_DABORT_LOWER_EL U(0x24)
969#define EC_DABORT_CUR_EL U(0x25)
970#define EC_SP_ALIGN U(0x26)
971#define EC_AARCH32_FP U(0x28)
972#define EC_AARCH64_FP U(0x2c)
973#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100974#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100975
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000976/*
977 * External Abort bit in Instruction and Data Aborts synchronous exception
978 * syndromes.
979 */
980#define ESR_ISS_EABORT_EA_BIT U(9)
981
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700982#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100983
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800984/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700985#define RMR_RESET_REQUEST_SHIFT U(0x1)
986#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800987
Dan Handleyed6ff952014-05-14 17:44:19 +0100988/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000989 * Definitions of register offsets, fields and macros for CPU system
990 * instructions.
991 ******************************************************************************/
992
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700993#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000994#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
995#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
996
997/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100998 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
999 * system level implementation of the Generic Timer.
1000 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +01001001#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001002#define CNTNSAR U(0x4)
1003#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +01001004
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001005#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
1006#define CNTACR_RPCT_SHIFT U(0x0)
1007#define CNTACR_RVCT_SHIFT U(0x1)
1008#define CNTACR_RFRQ_SHIFT U(0x2)
1009#define CNTACR_RVOFF_SHIFT U(0x3)
1010#define CNTACR_RWVT_SHIFT U(0x4)
1011#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +01001012
Soby Mathew2d9f7952018-06-11 16:21:30 +01001013/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001014 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +01001015 * system level implementation of the Generic Timer.
1016 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001017/* Physical Count register. */
1018#define CNTPCT_LO U(0x0)
1019/* Counter Frequency register. */
1020#define CNTBASEN_CNTFRQ U(0x10)
1021/* Physical Timer CompareValue register. */
1022#define CNTP_CVAL_LO U(0x20)
1023/* Physical Timer Control register. */
1024#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +01001025
David Cunado5f55e282016-10-31 17:37:34 +00001026/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +01001027#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -07001028#define PMCR_EL0_N_SHIFT U(11)
1029#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +00001030#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +01001031#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +01001032#define PMCR_EL0_LC_BIT (U(1) << 6)
1033#define PMCR_EL0_DP_BIT (U(1) << 5)
1034#define PMCR_EL0_X_BIT (U(1) << 4)
1035#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +01001036#define PMCR_EL0_C_BIT (U(1) << 2)
1037#define PMCR_EL0_P_BIT (U(1) << 1)
1038#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +00001039
Isla Mitchell02c63072017-07-21 14:44:36 +01001040/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +01001041 * Definitions for system register interface to SVE
1042 ******************************************************************************/
1043#define ZCR_EL3 S3_6_C1_C2_0
1044#define ZCR_EL2 S3_4_C1_C2_0
1045
1046/* ZCR_EL3 definitions */
1047#define ZCR_EL3_LEN_MASK U(0xf)
1048
1049/* ZCR_EL2 definitions */
1050#define ZCR_EL2_LEN_MASK U(0xf)
1051
1052/*******************************************************************************
johpow019baade32021-07-08 14:14:00 -05001053 * Definitions for system register interface to SME as needed in EL3
1054 ******************************************************************************/
1055#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5
1056#define SMCR_EL3 S3_6_C1_C2_6
1057
1058/* ID_AA64SMFR0_EL1 definitions */
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +00001059#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
1060#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
1061#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001062#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
1063#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
1064#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
1065#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
johpow019baade32021-07-08 14:14:00 -05001066
1067/* SMCR_ELx definitions */
1068#define SMCR_ELX_LEN_SHIFT U(0)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001069#define SMCR_ELX_LEN_MAX U(0x1ff)
johpow019baade32021-07-08 14:14:00 -05001070#define SMCR_ELX_FA64_BIT (U(1) << 31)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +00001071#define SMCR_ELX_EZT0_BIT (U(1) << 30)
johpow019baade32021-07-08 14:14:00 -05001072
1073/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +01001074 * Definitions of MAIR encodings for device and normal memory
1075 ******************************************************************************/
1076/*
1077 * MAIR encodings for device memory attributes.
1078 */
1079#define MAIR_DEV_nGnRnE ULL(0x0)
1080#define MAIR_DEV_nGnRE ULL(0x4)
1081#define MAIR_DEV_nGRE ULL(0x8)
1082#define MAIR_DEV_GRE ULL(0xc)
1083
1084/*
1085 * MAIR encodings for normal memory attributes.
1086 *
1087 * Cache Policy
1088 * WT: Write Through
1089 * WB: Write Back
1090 * NC: Non-Cacheable
1091 *
1092 * Transient Hint
1093 * NTR: Non-Transient
1094 * TR: Transient
1095 *
1096 * Allocation Policy
1097 * RA: Read Allocate
1098 * WA: Write Allocate
1099 * RWA: Read and Write Allocate
1100 * NA: No Allocation
1101 */
1102#define MAIR_NORM_WT_TR_WA ULL(0x1)
1103#define MAIR_NORM_WT_TR_RA ULL(0x2)
1104#define MAIR_NORM_WT_TR_RWA ULL(0x3)
1105#define MAIR_NORM_NC ULL(0x4)
1106#define MAIR_NORM_WB_TR_WA ULL(0x5)
1107#define MAIR_NORM_WB_TR_RA ULL(0x6)
1108#define MAIR_NORM_WB_TR_RWA ULL(0x7)
1109#define MAIR_NORM_WT_NTR_NA ULL(0x8)
1110#define MAIR_NORM_WT_NTR_WA ULL(0x9)
1111#define MAIR_NORM_WT_NTR_RA ULL(0xa)
1112#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1113#define MAIR_NORM_WB_NTR_NA ULL(0xc)
1114#define MAIR_NORM_WB_NTR_WA ULL(0xd)
1115#define MAIR_NORM_WB_NTR_RA ULL(0xe)
1116#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1117
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001118#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +01001119
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001120#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
1121 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +01001122
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001123/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001124#define PAR_F_SHIFT U(0)
1125#define PAR_F_MASK ULL(0x1)
1126#define PAR_ADDR_SHIFT U(12)
1127#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001128
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01001129/*******************************************************************************
1130 * Definitions for system register interface to SPE
1131 ******************************************************************************/
1132#define PMBLIMITR_EL1 S3_0_C9_C10_0
1133
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001134/*******************************************************************************
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00001135 * Definitions for system register interface, shifts and masks for MPAM
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001136 ******************************************************************************/
1137#define MPAMIDR_EL1 S3_0_C10_C4_4
1138#define MPAM2_EL2 S3_4_C10_C5_0
1139#define MPAMHCR_EL2 S3_4_C10_C4_0
1140#define MPAM3_EL3 S3_6_C10_C5_0
1141
Andre Przywara84b86532022-11-17 16:42:09 +00001142#define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18)
1143#define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001144/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001145 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001146 ******************************************************************************/
1147#define AMCR_EL0 S3_3_C13_C2_0
1148#define AMCFGR_EL0 S3_3_C13_C2_1
1149#define AMCGCR_EL0 S3_3_C13_C2_2
1150#define AMUSERENR_EL0 S3_3_C13_C2_3
1151#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
1152#define AMCNTENSET0_EL0 S3_3_C13_C2_5
1153#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
1154#define AMCNTENSET1_EL0 S3_3_C13_C3_1
1155
1156/* Activity Monitor Group 0 Event Counter Registers */
1157#define AMEVCNTR00_EL0 S3_3_C13_C4_0
1158#define AMEVCNTR01_EL0 S3_3_C13_C4_1
1159#define AMEVCNTR02_EL0 S3_3_C13_C4_2
1160#define AMEVCNTR03_EL0 S3_3_C13_C4_3
1161
1162/* Activity Monitor Group 0 Event Type Registers */
1163#define AMEVTYPER00_EL0 S3_3_C13_C6_0
1164#define AMEVTYPER01_EL0 S3_3_C13_C6_1
1165#define AMEVTYPER02_EL0 S3_3_C13_C6_2
1166#define AMEVTYPER03_EL0 S3_3_C13_C6_3
1167
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001168/* Activity Monitor Group 1 Event Counter Registers */
1169#define AMEVCNTR10_EL0 S3_3_C13_C12_0
1170#define AMEVCNTR11_EL0 S3_3_C13_C12_1
1171#define AMEVCNTR12_EL0 S3_3_C13_C12_2
1172#define AMEVCNTR13_EL0 S3_3_C13_C12_3
1173#define AMEVCNTR14_EL0 S3_3_C13_C12_4
1174#define AMEVCNTR15_EL0 S3_3_C13_C12_5
1175#define AMEVCNTR16_EL0 S3_3_C13_C12_6
1176#define AMEVCNTR17_EL0 S3_3_C13_C12_7
1177#define AMEVCNTR18_EL0 S3_3_C13_C13_0
1178#define AMEVCNTR19_EL0 S3_3_C13_C13_1
1179#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
1180#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
1181#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
1182#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
1183#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
1184#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
1185
1186/* Activity Monitor Group 1 Event Type Registers */
1187#define AMEVTYPER10_EL0 S3_3_C13_C14_0
1188#define AMEVTYPER11_EL0 S3_3_C13_C14_1
1189#define AMEVTYPER12_EL0 S3_3_C13_C14_2
1190#define AMEVTYPER13_EL0 S3_3_C13_C14_3
1191#define AMEVTYPER14_EL0 S3_3_C13_C14_4
1192#define AMEVTYPER15_EL0 S3_3_C13_C14_5
1193#define AMEVTYPER16_EL0 S3_3_C13_C14_6
1194#define AMEVTYPER17_EL0 S3_3_C13_C14_7
1195#define AMEVTYPER18_EL0 S3_3_C13_C15_0
1196#define AMEVTYPER19_EL0 S3_3_C13_C15_1
1197#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
1198#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
1199#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
1200#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
1201#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
1202#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
1203
Chris Kaya5fde282021-05-26 11:58:23 +01001204/* AMCNTENSET0_EL0 definitions */
1205#define AMCNTENSET0_EL0_Pn_SHIFT U(0)
1206#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1207
1208/* AMCNTENSET1_EL0 definitions */
1209#define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1210#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1211
1212/* AMCNTENCLR0_EL0 definitions */
1213#define AMCNTENCLR0_EL0_Pn_SHIFT U(0)
1214#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1215
1216/* AMCNTENCLR1_EL0 definitions */
1217#define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1218#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1219
Alexei Fedorov7e6306b2020-07-14 08:17:56 +01001220/* AMCFGR_EL0 definitions */
1221#define AMCFGR_EL0_NCG_SHIFT U(28)
1222#define AMCFGR_EL0_NCG_MASK U(0xf)
1223#define AMCFGR_EL0_N_SHIFT U(0)
1224#define AMCFGR_EL0_N_MASK U(0xff)
1225
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001226/* AMCGCR_EL0 definitions */
Chris Kaya40141d2021-05-25 12:33:18 +01001227#define AMCGCR_EL0_CG0NC_SHIFT U(0)
1228#define AMCGCR_EL0_CG0NC_MASK U(0xff)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001229#define AMCGCR_EL0_CG1NC_SHIFT U(8)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001230#define AMCGCR_EL0_CG1NC_MASK U(0xff)
1231
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001232/* MPAM register definitions */
1233#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001234#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1235
1236#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1237#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001238
1239#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1240
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001241/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001242 * Definitions for system register interface to AMU for FEAT_AMUv1p1
1243 ******************************************************************************/
1244
1245/* Definition for register defining which virtual offsets are implemented. */
1246#define AMCG1IDR_EL0 S3_3_C13_C2_6
1247#define AMCG1IDR_CTR_MASK ULL(0xffff)
1248#define AMCG1IDR_CTR_SHIFT U(0)
1249#define AMCG1IDR_VOFF_MASK ULL(0xffff)
1250#define AMCG1IDR_VOFF_SHIFT U(16)
1251
1252/* New bit added to AMCR_EL0 */
Chris Kaya5fde282021-05-26 11:58:23 +01001253#define AMCR_CG1RZ_SHIFT U(17)
1254#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)
johpow01fa59c6f2020-10-02 13:41:11 -05001255
1256/*
1257 * Definitions for virtual offset registers for architected activity monitor
1258 * event counters.
1259 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
1260 */
1261#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
1262#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
1263#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
1264
1265/*
1266 * Definitions for virtual offset registers for auxiliary activity monitor event
1267 * counters.
1268 */
1269#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
1270#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
1271#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
1272#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
1273#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
1274#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
1275#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
1276#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
1277#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
1278#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
1279#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
1280#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
1281#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
1282#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
1283#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
1284#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
1285
1286/*******************************************************************************
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001287 * Realm management extension register definitions
1288 ******************************************************************************/
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001289#define GPCCR_EL3 S3_6_C2_C1_6
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001290#define GPTBR_EL3 S3_6_C2_C1_4
1291
Andre Przywara3edbfa72023-03-28 16:55:06 +01001292#define SCXTNUM_EL2 S3_4_C13_C0_7
1293
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001294/*******************************************************************************
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001295 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +00001296 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001297#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001298#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001299
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001300#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001301#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001302
1303#define ERRSELR_EL1 S3_0_C5_C3_1
1304
1305/* System register access to Standard Error Record registers */
1306#define ERXFR_EL1 S3_0_C5_C4_0
1307#define ERXCTLR_EL1 S3_0_C5_C4_1
1308#define ERXSTATUS_EL1 S3_0_C5_C4_2
1309#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001310#define ERXPFGF_EL1 S3_0_C5_C4_4
1311#define ERXPFGCTL_EL1 S3_0_C5_C4_5
1312#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +02001313#define ERXMISC0_EL1 S3_0_C5_C5_0
1314#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001315
johpow017d52a8f2022-03-09 16:23:04 -06001316#define ERXCTLR_ED_SHIFT U(0)
1317#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001318#define ERXCTLR_UE_BIT (U(1) << 4)
1319
1320#define ERXPFGCTL_UC_BIT (U(1) << 1)
1321#define ERXPFGCTL_UEU_BIT (U(1) << 2)
1322#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1323
1324/*******************************************************************************
1325 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +00001326 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001327#define APIAKeyLo_EL1 S3_0_C2_C1_0
1328#define APIAKeyHi_EL1 S3_0_C2_C1_1
1329#define APIBKeyLo_EL1 S3_0_C2_C1_2
1330#define APIBKeyHi_EL1 S3_0_C2_C1_3
1331#define APDAKeyLo_EL1 S3_0_C2_C2_0
1332#define APDAKeyHi_EL1 S3_0_C2_C2_1
1333#define APDBKeyLo_EL1 S3_0_C2_C2_2
1334#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001335#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001336#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001337
Sathees Balya0911df12018-12-06 13:33:24 +00001338/*******************************************************************************
1339 * Armv8.4 Data Independent Timing Registers
1340 ******************************************************************************/
1341#define DIT S3_3_C4_C2_5
1342#define DIT_BIT BIT(24)
1343
John Tsichritzis1f9ff492019-03-04 16:41:26 +00001344/*******************************************************************************
1345 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1346 ******************************************************************************/
1347#define SSBS S3_3_C4_C2_6
1348
Justin Chadwell1c7c13a2019-07-18 14:25:33 +01001349/*******************************************************************************
1350 * Armv8.5 - Memory Tagging Extension Registers
1351 ******************************************************************************/
1352#define TFSRE0_EL1 S3_0_C5_C6_1
1353#define TFSR_EL1 S3_0_C5_C6_0
1354#define RGSR_EL1 S3_0_C1_C0_5
1355#define GCR_EL1 S3_0_C1_C0_6
1356
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001357/*******************************************************************************
Andre Przywarabdc76f12022-11-21 17:07:25 +00001358 * Armv8.5 - Random Number Generator Registers
1359 ******************************************************************************/
1360#define RNDR S3_3_C2_C4_0
1361#define RNDRRS S3_3_C2_C4_1
1362
1363/*******************************************************************************
johpow01f91e59f2021-08-04 19:38:18 -05001364 * FEAT_HCX - Extended Hypervisor Configuration Register
1365 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -05001366#define HCRX_EL2 S3_4_C1_C2_2
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001367#define HCRX_EL2_MSCEn_BIT (UL(1) << 11)
1368#define HCRX_EL2_MCE2_BIT (UL(1) << 10)
1369#define HCRX_EL2_CMOW_BIT (UL(1) << 9)
1370#define HCRX_EL2_VFNMI_BIT (UL(1) << 8)
1371#define HCRX_EL2_VINMI_BIT (UL(1) << 7)
1372#define HCRX_EL2_TALLINT_BIT (UL(1) << 6)
1373#define HCRX_EL2_SMPME_BIT (UL(1) << 5)
johpow019baade32021-07-08 14:14:00 -05001374#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4)
1375#define HCRX_EL2_FnXS_BIT (UL(1) << 3)
1376#define HCRX_EL2_EnASR_BIT (UL(1) << 2)
1377#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
1378#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001379#define HCRX_EL2_INIT_VAL ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -05001380
1381/*******************************************************************************
Juan Pablo Condef7252982023-07-10 16:00:41 -05001382 * FEAT_FGT - Definitions for Fine-Grained Trap registers
1383 ******************************************************************************/
1384#define HFGITR_EL2_INIT_VAL ULL(0x180000000000000)
1385#define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000)
1386#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)
1387
1388/*******************************************************************************
Mark Brownc37eee72023-03-14 20:13:03 +00001389 * FEAT_TCR2 - Extended Translation Control Register
1390 ******************************************************************************/
1391#define TCR2_EL2 S3_4_C2_C0_3
1392
1393/*******************************************************************************
Mark Brown293a6612023-03-14 20:48:43 +00001394 * Permission indirection and overlay
1395 ******************************************************************************/
1396
1397#define PIRE0_EL2 S3_4_C10_C2_2
1398#define PIR_EL2 S3_4_C10_C2_3
1399#define POR_EL2 S3_4_C10_C2_4
1400#define S2PIR_EL2 S3_4_C10_C2_5
1401
1402/*******************************************************************************
Mark Brown326f2952023-03-14 21:33:04 +00001403 * FEAT_GCS - Guarded Control Stack Registers
1404 ******************************************************************************/
1405#define GCSCR_EL2 S3_4_C2_C5_0
1406#define GCSPR_EL2 S3_4_C2_C5_1
1407
1408/*******************************************************************************
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001409 * Definitions for DynamicIQ Shared Unit registers
1410 ******************************************************************************/
1411#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
1412
1413/* CLUSTERPWRDN_EL1 register definitions */
1414#define DSU_CLUSTER_PWR_OFF 0
1415#define DSU_CLUSTER_PWR_ON 1
1416#define DSU_CLUSTER_PWR_MASK U(1)
1417
Chris Kay03be39d2021-05-05 13:38:30 +01001418/*******************************************************************************
1419 * Definitions for CPU Power/Performance Management registers
1420 ******************************************************************************/
1421
1422#define CPUPPMCR_EL3 S3_6_C15_C2_0
1423#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0)
1424#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1)
1425
1426#define CPUMPMMCR_EL3 S3_6_C15_C2_1
1427#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
1428#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
1429
Andre Przywarac735f1c2022-11-25 14:10:13 +00001430/* alternative system register encoding for the "sb" speculation barrier */
1431#define SYSREG_SB S0_3_C3_C0_7
1432
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01001433#endif /* ARCH_H */