Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef ZYNQMP_DEF_H |
| 8 | #define ZYNQMP_DEF_H |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 9 | |
Manish V Badarkhe | 5586151 | 2020-03-27 13:25:51 +0000 | [diff] [blame] | 10 | #include <plat/arm/common/smccc_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <plat/common/common_def.h> |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 12 | |
Soren Brinkmann | 99c0d7b | 2016-06-10 09:57:14 -0700 | [diff] [blame] | 13 | #define ZYNQMP_CONSOLE_ID_cadence 1 |
| 14 | #define ZYNQMP_CONSOLE_ID_cadence0 1 |
| 15 | #define ZYNQMP_CONSOLE_ID_cadence1 2 |
| 16 | #define ZYNQMP_CONSOLE_ID_dcc 3 |
| 17 | |
Michal Simek | c56e548 | 2023-09-27 13:58:06 +0200 | [diff] [blame^] | 18 | #define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) |
Soren Brinkmann | 99c0d7b | 2016-06-10 09:57:14 -0700 | [diff] [blame] | 19 | |
Rajan Vaja | 12be18b | 2021-03-26 04:16:36 -0700 | [diff] [blame] | 20 | /* Default counter frequency */ |
| 21 | #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U |
| 22 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 23 | /* Firmware Image Package */ |
| 24 | #define ZYNQMP_PRIMARY_CPU 0 |
| 25 | |
| 26 | /* Memory location options for Shared data and TSP in ZYNQMP */ |
| 27 | #define ZYNQMP_IN_TRUSTED_SRAM 0 |
| 28 | #define ZYNQMP_IN_TRUSTED_DRAM 1 |
| 29 | |
| 30 | /******************************************************************************* |
| 31 | * ZYNQMP memory map related constants |
| 32 | ******************************************************************************/ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 33 | /* Aggregate of all devices in the first GB */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 34 | #define DEVICE0_BASE U(0xFF000000) |
| 35 | #define DEVICE0_SIZE U(0x00E00000) |
| 36 | #define DEVICE1_BASE U(0xF9000000) |
| 37 | #define DEVICE1_SIZE U(0x00800000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 38 | |
| 39 | /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 40 | #define CRF_APB_BASE U(0xFD1A0000) |
| 41 | #define CRF_APB_SIZE U(0x00600000) |
| 42 | #define CRF_APB_CLK_BASE U(0xFD1A0020) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 43 | |
| 44 | /* CRF registers and bitfields */ |
| 45 | #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) |
| 46 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 47 | #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) |
| 48 | #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 49 | |
| 50 | /* CRL registers and bitfields */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 51 | #define CRL_APB_BASE U(0xFF5E0000) |
Soren Brinkmann | b43d943 | 2016-04-18 11:49:42 -0700 | [diff] [blame] | 52 | #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 53 | #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 54 | #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) |
Siva Durga Prasad Paladugu | ed1d5cb | 2018-09-04 17:03:25 +0530 | [diff] [blame] | 55 | #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 56 | #define CRL_APB_CLK_BASE U(0xFF5E0020) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 57 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 58 | #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) |
| 59 | #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 60 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 61 | #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 62 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 63 | #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) |
Siva Durga Prasad Paladugu | ed1d5cb | 2018-09-04 17:03:25 +0530 | [diff] [blame] | 64 | #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) |
| 65 | #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) |
| 66 | #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 67 | #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ |
| 68 | CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) |
| 69 | #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ |
| 70 | CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 71 | #define ZYNQMP_BOOTMODE_JTAG U(0) |
Siva Durga Prasad Paladugu | ed1d5cb | 2018-09-04 17:03:25 +0530 | [diff] [blame] | 72 | #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ |
| 73 | CRL_APB_BOOT_DRIVE_PIN_1) |
| 74 | #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 |
Soren Brinkmann | b43d943 | 2016-04-18 11:49:42 -0700 | [diff] [blame] | 75 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 76 | /* system counter registers and bitfields */ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 77 | #define IOU_SCNTRS_BASE U(0xFF260000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 78 | #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) |
| 79 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 80 | /* APU registers and bitfields */ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 81 | #define APU_BASE U(0xFD5C0000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 82 | #define APU_CONFIG_0 (APU_BASE + 0x20) |
| 83 | #define APU_RVBAR_L_0 (APU_BASE + 0x40) |
| 84 | #define APU_RVBAR_H_0 (APU_BASE + 0x44) |
| 85 | #define APU_PWRCTL (APU_BASE + 0x90) |
| 86 | |
| 87 | #define APU_CONFIG_0_VINITHI_SHIFT 8 |
| 88 | #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 |
| 89 | #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 |
| 90 | #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 |
| 91 | #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 |
| 92 | |
| 93 | /* PMU registers and bitfields */ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 94 | #define PMU_GLOBAL_BASE U(0xFFD80000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 95 | #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) |
Michal Simek | ef8f559 | 2015-06-15 14:22:50 +0200 | [diff] [blame] | 96 | #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 97 | #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) |
| 98 | #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) |
| 99 | #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) |
| 100 | #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) |
| 101 | |
| 102 | #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) |
| 103 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 104 | /******************************************************************************* |
| 105 | * CCI-400 related constants |
| 106 | ******************************************************************************/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 107 | #define PLAT_ARM_CCI_BASE U(0xFD6E0000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 108 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 109 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 |
| 110 | |
| 111 | /******************************************************************************* |
| 112 | * GIC-400 & interrupt handling related constants |
| 113 | ******************************************************************************/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 114 | #define BASE_GICD_BASE U(0xF9010000) |
| 115 | #define BASE_GICC_BASE U(0xF9020000) |
| 116 | #define BASE_GICH_BASE U(0xF9040000) |
| 117 | #define BASE_GICV_BASE U(0xF9060000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 118 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 119 | #if ZYNQMP_WDT_RESTART |
| 120 | #define IRQ_SEC_IPI_APU 67 |
| 121 | #define IRQ_TTC3_1 77 |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 122 | #define TTC3_BASE_ADDR U(0xFF140000) |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 123 | #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) |
| 124 | #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) |
| 125 | #endif |
| 126 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 127 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 128 | |
| 129 | #define ARM_IRQ_SEC_SGI_0 8 |
| 130 | #define ARM_IRQ_SEC_SGI_1 9 |
| 131 | #define ARM_IRQ_SEC_SGI_2 10 |
| 132 | #define ARM_IRQ_SEC_SGI_3 11 |
| 133 | #define ARM_IRQ_SEC_SGI_4 12 |
| 134 | #define ARM_IRQ_SEC_SGI_5 13 |
| 135 | #define ARM_IRQ_SEC_SGI_6 14 |
| 136 | #define ARM_IRQ_SEC_SGI_7 15 |
| 137 | |
Prasad Kummari | eeef80d | 2023-05-11 14:58:13 +0530 | [diff] [blame] | 138 | /* number of interrupt handlers. increase as required */ |
| 139 | #define MAX_INTR_EL3 2 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 140 | |
| 141 | /******************************************************************************* |
| 142 | * UART related constants |
| 143 | ******************************************************************************/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 144 | #define ZYNQMP_UART0_BASE U(0xFF000000) |
| 145 | #define ZYNQMP_UART1_BASE U(0xFF010000) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 146 | |
Michal Simek | c56e548 | 2023-09-27 13:58:06 +0200 | [diff] [blame^] | 147 | #if CONSOLE_IS(cadence) || CONSOLE_IS(dcc) |
| 148 | # define UART_BASE ZYNQMP_UART0_BASE |
| 149 | #elif CONSOLE_IS(cadence1) |
| 150 | # define UART_BASE ZYNQMP_UART1_BASE |
Soren Brinkmann | 99c0d7b | 2016-06-10 09:57:14 -0700 | [diff] [blame] | 151 | #else |
| 152 | # error "invalid ZYNQMP_CONSOLE" |
| 153 | #endif |
| 154 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 155 | /* Must be non zero */ |
Michal Simek | c56e548 | 2023-09-27 13:58:06 +0200 | [diff] [blame^] | 156 | #define UART_BAUDRATE 115200 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 157 | |
| 158 | /* Silicon version detection */ |
| 159 | #define ZYNQMP_SILICON_VER_MASK 0xF000 |
| 160 | #define ZYNQMP_SILICON_VER_SHIFT 12 |
| 161 | #define ZYNQMP_CSU_VERSION_SILICON 0 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 162 | #define ZYNQMP_CSU_VERSION_QEMU 3 |
| 163 | |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 164 | #define ZYNQMP_RTL_VER_MASK 0xFF0U |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 165 | #define ZYNQMP_RTL_VER_SHIFT 4 |
| 166 | |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 167 | #define ZYNQMP_PS_VER_MASK 0xFU |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 168 | #define ZYNQMP_PS_VER_SHIFT 0 |
| 169 | |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 170 | #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 171 | #define ZYNQMP_CSU_IDCODE_OFFSET 0x40U |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 172 | |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 173 | #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U |
| 174 | #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 175 | ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 176 | #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 |
| 177 | |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 178 | #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U |
| 179 | #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ |
Siva Durga Prasad Paladugu | b982d16 | 2017-08-01 10:23:19 +0530 | [diff] [blame] | 180 | ZYNQMP_CSU_IDCODE_SVD_SHIFT) |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 181 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U |
| 182 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 183 | ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 184 | #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U |
| 185 | #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 186 | ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 187 | #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U |
| 188 | #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 189 | ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 190 | #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 |
| 191 | |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 192 | #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U |
| 193 | #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ |
Jolly Shah | 16fe5ab | 2019-01-08 11:16:16 -0800 | [diff] [blame] | 194 | ZYNQMP_CSU_IDCODE_REVISION_SHIFT) |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 195 | #define ZYNQMP_CSU_IDCODE_REVISION 0U |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 196 | |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 197 | #define ZYNQMP_CSU_VERSION_OFFSET 0x44U |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 198 | |
Siva Durga Prasad Paladugu | 83e3725 | 2018-05-01 11:10:25 +0530 | [diff] [blame] | 199 | /* Efuse */ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 200 | #define EFUSE_BASEADDR U(0xFFCC0000) |
Siva Durga Prasad Paladugu | 83e3725 | 2018-05-01 11:10:25 +0530 | [diff] [blame] | 201 | #define EFUSE_IPDISABLE_OFFSET 0x1018 |
| 202 | #define EFUSE_IPDISABLE_VERSION 0x1FFU |
Siva Durga Prasad Paladugu | b76656d | 2018-03-05 18:47:15 +0530 | [diff] [blame] | 203 | #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 |
Siva Durga Prasad Paladugu | 83e3725 | 2018-05-01 11:10:25 +0530 | [diff] [blame] | 204 | |
Naga Sureshkumar Relli | cf4e714 | 2016-07-01 12:46:43 +0530 | [diff] [blame] | 205 | /* Access control register defines */ |
| 206 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 207 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 208 | |
Siva Durga Prasad Paladugu | 90539cd | 2018-09-04 17:33:19 +0530 | [diff] [blame] | 209 | #define FPD_SLCR_BASEADDR U(0xFD610000) |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 210 | #define IOU_SLCR_BASEADDR U(0xFF180000) |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 211 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 212 | #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) |
| 213 | #define ZYNQMP_RPU0_CFG U(0xFF9A0100) |
| 214 | #define ZYNQMP_RPU1_CFG U(0xFF9A0200) |
| 215 | #define ZYNQMP_SLSPLIT_MASK U(0x08) |
| 216 | #define ZYNQMP_TCM_COMB_MASK U(0x40) |
| 217 | #define ZYNQMP_SLCLAMP_MASK U(0x10) |
| 218 | #define ZYNQMP_VINITHI_MASK U(0x04) |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 219 | |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 220 | /* Tap delay bypass */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 221 | #define IOU_TAPDLY_BYPASS U(0XFF180390) |
| 222 | #define TAP_DELAY_MASK U(0x7) |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 223 | |
| 224 | /* SGMII mode */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 225 | #define IOU_GEM_CTRL U(0xFF180360) |
| 226 | #define IOU_GEM_CLK_CTRL U(0xFF180308) |
| 227 | #define SGMII_SD_MASK U(0x3) |
| 228 | #define SGMII_SD_OFFSET U(2) |
| 229 | #define SGMII_PCS_SD_0 U(0x0) |
| 230 | #define SGMII_PCS_SD_1 U(0x1) |
| 231 | #define SGMII_PCS_SD_PHY U(0x2) |
| 232 | #define GEM_SGMII_MASK U(0x4) |
| 233 | #define GEM_CLK_CTRL_MASK U(0xF) |
| 234 | #define GEM_CLK_CTRL_OFFSET U(5) |
| 235 | #define GEM_RX_SRC_SEL_GTR U(0x1) |
| 236 | #define GEM_SGMII_MODE U(0x4) |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 237 | |
| 238 | /* SD DLL reset */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 239 | #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) |
| 240 | #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) |
| 241 | #define ZYNQMP_SD0_DLL_RST U(0x00000004) |
| 242 | #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) |
| 243 | #define ZYNQMP_SD1_DLL_RST U(0x00040000) |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 244 | |
| 245 | /* SD tap delay */ |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 246 | #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) |
| 247 | #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) |
| 248 | #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) |
| 249 | #define ZYNQMP_SD_TAP_OFFSET U(16) |
| 250 | #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) |
| 251 | #define ZYNQMP_SD_ITAPCHGWIN U(0x200) |
| 252 | #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) |
| 253 | #define ZYNQMP_SD_ITAPDLYENA U(0x100) |
| 254 | #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) |
| 255 | #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) |
| 256 | #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) |
| 257 | #define ZYNQMP_SD_OTAPDLYENA U(0x40) |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 258 | |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 259 | /* Clock control registers */ |
| 260 | /* Full power domain clocks */ |
| 261 | #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) |
| 262 | #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) |
| 263 | #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) |
| 264 | #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) |
| 265 | #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) |
| 266 | #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) |
| 267 | #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) |
| 268 | /* Peripheral clocks */ |
| 269 | #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) |
| 270 | #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) |
| 271 | #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) |
| 272 | #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) |
| 273 | #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) |
| 274 | #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) |
| 275 | #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) |
| 276 | #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) |
| 277 | #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) |
| 278 | #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) |
| 279 | #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) |
| 280 | #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) |
| 281 | #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) |
| 282 | #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) |
| 283 | #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) |
| 284 | #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) |
| 285 | |
| 286 | /* Low power domain clocks */ |
| 287 | #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) |
| 288 | #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) |
| 289 | #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) |
| 290 | #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) |
| 291 | #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) |
| 292 | /* Peripheral clocks */ |
| 293 | #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) |
| 294 | #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) |
| 295 | #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) |
| 296 | #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) |
| 297 | #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) |
| 298 | #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) |
| 299 | #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) |
| 300 | #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) |
| 301 | #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) |
| 302 | #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) |
| 303 | #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) |
| 304 | #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) |
| 305 | #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) |
| 306 | #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) |
| 307 | #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) |
| 308 | #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) |
| 309 | #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) |
| 310 | #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) |
| 311 | #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) |
| 312 | #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) |
| 313 | #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) |
| 314 | #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) |
| 315 | #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) |
| 316 | #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) |
| 317 | #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) |
| 318 | #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) |
| 319 | #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) |
| 320 | #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) |
| 321 | #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) |
| 322 | #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) |
| 323 | #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) |
| 324 | #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) |
| 325 | #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) |
| 326 | #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) |
| 327 | #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) |
| 328 | #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) |
| 329 | #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) |
| 330 | #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) |
| 331 | #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) |
| 332 | #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) |
| 333 | #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) |
Siva Durga Prasad Paladugu | 90539cd | 2018-09-04 17:33:19 +0530 | [diff] [blame] | 334 | #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) |
Mounika Grace Akula | 591ad4d | 2019-01-09 17:38:13 +0530 | [diff] [blame] | 335 | #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 336 | |
Rajan Vaja | 393c0a2 | 2018-01-17 02:39:27 -0800 | [diff] [blame] | 337 | /* Global general storage register base address */ |
| 338 | #define GGS_BASEADDR (0xFFD80030U) |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 339 | #define GGS_NUM_REGS U(4) |
Rajan Vaja | 393c0a2 | 2018-01-17 02:39:27 -0800 | [diff] [blame] | 340 | |
| 341 | /* Persistent global general storage register base address */ |
| 342 | #define PGGS_BASEADDR (0xFFD80050U) |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 343 | #define PGGS_NUM_REGS U(4) |
Rajan Vaja | 393c0a2 | 2018-01-17 02:39:27 -0800 | [diff] [blame] | 344 | |
Tejas Patel | 6552a55 | 2020-11-22 23:37:55 -0800 | [diff] [blame] | 345 | /* PMU GGS4 register 4 is used for warm restart boot health status */ |
| 346 | #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) |
| 347 | /* Warm restart boot health status mask */ |
Siva Durga Prasad Paladugu | ac8526f | 2018-09-04 17:12:51 +0530 | [diff] [blame] | 348 | #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) |
Will Wong | cc12795 | 2020-11-22 23:45:21 -0800 | [diff] [blame] | 349 | /* WDT restart scope shift and mask */ |
| 350 | #define RESTART_SCOPE_SHIFT (3) |
| 351 | #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) |
Siva Durga Prasad Paladugu | ac8526f | 2018-09-04 17:12:51 +0530 | [diff] [blame] | 352 | |
Michal Simek | 7bb61a8 | 2022-09-14 09:35:09 +0200 | [diff] [blame] | 353 | /* AFI registers */ |
Siva Durga Prasad Paladugu | a22b885 | 2018-09-04 17:27:12 +0530 | [diff] [blame] | 354 | #define AFIFM6_WRCTRL U(13) |
| 355 | #define FABRIC_WIDTH U(3) |
| 356 | |
Kalyani Akula | 6ebe483 | 2020-11-22 22:42:10 -0800 | [diff] [blame] | 357 | /* CSUDMA Module Base Address*/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 358 | #define CSUDMA_BASE U(0xFFC80000) |
Kalyani Akula | 6ebe483 | 2020-11-22 22:42:10 -0800 | [diff] [blame] | 359 | |
| 360 | /* RSA-CORE Module Base Address*/ |
Venkatesh Yadav Abbarapu | ed4f1e8 | 2022-04-29 09:58:30 +0530 | [diff] [blame] | 361 | #define RSA_CORE_BASE U(0xFFCE0000) |
Kalyani Akula | 6ebe483 | 2020-11-22 22:42:10 -0800 | [diff] [blame] | 362 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 363 | #endif /* ZYNQMP_DEF_H */ |