commit cf4e7146bc636f7b307d7d5ab378417060ac8886
author Naga Sureshkumar Relli <nagasure@xilinx.com> Fri Jul 01 12:46:43 2016 +0530
committer Soren Brinkmann <soren.brinkmann@xilinx.com> Tue Sep 13 09:19:02 2016 -0700
tree 5fd42e5ebc670e5e2437fa7c88880474f294b9ec
parent 92b8932a7f5271d4903a89f0366e6217abd30d41

zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1

Arm provided error injection support. To enable this error injection,
we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in
CPUACTLR_EL1 register.

This is needed for our cortexa53 edac linux driver testing.
These registers need write access from non secure EL1 i.e linux
at the time of setting the above bits.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>

plat/xilinx/zynqmp/zynqmp_def.h

diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index 4bb332e..65bc25f 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -201,4 +201,8 @@
 
 #define ZYNQMP_CSU_VERSION_OFFSET	0x44
 
+/* Access control register defines */
+#define ACTLR_EL3_L2ACTLR_BIT	(1 << 6)
+#define ACTLR_EL3_CPUACTLR_BIT	(1 << 0)
+
 #endif /* __ZYNQMP_DEF_H__ */