blob: 65bc25f821f752a22d49ca3aba423d3350677820 [file] [log] [blame]
Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ZYNQMP_DEF_H__
32#define __ZYNQMP_DEF_H__
33
34#include <common_def.h>
35
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070036#define ZYNQMP_CONSOLE_ID_cadence 1
37#define ZYNQMP_CONSOLE_ID_cadence0 1
38#define ZYNQMP_CONSOLE_ID_cadence1 2
39#define ZYNQMP_CONSOLE_ID_dcc 3
40
41#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
42
Soren Brinkmann76fcae32016-03-06 20:16:27 -080043/* Firmware Image Package */
44#define ZYNQMP_PRIMARY_CPU 0
45
46/* Memory location options for Shared data and TSP in ZYNQMP */
47#define ZYNQMP_IN_TRUSTED_SRAM 0
48#define ZYNQMP_IN_TRUSTED_DRAM 1
49
50/*******************************************************************************
51 * ZYNQMP memory map related constants
52 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080053/* Aggregate of all devices in the first GB */
54#define DEVICE0_BASE 0xFF000000
55#define DEVICE0_SIZE 0x00E00000
56#define DEVICE1_BASE 0xF9000000
Soren Brinkmann845cd5c2016-04-22 10:02:46 -070057#define DEVICE1_SIZE 0x00800000
Soren Brinkmann76fcae32016-03-06 20:16:27 -080058
59/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
60#define CRF_APB_BASE 0xFD1A0000
61#define CRF_APB_SIZE 0x00600000
62
63/* CRF registers and bitfields */
64#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
65
66#define CRF_APB_RST_FPD_APU_ACPU_RESET (1 << 0)
67#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (1 << 10)
68
69/* CRL registers and bitfields */
70#define CRL_APB_BASE 0xFF5E0000
71#define CRL_APB_RPLL_CTRL (CRL_APB_BASE + 0x30)
72#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_BASE + 0x128)
Soren Brinkmannb43d9432016-04-18 11:49:42 -070073#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080074#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
75
76#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 24)
77
78#define CRL_APB_RPLL_CTRL_BYPASS (1 << 3)
79
80#define CRL_APB_RESET_CTRL_SOFT_RESET (1 << 4)
81
Soren Brinkmannb43d9432016-04-18 11:49:42 -070082#define CRL_APB_BOOT_MODE_MASK (0xf << 0)
83#define ZYNQMP_BOOTMODE_JTAG 0
84
Soren Brinkmann76fcae32016-03-06 20:16:27 -080085/* system counter registers and bitfields */
86#define IOU_SCNTRS_BASE 0xFF260000
87#define IOU_SCNTRS_CONTROL (IOU_SCNTRS_BASE + 0)
88#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
89
90#define IOU_SCNTRS_CONTROL_EN (1 << 0)
91
92/* APU registers and bitfields */
93#define APU_BASE 0xFD5C0000
94#define APU_CONFIG_0 (APU_BASE + 0x20)
95#define APU_RVBAR_L_0 (APU_BASE + 0x40)
96#define APU_RVBAR_H_0 (APU_BASE + 0x44)
97#define APU_PWRCTL (APU_BASE + 0x90)
98
99#define APU_CONFIG_0_VINITHI_SHIFT 8
100#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
101#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
102#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4
103#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
104
105/* PMU registers and bitfields */
106#define PMU_GLOBAL_BASE 0xFFD80000
107#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
Michal Simekef8f5592015-06-15 14:22:50 +0200108#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800109#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
110#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
111#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
112#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120)
113
114#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
115
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800116/*******************************************************************************
117 * CCI-400 related constants
118 ******************************************************************************/
119#define PLAT_ARM_CCI_BASE 0xFD6E0000
120#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
121#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
122
123/*******************************************************************************
124 * GIC-400 & interrupt handling related constants
125 ******************************************************************************/
126#define BASE_GICD_BASE 0xF9010000
127#define BASE_GICC_BASE 0xF9020000
128#define BASE_GICH_BASE 0xF9040000
129#define BASE_GICV_BASE 0xF9060000
130
131#define IRQ_SEC_IPI_APU 67
132#define ARM_IRQ_SEC_PHY_TIMER 29
133
134#define ARM_IRQ_SEC_SGI_0 8
135#define ARM_IRQ_SEC_SGI_1 9
136#define ARM_IRQ_SEC_SGI_2 10
137#define ARM_IRQ_SEC_SGI_3 11
138#define ARM_IRQ_SEC_SGI_4 12
139#define ARM_IRQ_SEC_SGI_5 13
140#define ARM_IRQ_SEC_SGI_6 14
141#define ARM_IRQ_SEC_SGI_7 15
142
143#define MAX_INTR_EL3 128
144
145/*******************************************************************************
146 * UART related constants
147 ******************************************************************************/
148#define ZYNQMP_UART0_BASE 0xFF000000
149#define ZYNQMP_UART1_BASE 0xFF001000
150
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -0700151#if ZYNQMP_CONSOLE_IS(cadence)
152# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
153#elif ZYNQMP_CONSOLE_IS(cadence1)
154# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
155#else
156# error "invalid ZYNQMP_CONSOLE"
157#endif
158
159#define PLAT_ARM_CRASH_UART_BASE ZYNQMP_UART_BASE
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800160/* impossible to call C routine how it is done now - hardcode any value */
161#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
162
163/* Must be non zero */
164#define ZYNQMP_UART_BAUDRATE 115200
165#define ARM_CONSOLE_BAUDRATE ZYNQMP_UART_BAUDRATE
166
167/* Silicon version detection */
168#define ZYNQMP_SILICON_VER_MASK 0xF000
169#define ZYNQMP_SILICON_VER_SHIFT 12
170#define ZYNQMP_CSU_VERSION_SILICON 0
171#define ZYNQMP_CSU_VERSION_EP108 1
172#define ZYNQMP_CSU_VERSION_VELOCE 2
173#define ZYNQMP_CSU_VERSION_QEMU 3
174
175#define ZYNQMP_RTL_VER_MASK 0xFF0
176#define ZYNQMP_RTL_VER_SHIFT 4
177
178#define ZYNQMP_PS_VER_MASK 0xF
179#define ZYNQMP_PS_VER_SHIFT 0
180
181#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
182#define ZYNQMP_CSU_IDCODE_OFFSET 0x40
183
184#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0
185#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
186#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
187
188#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
189#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xE << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
190#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
191#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
192#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19
193#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
194#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21
195#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
196#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
197
198#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28
199#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
200#define ZYNQMP_CSU_IDCODE_REVISION 0
201
202#define ZYNQMP_CSU_VERSION_OFFSET 0x44
203
Naga Sureshkumar Rellicf4e7142016-07-01 12:46:43 +0530204/* Access control register defines */
205#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
206#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
207
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800208#endif /* __ZYNQMP_DEF_H__ */