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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Rajan Vaja0ac2be12018-01-17 02:39:21 -08002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#ifndef __ZYNQMP_DEF_H__
8#define __ZYNQMP_DEF_H__
9
10#include <common_def.h>
11
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070012#define ZYNQMP_CONSOLE_ID_cadence 1
13#define ZYNQMP_CONSOLE_ID_cadence0 1
14#define ZYNQMP_CONSOLE_ID_cadence1 2
15#define ZYNQMP_CONSOLE_ID_dcc 3
16
17#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
18
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019/* Firmware Image Package */
20#define ZYNQMP_PRIMARY_CPU 0
21
22/* Memory location options for Shared data and TSP in ZYNQMP */
23#define ZYNQMP_IN_TRUSTED_SRAM 0
24#define ZYNQMP_IN_TRUSTED_DRAM 1
25
26/*******************************************************************************
27 * ZYNQMP memory map related constants
28 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080029/* Aggregate of all devices in the first GB */
Jolly Shah69fb5bf2018-02-07 16:25:41 -080030#define DEVICE0_BASE U(0xFF000000)
31#define DEVICE0_SIZE U(0x00E00000)
32#define DEVICE1_BASE U(0xF9000000)
33#define DEVICE1_SIZE U(0x00800000)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080034
35/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
Jolly Shah69fb5bf2018-02-07 16:25:41 -080036#define CRF_APB_BASE U(0xFD1A0000)
37#define CRF_APB_SIZE U(0x00600000)
38#define CRF_APB_CLK_BASE U(0xFD1A0020)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080039
40/* CRF registers and bitfields */
41#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
42
Jolly Shah69fb5bf2018-02-07 16:25:41 -080043#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
44#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080045
46/* CRL registers and bitfields */
Jolly Shah69fb5bf2018-02-07 16:25:41 -080047#define CRL_APB_BASE U(0xFF5E0000)
Soren Brinkmannb43d9432016-04-18 11:49:42 -070048#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080049#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
Rajan Vaja5529a012018-01-17 02:39:23 -080050#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
Jolly Shah69fb5bf2018-02-07 16:25:41 -080051#define CRL_APB_CLK_BASE U(0xFF5E0020)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080052
Jolly Shah69fb5bf2018-02-07 16:25:41 -080053#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
54#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080055
Jolly Shah69fb5bf2018-02-07 16:25:41 -080056#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080057
Jolly Shah69fb5bf2018-02-07 16:25:41 -080058#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
59#define ZYNQMP_BOOTMODE_JTAG U(0)
Soren Brinkmannb43d9432016-04-18 11:49:42 -070060
Soren Brinkmann76fcae32016-03-06 20:16:27 -080061/* system counter registers and bitfields */
62#define IOU_SCNTRS_BASE 0xFF260000
Soren Brinkmann76fcae32016-03-06 20:16:27 -080063#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
64
Soren Brinkmann76fcae32016-03-06 20:16:27 -080065/* APU registers and bitfields */
66#define APU_BASE 0xFD5C0000
67#define APU_CONFIG_0 (APU_BASE + 0x20)
68#define APU_RVBAR_L_0 (APU_BASE + 0x40)
69#define APU_RVBAR_H_0 (APU_BASE + 0x44)
70#define APU_PWRCTL (APU_BASE + 0x90)
71
72#define APU_CONFIG_0_VINITHI_SHIFT 8
73#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
74#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
75#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4
76#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
77
78/* PMU registers and bitfields */
79#define PMU_GLOBAL_BASE 0xFFD80000
80#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
Michal Simekef8f5592015-06-15 14:22:50 +020081#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080082#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
83#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
84#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
85#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120)
86
87#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
88
Soren Brinkmann76fcae32016-03-06 20:16:27 -080089/*******************************************************************************
90 * CCI-400 related constants
91 ******************************************************************************/
92#define PLAT_ARM_CCI_BASE 0xFD6E0000
93#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
94#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
95
96/*******************************************************************************
97 * GIC-400 & interrupt handling related constants
98 ******************************************************************************/
99#define BASE_GICD_BASE 0xF9010000
100#define BASE_GICC_BASE 0xF9020000
101#define BASE_GICH_BASE 0xF9040000
102#define BASE_GICV_BASE 0xF9060000
103
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800104#define ARM_IRQ_SEC_PHY_TIMER 29
105
106#define ARM_IRQ_SEC_SGI_0 8
107#define ARM_IRQ_SEC_SGI_1 9
108#define ARM_IRQ_SEC_SGI_2 10
109#define ARM_IRQ_SEC_SGI_3 11
110#define ARM_IRQ_SEC_SGI_4 12
111#define ARM_IRQ_SEC_SGI_5 13
112#define ARM_IRQ_SEC_SGI_6 14
113#define ARM_IRQ_SEC_SGI_7 15
114
115#define MAX_INTR_EL3 128
116
117/*******************************************************************************
118 * UART related constants
119 ******************************************************************************/
120#define ZYNQMP_UART0_BASE 0xFF000000
Soren Brinkmann836418d2016-05-27 08:56:53 -0700121#define ZYNQMP_UART1_BASE 0xFF010000
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800122
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -0700123#if ZYNQMP_CONSOLE_IS(cadence)
124# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
125#elif ZYNQMP_CONSOLE_IS(cadence1)
126# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
127#else
128# error "invalid ZYNQMP_CONSOLE"
129#endif
130
131#define PLAT_ARM_CRASH_UART_BASE ZYNQMP_UART_BASE
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800132/* impossible to call C routine how it is done now - hardcode any value */
133#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
134
135/* Must be non zero */
136#define ZYNQMP_UART_BAUDRATE 115200
137#define ARM_CONSOLE_BAUDRATE ZYNQMP_UART_BAUDRATE
138
139/* Silicon version detection */
140#define ZYNQMP_SILICON_VER_MASK 0xF000
141#define ZYNQMP_SILICON_VER_SHIFT 12
142#define ZYNQMP_CSU_VERSION_SILICON 0
143#define ZYNQMP_CSU_VERSION_EP108 1
144#define ZYNQMP_CSU_VERSION_VELOCE 2
145#define ZYNQMP_CSU_VERSION_QEMU 3
146
147#define ZYNQMP_RTL_VER_MASK 0xFF0
148#define ZYNQMP_RTL_VER_SHIFT 4
149
150#define ZYNQMP_PS_VER_MASK 0xF
151#define ZYNQMP_PS_VER_SHIFT 0
152
153#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
154#define ZYNQMP_CSU_IDCODE_OFFSET 0x40
155
156#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0
157#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
158#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
159
160#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
161#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xE << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
162#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
163#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
164#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19
165#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
166#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21
167#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
168#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
169
170#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28
171#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
172#define ZYNQMP_CSU_IDCODE_REVISION 0
173
174#define ZYNQMP_CSU_VERSION_OFFSET 0x44
175
Naga Sureshkumar Rellicf4e7142016-07-01 12:46:43 +0530176/* Access control register defines */
177#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
178#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
179
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800180#define IOU_SLCR_BASEADDR U(0xFF180000)
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800181
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800182#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
183#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
184#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
185#define ZYNQMP_SLSPLIT_MASK U(0x08)
186#define ZYNQMP_TCM_COMB_MASK U(0x40)
187#define ZYNQMP_SLCLAMP_MASK U(0x10)
188#define ZYNQMP_VINITHI_MASK U(0x04)
Rajan Vaja5529a012018-01-17 02:39:23 -0800189
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800190/* Tap delay bypass */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800191#define IOU_TAPDLY_BYPASS U(0XFF180390)
192#define TAP_DELAY_MASK U(0x7)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800193
194/* SGMII mode */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800195#define IOU_GEM_CTRL U(0xFF180360)
196#define IOU_GEM_CLK_CTRL U(0xFF180308)
197#define SGMII_SD_MASK U(0x3)
198#define SGMII_SD_OFFSET U(2)
199#define SGMII_PCS_SD_0 U(0x0)
200#define SGMII_PCS_SD_1 U(0x1)
201#define SGMII_PCS_SD_PHY U(0x2)
202#define GEM_SGMII_MASK U(0x4)
203#define GEM_CLK_CTRL_MASK U(0xF)
204#define GEM_CLK_CTRL_OFFSET U(5)
205#define GEM_RX_SRC_SEL_GTR U(0x1)
206#define GEM_SGMII_MODE U(0x4)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800207
208/* SD DLL reset */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800209#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
210#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
211#define ZYNQMP_SD0_DLL_RST U(0x00000004)
212#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
213#define ZYNQMP_SD1_DLL_RST U(0x00040000)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800214
215/* SD tap delay */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800216#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
217#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
218#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
219#define ZYNQMP_SD_TAP_OFFSET U(16)
220#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
221#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
222#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
223#define ZYNQMP_SD_ITAPDLYENA U(0x100)
224#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
225#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
226#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
227#define ZYNQMP_SD_OTAPDLYENA U(0x40)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800228
Rajan Vajad98455b2018-01-17 02:39:26 -0800229/* Clock control registers */
230/* Full power domain clocks */
231#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
232#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
233#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
234#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
235#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
236#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
237#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
238/* Peripheral clocks */
239#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
240#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
241#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
242#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
243#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
244#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
245#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
246#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
247#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
248#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
249#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
250#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
251#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
252#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
253#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
254#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
255
256/* Low power domain clocks */
257#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
258#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
259#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
260#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
261#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
262/* Peripheral clocks */
263#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
264#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
265#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
266#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
267#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
268#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
269#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
270#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
271#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
272#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
273#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
274#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
275#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
276#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
277#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
278#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
279#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
280#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
281#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
282#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
283#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
284#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
285#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
286#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
287#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
288#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
289#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
290#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
291#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
292#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
293#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
294#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
295#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
296#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
297#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
298#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
299#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
300#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
301#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
302#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
303#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
304#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
305
Rajan Vaja393c0a22018-01-17 02:39:27 -0800306/* Global general storage register base address */
307#define GGS_BASEADDR (0xFFD80030U)
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800308#define GGS_NUM_REGS U(4)
Rajan Vaja393c0a22018-01-17 02:39:27 -0800309
310/* Persistent global general storage register base address */
311#define PGGS_BASEADDR (0xFFD80050U)
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800312#define PGGS_NUM_REGS U(4)
Rajan Vaja393c0a22018-01-17 02:39:27 -0800313
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800314#endif /* __ZYNQMP_DEF_H__ */