commit 5529a0168b6f73c39c976874ec251b33519a7d11
author Rajan Vaja <rajan.vaja@xilinx.com> Wed Jan 17 02:39:23 2018 -0800
committer Jolly Shah <jollys@xilinx.com> Thu Mar 15 10:23:31 2018 -0700
tree 37f8ecfda56fe9e7970f2ec066a1594316027561
parent 5e139e78bddc50f62a02b4b5a6787321380b4989

zynqmp: pm: Implement IOCTL APIs for remoteproc

Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
  * Get RPU operation mode
  * Set RPU operation mode
  * Configure RPU boot address (OCM/TCM)
  * Configure TCM combined mode

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

plat/xilinx/zynqmp/zynqmp_def.h

diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index 45fa387..54036f9 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -47,7 +47,9 @@
 #define CRL_APB_RPLL_CTRL		(CRL_APB_BASE + 0x30)
 #define CRL_APB_BOOT_MODE_USER		(CRL_APB_BASE + 0x200)
 #define CRL_APB_RESET_CTRL		(CRL_APB_BASE + 0x218)
+#define CRL_APB_RST_LPD_TOP		(CRL_APB_BASE + 0x23C)
 
+#define CRL_APB_RPU_AMBA_RESET		(1 << 2)
 #define CRL_APB_RPLL_CTRL_BYPASS	(1 << 3)
 
 #define CRL_APB_RESET_CTRL_SOFT_RESET	(1 << 4)
@@ -176,4 +178,12 @@
 
 #define IOU_SLCR_BASEADDR		0xFF180000
 
+#define ZYNQMP_RPU_GLBL_CNTL			0xFF9A0000
+#define ZYNQMP_RPU0_CFG				0xFF9A0100
+#define ZYNQMP_RPU1_CFG				0xFF9A0200
+#define ZYNQMP_SLSPLIT_MASK			0x08
+#define ZYNQMP_TCM_COMB_MASK			0x40
+#define ZYNQMP_SLCLAMP_MASK			0x10
+#define ZYNQMP_VINITHI_MASK			0x04
+
 #endif /* __ZYNQMP_DEF_H__ */