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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
Sathees Balya2d0aeb02018-07-10 14:46:51 +010055 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056
David Cunado05845bf2017-12-19 16:33:25 +000057TF-A has been tested with Linaro Release 18.04.
David Cunadob2de0992017-06-29 12:01:33 +010058
Louis Mayencourt545a9ed2019-03-08 15:35:40 +000059Download and install the AArch32 or AArch64 little-endian GCC cross compiler. If
60you would like to use the latest features available, download GCC 8.2-2019.01
61compiler from `arm Developer page`_. Otherwise, the `Linaro Release Notes`_
62documents which version of the compiler to use for a given Linaro Release. Also,
63these `Linaro instructions`_ provide further guidance and a script, which can be
64used to download Linaro deliverables automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065
Roberto Vargas0489bc02018-04-16 15:43:26 +010066Optionally, TF-A can be built using clang version 4.0 or newer or Arm
67Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010068
69In addition, the following optional packages and tools may be needed:
70
Sathees Balya017a67e2018-08-17 10:22:01 +010071- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
72 Tree (FDT) source files (``.dts`` files) provided with this software. The
73 version of dtc must be 1.4.6 or above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010074
Dan Handley610e7e12018-03-01 18:44:00 +000075- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010076
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010077- To create and modify the diagram files included in the documentation, `Dia`_.
78 This tool can be found in most Linux distributions. Inkscape is needed to
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010079 generate the actual \*.png files.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010080
Dan Handley610e7e12018-03-01 18:44:00 +000081Getting the TF-A source code
82----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010083
Louis Mayencourt72ef3d42019-03-22 11:47:22 +000084Clone the repository from the Gerrit server. The project details may be found
85on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
86commit-msg hook`" clone method, which will setup the git commit hook that
87automatically generates and inserts appropriate `Change-Id:` lines in your
88commit messages.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010089
Paul Beesley8b4bdeb2019-01-21 12:06:24 +000090Checking source code style
91~~~~~~~~~~~~~~~~~~~~~~~~~~
92
93Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
94source, for submission to the project, the source must be in compliance with
95this style guide.
96
97Additional, project-specific guidelines are defined in the `Trusted Firmware-A
98Coding Guidelines`_ document.
99
100To assist with coding style compliance, the project Makefile contains two
101targets which both utilise the `checkpatch.pl` script that ships with the Linux
102source tree. The project also defines certain *checkpatch* options in the
103``.checkpatch.conf`` file in the top-level directory.
104
105**Note:** Checkpatch errors will gate upstream merging of pull requests.
106Checkpatch warnings will not gate merging but should be reviewed and fixed if
107possible.
108
109To check the entire source tree, you must first download copies of
110``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
111in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
112environment variable to point to ``checkpatch.pl`` (with the other 2 files in
113the same directory) and build the `checkcodebase` target:
114
115::
116
117 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
118
119To just check the style on the files that differ between your local branch and
120the remote master, use:
121
122::
123
124 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
125
126If you wish to check your patch against something other than the remote master,
127set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
128is set to ``origin/master``.
129
Dan Handley610e7e12018-03-01 18:44:00 +0000130Building TF-A
131-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
Dan Handley610e7e12018-03-01 18:44:00 +0000133- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
134 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100135
136 For AArch64:
137
138 ::
139
140 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
141
142 For AArch32:
143
144 ::
145
146 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
147
Roberto Vargas07b1e242018-04-23 08:38:12 +0100148 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
149 ``CC`` needs to point to the clang or armclang binary, which will
150 also select the clang or armclang assembler. Be aware that the
151 GNU linker is used by default. In case of being needed the linker
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000152 can be overridden using the ``LD`` variable. Clang linker version 6 is
Roberto Vargas07b1e242018-04-23 08:38:12 +0100153 known to work with TF-A.
154
155 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100156
Dan Handley610e7e12018-03-01 18:44:00 +0000157 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100158 to ``CC`` matches the string 'armclang'.
159
Dan Handley610e7e12018-03-01 18:44:00 +0000160 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 ::
163
164 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
165 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
166
167 Clang will be selected when the base name of the path assigned to ``CC``
168 contains the string 'clang'. This is to allow both clang and clang-X.Y
169 to work.
170
171 For AArch64 using clang:
172
173 ::
174
175 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
176 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
177
Dan Handley610e7e12018-03-01 18:44:00 +0000178- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100179
180 For AArch64:
181
182 ::
183
184 make PLAT=<platform> all
185
186 For AArch32:
187
188 ::
189
190 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
191
192 Notes:
193
194 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
195 `Summary of build options`_ for more information on available build
196 options.
197
198 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
199
200 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100201 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000202 provided by TF-A to demonstrate how PSCI Library can be integrated with
203 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
204 include other runtime services, for example Trusted OS services. A guide
205 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
206 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100207
208 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
209 image, is not compiled in by default. Refer to the
210 `Building the Test Secure Payload`_ section below.
211
212 - By default this produces a release version of the build. To produce a
213 debug version instead, refer to the "Debugging options" section below.
214
215 - The build process creates products in a ``build`` directory tree, building
216 the objects and binaries for each boot loader stage in separate
217 sub-directories. The following boot loader binary files are created
218 from the corresponding ELF files:
219
220 - ``build/<platform>/<build-type>/bl1.bin``
221 - ``build/<platform>/<build-type>/bl2.bin``
222 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
223 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
224
225 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
226 is either ``debug`` or ``release``. The actual number of images might differ
227 depending on the platform.
228
229- Build products for a specific build variant can be removed using:
230
231 ::
232
233 make DEBUG=<D> PLAT=<platform> clean
234
235 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
236
237 The build tree can be removed completely using:
238
239 ::
240
241 make realclean
242
243Summary of build options
244~~~~~~~~~~~~~~~~~~~~~~~~
245
Dan Handley610e7e12018-03-01 18:44:00 +0000246The TF-A build system supports the following build options. Unless mentioned
247otherwise, these options are expected to be specified at the build command
248line and are not to be modified in any component makefiles. Note that the
249build system doesn't track dependency for build options. Therefore, if any of
250the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100251performed.
252
253Common build options
254^^^^^^^^^^^^^^^^^^^^
255
Antonio Nino Diaz80914a82018-08-08 16:28:43 +0100256- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
257 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
258 code having a smaller resulting size.
259
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100260- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
261 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
262 directory containing the SP source, relative to the ``bl32/``; the directory
263 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
264
Dan Handley610e7e12018-03-01 18:44:00 +0000265- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
266 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
267 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100268
Dan Handley610e7e12018-03-01 18:44:00 +0000269- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
270 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
271 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
272 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100273
Dan Handley610e7e12018-03-01 18:44:00 +0000274- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
275 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
276 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100278- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000279 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
280 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100281
282- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000283 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
John Tsichritzisee10e792018-06-06 09:38:10 +0100285- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000286 BL2 at EL3 execution level.
287
John Tsichritzisee10e792018-06-06 09:38:10 +0100288- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000289 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
290 the RW sections in RAM, while leaving the RO sections in place. This option
291 enable this use-case. For now, this option is only supported when BL2_AT_EL3
292 is set to '1'.
293
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000295 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
296 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100297
298- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
299 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
300 this file name will be used to save the key.
301
302- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000303 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
304 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100305
John Tsichritzisee10e792018-06-06 09:38:10 +0100306- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100307 Trusted OS Extra1 image for the ``fip`` target.
308
John Tsichritzisee10e792018-06-06 09:38:10 +0100309- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100310 Trusted OS Extra2 image for the ``fip`` target.
311
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100312- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
313 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
314 this file name will be used to save the key.
315
316- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000317 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100318
319- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
320 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
321 this file name will be used to save the key.
322
323- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
324 compilation of each build. It must be set to a C string (including quotes
325 where applicable). Defaults to a string that contains the time and date of
326 the compilation.
327
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100328- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
Dan Handley610e7e12018-03-01 18:44:00 +0000329 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100330
331- ``CFLAGS``: Extra user options appended on the compiler's command line in
332 addition to the options set by the build system.
333
334- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
335 release several CPUs out of reset. It can take either 0 (several CPUs may be
336 brought up) or 1 (only one CPU will ever be brought up during cold reset).
337 Default is 0. If the platform always brings up a single CPU, there is no
338 need to distinguish between primary and secondary CPUs and the boot path can
339 be optimised. The ``plat_is_my_cpu_primary()`` and
340 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
341 to be implemented in this case.
342
343- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
344 register state when an unexpected exception occurs during execution of
345 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
346 this is only enabled for a debug build of the firmware.
347
348- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
349 certificate generation tool to create new keys in case no valid keys are
350 present or specified. Allowed options are '0' or '1'. Default is '1'.
351
352- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
353 the AArch32 system registers to be included when saving and restoring the
354 CPU context. The option must be set to 0 for AArch64-only platforms (that
355 is on hardware that does not implement AArch32, or at least not at EL1 and
356 higher ELs). Default value is 1.
357
358- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
359 registers to be included when saving and restoring the CPU context. Default
360 is 0.
361
Alexei Fedorov2831d582019-03-13 11:05:07 +0000362- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
363 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
364 registers to be included when saving and restoring the CPU context as
365 part of world switch. Default value is 0 and this is an experimental feature.
366 Note that Pointer Authentication is enabled for Non-secure world irrespective
367 of the value of this flag if the CPU supports it.
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000368
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369- ``DEBUG``: Chooses between a debug and release build. It can take either 0
370 (release) or 1 (debug) as values. 0 is the default.
371
John Tsichritzisee10e792018-06-06 09:38:10 +0100372- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
373 Board Boot authentication at runtime. This option is meant to be enabled only
Roberto Vargas025946a2018-09-24 17:20:48 +0100374 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
375 flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100376
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100377- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
378 the normal boot flow. It must specify the entry point address of the EL3
379 payload. Please refer to the "Booting an EL3 payload" section for more
380 details.
381
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100382- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100383 This is an optional architectural feature available on v8.4 onwards. Some
384 v8.2 implementations also implement an AMU and this option can be used to
385 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100386
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
388 are compiled out. For debug builds, this option defaults to 1, and calls to
389 ``assert()`` are left in place. For release builds, this option defaults to 0
390 and calls to ``assert()`` function are compiled out. This option can be set
391 independently of ``DEBUG``. It can also be used to hide any auxiliary code
392 that is only required for the assertion and does not fit in the assertion
393 itself.
394
Douglas Raillard77414632018-08-21 12:54:45 +0100395- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
396 dumps or not. It is supported in both AArch64 and AArch32. However, in
397 AArch32 the format of the frame records are not defined in the AAPCS and they
398 are defined by the implementation. This implementation of backtrace only
399 supports the format used by GCC when T32 interworking is disabled. For this
400 reason enabling this option in AArch32 will force the compiler to only
401 generate A32 code. This option is enabled by default only in AArch64 debug
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000402 builds, but this behaviour can be overridden in each platform's Makefile or
403 in the build command line.
Douglas Raillard77414632018-08-21 12:54:45 +0100404
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100405- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
406 feature. MPAM is an optional Armv8.4 extension that enables various memory
407 system components and resources to define partitions; software running at
408 various ELs can assign themselves to desired partition to control their
409 performance aspects.
410
411 When this option is set to ``1``, EL3 allows lower ELs to access their own
412 MPAM registers without trapping into EL3. This option doesn't make use of
413 partitioning in EL3, however. Platform initialisation code should configure
414 and use partitions in EL3 as required. This option defaults to ``0``.
415
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000416- ``ENABLE_PAUTH``: Boolean option to enable ARMv8.3 Pointer Authentication
Ambroise Vincentc3568ef2019-03-14 10:53:16 +0000417 support for TF-A BL images itself. If enabled, it is needed to use a compiler
Alexei Fedorov2831d582019-03-13 11:05:07 +0000418 that supports the option ``-msign-return-address``. This flag defaults to 0
419 and this is an experimental feature.
420 Note that Pointer Authentication is enabled for Non-secure world irrespective
421 of the value of this flag if the CPU supports it.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000422
Soby Mathew078f1a42018-08-28 11:13:55 +0100423- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
424 support within generic code in TF-A. This option is currently only supported
425 in BL31. Default is 0.
426
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100427- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
428 Measurement Framework(PMF). Default is 0.
429
430- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
431 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
432 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
433 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
434 software.
435
436- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000437 instrumentation which injects timestamp collection points into TF-A to
438 allow runtime performance to be measured. Currently, only PSCI is
439 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
440 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100441
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100442- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100443 extensions. This is an optional architectural feature for AArch64.
444 The default is 1 but is automatically disabled when the target architecture
445 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100446
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200447- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
448 Refer to the `Secure Partition Manager Design guide`_ for more details about
449 this feature. Default is 0.
450
David Cunadoce88eee2017-10-20 11:30:57 +0100451- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
452 (SVE) for the Non-secure world only. SVE is an optional architectural feature
453 for AArch64. Note that when SVE is enabled for the Non-secure world, access
454 to SIMD and floating-point functionality from the Secure world is disabled.
455 This is to avoid corruption of the Non-secure world data in the Z-registers
456 which are aliased by the SIMD and FP registers. The build option is not
457 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
458 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
459 1. The default is 1 but is automatically disabled when the target
460 architecture is AArch32.
461
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100462- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
463 checks in GCC. Allowed values are "all", "strong" and "0" (default).
464 "strong" is the recommended stack protection level if this feature is
465 desired. 0 disables the stack protection. For all values other than 0, the
466 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
467 The value is passed as the last component of the option
468 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
469
470- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
471 deprecated platform APIs, helper functions or drivers within Trusted
472 Firmware as error. It can take the value 1 (flag the use of deprecated
473 APIs as error) or 0. The default is 0.
474
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100475- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
476 targeted at EL3. When set ``0`` (default), no exceptions are expected or
477 handled at EL3, and a panic will result. This is supported only for AArch64
478 builds.
479
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000480- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000481 injection from lower ELs, and this build option enables lower ELs to use
482 Error Records accessed via System Registers to inject faults. This is
483 applicable only to AArch64 builds.
484
485 This feature is intended for testing purposes only, and is advisable to keep
486 disabled for production images.
487
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100488- ``FIP_NAME``: This is an optional build option which specifies the FIP
489 filename for the ``fip`` target. Default is ``fip.bin``.
490
491- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
492 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
493
494- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
495 tool to create certificates as per the Chain of Trust described in
496 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100497 include the certificates in the FIP and FWU_FIP. Default value is '0'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100498
499 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
500 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
501 the corresponding certificates, and to include those certificates in the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100502 FIP and FWU_FIP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100503
504 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
505 images will not include support for Trusted Board Boot. The FIP will still
506 include the corresponding certificates. This FIP can be used to verify the
507 Chain of Trust on the host machine through other mechanisms.
508
509 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100510 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511 will not include the corresponding certificates, causing a boot failure.
512
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100513- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
514 inherent support for specific EL3 type interrupts. Setting this build option
515 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
516 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
517 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
518 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
519 the Secure Payload interrupts needs to be synchronously handed over to Secure
520 EL1 for handling. The default value of this option is ``0``, which means the
521 Group 0 interrupts are assumed to be handled by Secure EL1.
522
523 .. __: `platform-interrupt-controller-API.rst`
524 .. __: `interrupt-framework-design.rst`
525
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700526- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
527 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
528 ``0`` (default), these exceptions will be trapped in the current exception
529 level (or in EL1 if the current exception level is EL0).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100530
Dan Handley610e7e12018-03-01 18:44:00 +0000531- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100532 software operations are required for CPUs to enter and exit coherency.
533 However, there exists newer systems where CPUs' entry to and exit from
534 coherency is managed in hardware. Such systems require software to only
535 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000536 active software management. In such systems, this boolean option enables
537 TF-A to carry out build and run-time optimizations during boot and power
538 management operations. This option defaults to 0 and if it is enabled,
539 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100540
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100541 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
542 translation library (xlat tables v2) must be used; version 1 of translation
543 library is not supported.
544
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100545- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
546 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
547 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
548 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
549 images.
550
Soby Mathew13b16052017-08-31 11:49:32 +0100551- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
552 used for generating the PKCS keys and subsequent signing of the certificate.
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000553 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
554 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
555 compliant and is retained only for compatibility. The default value of this
556 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100557
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800558- ``HASH_ALG``: This build flag enables the user to select the secure hash
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000559 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800560 The default value of this flag is ``sha256``.
561
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100562- ``LDFLAGS``: Extra user options appended to the linkers' command line in
563 addition to the one set by the build system.
564
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100565- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
566 output compiled into the build. This should be one of the following:
567
568 ::
569
570 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100571 10 (LOG_LEVEL_ERROR)
572 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100573 30 (LOG_LEVEL_WARNING)
574 40 (LOG_LEVEL_INFO)
575 50 (LOG_LEVEL_VERBOSE)
576
John Tsichritzis35006c42018-10-05 12:02:29 +0100577 All log output up to and including the selected log level is compiled into
578 the build. The default value is 40 in debug builds and 20 in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100579
580- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
581 specifies the file that contains the Non-Trusted World private key in PEM
582 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
583
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100584- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100585 optional. It is only needed if the platform makefile specifies that it
586 is required in order to build the ``fwu_fip`` target.
587
588- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
589 contents upon world switch. It can take either 0 (don't save and restore) or
590 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
591 wants the timer registers to be saved and restored.
592
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +0100593- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800594 for the BL image. It can be either 0 (include) or 1 (remove). The default
595 value is 0.
596
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100597- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
598 the underlying hardware is not a full PL011 UART but a minimally compliant
599 generic UART, which is a subset of the PL011. The driver will not access
600 any register that is not part of the SBSA generic UART specification.
601 Default value is 0 (a full PL011 compliant UART is present).
602
Dan Handley610e7e12018-03-01 18:44:00 +0000603- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
604 must be subdirectory of any depth under ``plat/``, and must contain a
605 platform makefile named ``platform.mk``. For example, to build TF-A for the
606 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100607
608- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
609 instead of the normal boot flow. When defined, it must specify the entry
610 point address for the preloaded BL33 image. This option is incompatible with
611 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
612 over ``PRELOADED_BL33_BASE``.
613
614- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
615 vector address can be programmed or is fixed on the platform. It can take
616 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
617 programmable reset address, it is expected that a CPU will start executing
618 code directly at the right address, both on a cold and warm reset. In this
619 case, there is no need to identify the entrypoint on boot and the boot path
620 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
621 does not need to be implemented in this case.
622
623- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000624 possible for the PSCI power-state parameter: original and extended State-ID
625 formats. This flag if set to 1, configures the generic PSCI layer to use the
626 extended format. The default value of this flag is 0, which means by default
627 the original power-state format is used by the PSCI implementation. This flag
628 should be specified by the platform makefile and it governs the return value
629 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
630 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
631 set to 1 as well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100632
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100633- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
634 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
635 or later CPUs.
636
637 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
638 set to ``1``.
639
640 This option is disabled by default.
641
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100642- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
643 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
644 entrypoint) or 1 (CPU reset to BL31 entrypoint).
645 The default value is 0.
646
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100647- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
648 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
Dan Handley610e7e12018-03-01 18:44:00 +0000649 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100650 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100651
652- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
653 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
654 file name will be used to save the key.
655
656- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
657 certificate generation tool to save the keys used to establish the Chain of
658 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
659
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100660- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
661 If a SCP_BL2 image is present then this option must be passed for the ``fip``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100662 target.
663
664- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100665 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100666 this file name will be used to save the key.
667
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100668- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100669 optional. It is only needed if the platform makefile specifies that it
670 is required in order to build the ``fwu_fip`` target.
671
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100672- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
673 Delegated Exception Interface to BL31 image. This defaults to ``0``.
674
675 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
676 set to ``1``.
677
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100678- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
679 isolated on separate memory pages. This is a trade-off between security and
680 memory usage. See "Isolating code and read-only data on separate memory
681 pages" section in `Firmware Design`_. This flag is disabled by default and
682 affects all BL images.
683
Dan Handley610e7e12018-03-01 18:44:00 +0000684- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
685 This build option is only valid if ``ARCH=aarch64``. The value should be
686 the path to the directory containing the SPD source, relative to
687 ``services/spd/``; the directory is expected to contain a makefile called
688 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100689
690- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
691 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
692 execution in BL1 just before handing over to BL31. At this point, all
693 firmware images have been loaded in memory, and the MMU and caches are
694 turned off. Refer to the "Debugging options" section for more details.
695
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100696- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200697 secure interrupts (caught through the FIQ line). Platforms can enable
698 this directive if they need to handle such interruption. When enabled,
699 the FIQ are handled in monitor mode and non secure world is not allowed
700 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
701 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
702
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100703- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
704 Boot feature. When set to '1', BL1 and BL2 images include support to load
705 and verify the certificates and images in a FIP, and BL1 includes support
706 for the Firmware Update. The default value is '0'. Generation and inclusion
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100707 of certificates in the FIP and FWU_FIP depends upon the value of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100708 ``GENERATE_COT`` option.
709
710 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
711 already exist in disk, they will be overwritten without further notice.
712
713- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
714 specifies the file that contains the Trusted World private key in PEM
715 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
716
717- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
718 synchronous, (see "Initializing a BL32 Image" section in
719 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
720 synchronous method) or 1 (BL32 is initialized using asynchronous method).
721 Default is 0.
722
723- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
724 routing model which routes non-secure interrupts asynchronously from TSP
725 to EL3 causing immediate preemption of TSP. The EL3 is responsible
726 for saving and restoring the TSP context in this routing model. The
727 default routing model (when the value is 0) is to route non-secure
728 interrupts to TSP allowing it to save its context and hand over
729 synchronously to EL3 via an SMC.
730
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000731 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
732 must also be set to ``1``.
733
Varun Wadekar4d034c52019-01-11 14:47:48 -0800734- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
735 linker. When the ``LINKER`` build variable points to the armlink linker,
736 this flag is enabled automatically. To enable support for armlink, platforms
737 will have to provide a scatter file for the BL image. Currently, Tegra
738 platforms use the armlink support to compile BL3-1 images.
739
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100740- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
741 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000742 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100743 (Coherent memory region is included) or 0 (Coherent memory region is
744 excluded). Default is 1.
745
John Tsichritzis2e42b622019-03-19 12:12:55 +0000746- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
747 This feature creates a library of functions to be placed in ROM and thus
748 reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
749 is 0.
750
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100751- ``V``: Verbose build. If assigned anything other than 0, the build commands
752 are printed. Default is 0.
753
Dan Handley610e7e12018-03-01 18:44:00 +0000754- ``VERSION_STRING``: String used in the log output for each TF-A image.
755 Defaults to a string formed by concatenating the version number, build type
756 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100757
758- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
759 the CPU after warm boot. This is applicable for platforms which do not
760 require interconnect programming to enable cache coherency (eg: single
761 cluster platforms). If this option is enabled, then warm boot path
762 enables D-caches immediately after enabling MMU. This option defaults to 0.
763
Dan Handley610e7e12018-03-01 18:44:00 +0000764Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100765^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
766
767- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
768 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
769 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
770 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
771 flag.
772
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
774 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
775 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
776 match the frame used by the Non-Secure image (normally the Linux kernel).
777 Default is true (access to the frame is allowed).
778
779- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000780 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100781 an error is encountered during the boot process (for example, when an image
782 could not be loaded or authenticated). The watchdog is enabled in the early
783 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
784 Trusted Watchdog may be disabled at build time for testing or development
785 purposes.
786
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100787- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
788 have specific values at boot. This boolean option allows the Trusted Firmware
789 to have a Linux kernel image as BL33 by preparing the registers to these
Manish Pandey37c4ec22018-11-02 13:28:25 +0000790 values before jumping to BL33. This option defaults to 0 (disabled). For
791 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
792 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
793 to the location of a device tree blob (DTB) already loaded in memory. The
794 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
795 option.
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100796
Sandrine Bailleux281f8f72019-01-31 13:12:41 +0100797- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
798 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
799 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
800 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
801 this flag is 0. Note that this option is not used on FVP platforms.
802
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100803- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
804 for the construction of composite state-ID in the power-state parameter.
805 The existing PSCI clients currently do not support this encoding of
806 State-ID yet. Hence this flag is used to configure whether to use the
807 recommended State-ID encoding or not. The default value of this flag is 0,
808 in which case the platform is configured to expect NULL in the State-ID
809 field of power-state parameter.
810
811- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
812 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000813 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100814 must be specified using the ``ROT_KEY`` option when building the Trusted
815 Firmware. This private key will be used by the certificate generation tool
816 to sign the BL2 and Trusted Key certificates. Available options for
817 ``ARM_ROTPK_LOCATION`` are:
818
819 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
820 registers. The private key corresponding to this ROTPK hash is not
821 currently available.
822 - ``devel_rsa`` : return a development public key hash embedded in the BL1
823 and BL2 binaries. This hash has been obtained from the RSA public key
824 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
825 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
826 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800827 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
828 and BL2 binaries. This hash has been obtained from the ECDSA public key
829 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
830 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
831 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100832
833- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
834
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800835 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100836 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100837 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
838 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100839
Dan Handley610e7e12018-03-01 18:44:00 +0000840- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
841 of the translation tables library instead of version 2. It is set to 0 by
842 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100843
Dan Handley610e7e12018-03-01 18:44:00 +0000844- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
845 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
846 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100847 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
848
Dan Handley610e7e12018-03-01 18:44:00 +0000849For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100850map is explained in the `Firmware Design`_.
851
Dan Handley610e7e12018-03-01 18:44:00 +0000852Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100853^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
854
855- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
856 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
857 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000858 TF-A no longer supports earlier SCP versions. If this option is set to 1
859 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100860
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100861- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
862 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100863 during boot. Default is 1.
864
Soby Mathew1ced6b82017-06-12 12:37:10 +0100865- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
866 instead of SCPI/BOM driver for communicating with the SCP during power
867 management operations and for SCP RAM Firmware transfer. If this option
868 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100869
Dan Handley610e7e12018-03-01 18:44:00 +0000870Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100871^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
872
873- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000874 build the topology tree within TF-A. By default TF-A is configured for dual
875 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100876
877- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
878 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
879 explained in the options below:
880
881 - ``FVP_CCI`` : The CCI driver is selected. This is the default
882 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
883 - ``FVP_CCN`` : The CCN driver is selected. This is the default
884 if ``FVP_CLUSTER_COUNT`` > 2.
885
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000886- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
887 a single cluster. This option defaults to 4.
888
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000889- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
890 in the system. This option defaults to 1. Note that the build option
891 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
892
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100893- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
894
895 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
896 - ``FVP_GICV2`` : The GICv2 only driver is selected
897 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100898
899- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
900 for functions that wait for an arbitrary time length (udelay and mdelay).
901 The default value is 0.
902
Soby Mathewb1bf0442018-02-16 14:52:52 +0000903- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
904 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
905 details on HW_CONFIG. By default, this is initialized to a sensible DTS
906 file in ``fdts/`` folder depending on other build options. But some cases,
907 like shifted affinity format for MPIDR, cannot be detected at build time
908 and this option is needed to specify the appropriate DTS file.
909
910- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
911 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
912 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
913 HW_CONFIG blob instead of the DTS file. This option is useful to override
914 the default HW_CONFIG selected by the build system.
915
Summer Qin13b95c22018-03-02 15:51:14 +0800916ARM JUNO platform specific build options
917^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
918
919- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
920 Media Protection (TZ-MP1). Default value of this flag is 0.
921
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100922Debugging options
923~~~~~~~~~~~~~~~~~
924
925To compile a debug version and make the build more verbose use
926
927::
928
929 make PLAT=<platform> DEBUG=1 V=1 all
930
931AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
932example DS-5) might not support this and may need an older version of DWARF
933symbols to be emitted by GCC. This can be achieved by using the
934``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
935version to 2 is recommended for DS-5 versions older than 5.16.
936
937When debugging logic problems it might also be useful to disable all compiler
938optimizations by using ``-O0``.
939
940NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000941might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100942platforms** section in the `Firmware Design`_).
943
944Extra debug options can be passed to the build system by setting ``CFLAGS`` or
945``LDFLAGS``:
946
947.. code:: makefile
948
949 CFLAGS='-O0 -gdwarf-2' \
950 make PLAT=<platform> DEBUG=1 V=1 all
951
952Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
953ignored as the linker is called directly.
954
955It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000956post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
957``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100958section. In this case, the developer may take control of the target using a
959debugger when indicated by the console output. When using DS-5, the following
960commands can be used:
961
962::
963
964 # Stop target execution
965 interrupt
966
967 #
968 # Prepare your debugging environment, e.g. set breakpoints
969 #
970
971 # Jump over the debug loop
972 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
973
974 # Resume execution
975 continue
976
977Building the Test Secure Payload
978~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
979
980The TSP is coupled with a companion runtime service in the BL31 firmware,
981called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
982must be recompiled as well. For more information on SPs and SPDs, see the
983`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
984
Dan Handley610e7e12018-03-01 18:44:00 +0000985First clean the TF-A build directory to get rid of any previous BL31 binary.
986Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100987
988::
989
990 make PLAT=<platform> SPD=tspd all
991
992An additional boot loader binary file is created in the ``build`` directory:
993
994::
995
996 build/<platform>/<build-type>/bl32.bin
997
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100998
999Building and using the FIP tool
1000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1001
Dan Handley610e7e12018-03-01 18:44:00 +00001002Firmware Image Package (FIP) is a packaging format used by TF-A to package
1003firmware images in a single binary. The number and type of images that should
1004be packed in a FIP is platform specific and may include TF-A images and other
1005firmware images required by the platform. For example, most platforms require
1006a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1007U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001008
Dan Handley610e7e12018-03-01 18:44:00 +00001009The TF-A build system provides the make target ``fip`` to create a FIP file
1010for the specified platform using the FIP creation tool included in the TF-A
1011project. Examples below show how to build a FIP file for FVP, packaging TF-A
1012and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001013
1014For AArch64:
1015
1016::
1017
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001018 make PLAT=fvp BL33=<path-to>/bl33.bin fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001019
1020For AArch32:
1021
1022::
1023
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001024 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001025
1026The resulting FIP may be found in:
1027
1028::
1029
1030 build/fvp/<build-type>/fip.bin
1031
1032For advanced operations on FIP files, it is also possible to independently build
1033the tool and create or modify FIPs using this tool. To do this, follow these
1034steps:
1035
1036It is recommended to remove old artifacts before building the tool:
1037
1038::
1039
1040 make -C tools/fiptool clean
1041
1042Build the tool:
1043
1044::
1045
1046 make [DEBUG=1] [V=1] fiptool
1047
1048The tool binary can be located in:
1049
1050::
1051
1052 ./tools/fiptool/fiptool
1053
Alexei Fedorov2831d582019-03-13 11:05:07 +00001054Invoking the tool with ``help`` will print a help message with all available
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001055options.
1056
1057Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1058
1059::
1060
1061 ./tools/fiptool/fiptool create \
1062 --tb-fw build/<platform>/<build-type>/bl2.bin \
1063 --soc-fw build/<platform>/<build-type>/bl31.bin \
1064 fip.bin
1065
1066Example 2: view the contents of an existing Firmware package:
1067
1068::
1069
1070 ./tools/fiptool/fiptool info <path-to>/fip.bin
1071
1072Example 3: update the entries of an existing Firmware package:
1073
1074::
1075
1076 # Change the BL2 from Debug to Release version
1077 ./tools/fiptool/fiptool update \
1078 --tb-fw build/<platform>/release/bl2.bin \
1079 build/<platform>/debug/fip.bin
1080
1081Example 4: unpack all entries from an existing Firmware package:
1082
1083::
1084
1085 # Images will be unpacked to the working directory
1086 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1087
1088Example 5: remove an entry from an existing Firmware package:
1089
1090::
1091
1092 ./tools/fiptool/fiptool remove \
1093 --tb-fw build/<platform>/debug/fip.bin
1094
1095Note that if the destination FIP file exists, the create, update and
1096remove operations will automatically overwrite it.
1097
1098The unpack operation will fail if the images already exist at the
1099destination. In that case, use -f or --force to continue.
1100
1101More information about FIP can be found in the `Firmware Design`_ document.
1102
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001103Building FIP images with support for Trusted Board Boot
1104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1105
1106Trusted Board Boot primarily consists of the following two features:
1107
1108- Image Authentication, described in `Trusted Board Boot`_, and
1109- Firmware Update, described in `Firmware Update`_
1110
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001111The following steps should be followed to build FIP and (optionally) FWU_FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001112images with support for these features:
1113
1114#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1115 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001116 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001117 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001118 information. The latest version of TF-A is tested with tag
John Tsichritzisff4f9912019-03-12 16:11:17 +00001119 ``mbedtls-2.16.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001120
1121 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1122 source files the modules depend upon.
1123 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1124 options required to build the mbed TLS sources.
1125
1126 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001127 license. Using mbed TLS source code will affect the licensing of TF-A
1128 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001129
1130#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001131 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001132
1133 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1134 - ``TRUSTED_BOARD_BOOT=1``
1135 - ``GENERATE_COT=1``
1136
Dan Handley610e7e12018-03-01 18:44:00 +00001137 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001138 specified at build time. Two locations are currently supported (see
1139 ``ARM_ROTPK_LOCATION`` build option):
1140
1141 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1142 root-key storage registers present in the platform. On Juno, this
1143 registers are read-only. On FVP Base and Cortex models, the registers
1144 are read-only, but the value can be specified using the command line
1145 option ``bp.trusted_key_storage.public_key`` when launching the model.
1146 On both Juno and FVP models, the default value corresponds to an
1147 ECDSA-SECP256R1 public key hash, whose private part is not currently
1148 available.
1149
1150 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001151 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001152 found in ``plat/arm/board/common/rotpk``.
1153
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001154 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001155 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001156 found in ``plat/arm/board/common/rotpk``.
1157
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001158 Example of command line using RSA development keys:
1159
1160 ::
1161
1162 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1163 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1164 ARM_ROTPK_LOCATION=devel_rsa \
1165 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1166 BL33=<path-to>/<bl33_image> \
1167 all fip
1168
1169 The result of this build will be the bl1.bin and the fip.bin binaries. This
1170 FIP will include the certificates corresponding to the Chain of Trust
1171 described in the TBBR-client document. These certificates can also be found
1172 in the output build directory.
1173
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001174#. The optional FWU_FIP contains any additional images to be loaded from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001175 Non-Volatile storage during the `Firmware Update`_ process. To build the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001176 FWU_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001177 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001178
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001179 - NS_BL2U. The AP non-secure Firmware Updater image.
1180 - SCP_BL2U. The SCP Firmware Update Configuration image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001181
1182 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1183 targets using RSA development:
1184
1185 ::
1186
1187 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1188 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1189 ARM_ROTPK_LOCATION=devel_rsa \
1190 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1191 BL33=<path-to>/<bl33_image> \
1192 SCP_BL2=<path-to>/<scp_bl2_image> \
1193 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1194 NS_BL2U=<path-to>/<ns_bl2u_image> \
1195 all fip fwu_fip
1196
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001197 Note: The BL2U image will be built by default and added to the FWU_FIP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001198 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1199 to the command line above.
1200
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001201 Note: Building and installing the non-secure and SCP FWU images (NS_BL1U,
1202 NS_BL2U and SCP_BL2U) is outside the scope of this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001203
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001204 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1205 Both the FIP and FWU_FIP will include the certificates corresponding to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001206 Chain of Trust described in the TBBR-client document. These certificates
1207 can also be found in the output build directory.
1208
1209Building the Certificate Generation Tool
1210~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1211
Dan Handley610e7e12018-03-01 18:44:00 +00001212The ``cert_create`` tool is built as part of the TF-A build process when the
1213``fip`` make target is specified and TBB is enabled (as described in the
1214previous section), but it can also be built separately with the following
1215command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001216
1217::
1218
1219 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1220
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001221For platforms that require their own IDs in certificate files, the generic
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001222'cert_create' tool can be built with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001223
1224::
1225
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001226 make USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001227
1228``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1229verbose. The following command should be used to obtain help about the tool:
1230
1231::
1232
1233 ./tools/cert_create/cert_create -h
1234
1235Building a FIP for Juno and FVP
1236-------------------------------
1237
1238This section provides Juno and FVP specific instructions to build Trusted
1239Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001240a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001241
David Cunadob2de0992017-06-29 12:01:33 +01001242Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1243onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001244
Joel Huttonfe027712018-03-19 11:59:57 +00001245Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001246different one. Mixing instructions for different platforms may result in
1247corrupted binaries.
1248
Joel Huttonfe027712018-03-19 11:59:57 +00001249Note: The uboot image downloaded by the Linaro workspace script does not always
1250match the uboot image packaged as BL33 in the corresponding fip file. It is
1251recommended to use the version that is packaged in the fip file using the
1252instructions below.
1253
Soby Mathewecd94ad2018-05-09 13:59:29 +01001254Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1255by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1256section for more info on selecting the right FDT to use.
1257
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001258#. Clean the working directory
1259
1260 ::
1261
1262 make realclean
1263
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001264#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001265
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001266 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001267 package included in the Linaro release:
1268
1269 ::
1270
1271 # Build the fiptool
1272 make [DEBUG=1] [V=1] fiptool
1273
1274 # Unpack firmware images from Linaro FIP
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001275 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001276
1277 The unpack operation will result in a set of binary images extracted to the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001278 current working directory. The SCP_BL2 image corresponds to
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001279 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001280
Joel Huttonfe027712018-03-19 11:59:57 +00001281 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001282 exist in the current directory. If that is the case, either delete those
1283 files or use the ``--force`` option to overwrite.
1284
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001285 Note: For AArch32, the instructions below assume that nt-fw.bin is a normal
1286 world boot loader that supports AArch32.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001287
Dan Handley610e7e12018-03-01 18:44:00 +00001288#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001289
1290 ::
1291
1292 # AArch64
1293 make PLAT=fvp BL33=nt-fw.bin all fip
1294
1295 # AArch32
1296 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1297
Dan Handley610e7e12018-03-01 18:44:00 +00001298#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001299
1300 For AArch64:
1301
1302 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1303 as a build parameter.
1304
1305 ::
1306
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001307 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001308
1309 For AArch32:
1310
1311 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1312 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1313 separately for AArch32.
1314
1315 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1316 to the AArch32 Linaro cross compiler.
1317
1318 ::
1319
1320 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1321
1322 - Build BL32 in AArch32.
1323
1324 ::
1325
1326 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1327 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1328
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001329 - Save ``bl32.bin`` to a temporary location and clean the build products.
1330
1331 ::
1332
1333 cp <path-to-build>/bl32.bin <path-to-temporary>
1334 make realclean
1335
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001336 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1337 must point to the AArch64 Linaro cross compiler.
1338
1339 ::
1340
1341 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1342
1343 - The following parameters should be used to build BL1 and BL2 in AArch64
1344 and point to the BL32 file.
1345
1346 ::
1347
Soby Mathew97b1bff2018-09-27 16:46:41 +01001348 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001349 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1350 BL32=<path-to-temporary>/bl32.bin all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001351
1352The resulting BL1 and FIP images may be found in:
1353
1354::
1355
1356 # Juno
1357 ./build/juno/release/bl1.bin
1358 ./build/juno/release/fip.bin
1359
1360 # FVP
1361 ./build/fvp/release/bl1.bin
1362 ./build/fvp/release/fip.bin
1363
Roberto Vargas096f3a02017-10-17 10:19:00 +01001364
1365Booting Firmware Update images
1366-------------------------------------
1367
1368When Firmware Update (FWU) is enabled there are at least 2 new images
1369that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1370FWU FIP.
1371
1372Juno
1373~~~~
1374
1375The new images must be programmed in flash memory by adding
1376an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1377on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1378Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1379programming" for more information. User should ensure these do not
1380overlap with any other entries in the file.
1381
1382::
1383
1384 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1385 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1386 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1387 NOR10LOAD: 00000000 ;Image Load Address
1388 NOR10ENTRY: 00000000 ;Image Entry Point
1389
1390 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1391 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1392 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1393 NOR11LOAD: 00000000 ;Image Load Address
1394
1395The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1396In the same way, the address ns_bl2u_base_address is the value of
1397NS_BL2U_BASE - 0x8000000.
1398
1399FVP
1400~~~
1401
1402The additional fip images must be loaded with:
1403
1404::
1405
1406 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1407 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1408
1409The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1410In the same way, the address ns_bl2u_base_address is the value of
1411NS_BL2U_BASE.
1412
1413
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001414EL3 payloads alternative boot flow
1415----------------------------------
1416
1417On a pre-production system, the ability to execute arbitrary, bare-metal code at
1418the highest exception level is required. It allows full, direct access to the
1419hardware, for example to run silicon soak tests.
1420
1421Although it is possible to implement some baremetal secure firmware from
1422scratch, this is a complex task on some platforms, depending on the level of
1423configuration required to put the system in the expected state.
1424
1425Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001426``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1427boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1428other BL images and passing control to BL31. It reduces the complexity of
1429developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001430
1431- putting the system into a known architectural state;
1432- taking care of platform secure world initialization;
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001433- loading the SCP_BL2 image if required by the platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001434
Dan Handley610e7e12018-03-01 18:44:00 +00001435When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001436TrustZone controller is simplified such that only region 0 is enabled and is
1437configured to permit secure access only. This gives full access to the whole
1438DRAM to the EL3 payload.
1439
1440The system is left in the same state as when entering BL31 in the default boot
1441flow. In particular:
1442
1443- Running in EL3;
1444- Current state is AArch64;
1445- Little-endian data access;
1446- All exceptions disabled;
1447- MMU disabled;
1448- Caches disabled.
1449
1450Booting an EL3 payload
1451~~~~~~~~~~~~~~~~~~~~~~
1452
1453The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001454not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001455
1456- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1457 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001458 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001459
1460- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1461 run-time.
1462
1463To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1464used. The infinite loop that it introduces in BL1 stops execution at the right
1465moment for a debugger to take control of the target and load the payload (for
1466example, over JTAG).
1467
1468It is expected that this loading method will work in most cases, as a debugger
1469connection is usually available in a pre-production system. The user is free to
1470use any other platform-specific mechanism to load the EL3 payload, though.
1471
1472Booting an EL3 payload on FVP
1473^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1474
1475The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1476the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1477is undefined on the FVP platform and the FVP platform code doesn't clear it.
1478Therefore, one must modify the way the model is normally invoked in order to
1479clear the mailbox at start-up.
1480
1481One way to do that is to create an 8-byte file containing all zero bytes using
1482the following command:
1483
1484::
1485
1486 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1487
1488and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1489using the following model parameters:
1490
1491::
1492
1493 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1494 --data=mailbox.dat@0x04000000 [Foundation FVP]
1495
1496To provide the model with the EL3 payload image, the following methods may be
1497used:
1498
1499#. If the EL3 payload is able to execute in place, it may be programmed into
1500 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1501 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1502 used for the FIP):
1503
1504 ::
1505
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001506 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001507
1508 On Foundation FVP, there is no flash loader component and the EL3 payload
1509 may be programmed anywhere in flash using method 3 below.
1510
1511#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1512 command may be used to load the EL3 payload ELF image over JTAG:
1513
1514 ::
1515
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001516 load <path-to>/el3-payload.elf
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001517
1518#. The EL3 payload may be pre-loaded in volatile memory using the following
1519 model parameters:
1520
1521 ::
1522
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001523 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1524 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001525
1526 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001527 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001528
1529Booting an EL3 payload on Juno
1530^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1531
1532If the EL3 payload is able to execute in place, it may be programmed in flash
1533memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1534on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1535Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1536programming" for more information.
1537
1538Alternatively, the same DS-5 command mentioned in the FVP section above can
1539be used to load the EL3 payload's ELF file over JTAG on Juno.
1540
1541Preloaded BL33 alternative boot flow
1542------------------------------------
1543
1544Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001545on TF-A to load it. This may simplify packaging of the normal world code and
1546improve performance in a development environment. When secure world cold boot
1547is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001548
1549For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001550used when compiling TF-A. For example, the following command will create a FIP
1551without a BL33 and prepare to jump to a BL33 image loaded at address
15520x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001553
1554::
1555
1556 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1557
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001558Boot of a preloaded kernel image on Base FVP
1559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001560
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001561The following example uses a simplified boot flow by directly jumping from the
1562TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1563useful if both the kernel and the device tree blob (DTB) are already present in
1564memory (like in FVP).
1565
1566For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1567address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001568
1569::
1570
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001571 CROSS_COMPILE=aarch64-linux-gnu- \
1572 make PLAT=fvp DEBUG=1 \
1573 RESET_TO_BL31=1 \
1574 ARM_LINUX_KERNEL_AS_BL33=1 \
1575 PRELOADED_BL33_BASE=0x80080000 \
1576 ARM_PRELOADED_DTB_BASE=0x82000000 \
1577 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001578
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001579Now, it is needed to modify the DTB so that the kernel knows the address of the
1580ramdisk. The following script generates a patched DTB from the provided one,
1581assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1582script assumes that the user is using a ramdisk image prepared for U-Boot, like
1583the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1584offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001585
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001586.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001587
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001588 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001589
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001590 # Path to the input DTB
1591 KERNEL_DTB=<path-to>/<fdt>
1592 # Path to the output DTB
1593 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1594 # Base address of the ramdisk
1595 INITRD_BASE=0x84000000
1596 # Path to the ramdisk
1597 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001598
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001599 # Skip uboot header (64 bytes)
1600 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1601 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1602 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1603
1604 CHOSEN_NODE=$(echo \
1605 "/ { \
1606 chosen { \
1607 linux,initrd-start = <${INITRD_START}>; \
1608 linux,initrd-end = <${INITRD_END}>; \
1609 }; \
1610 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001611
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001612 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1613 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001614
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001615And the FVP binary can be run with the following command:
1616
1617::
1618
1619 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1620 -C pctl.startup=0.0.0.0 \
1621 -C bp.secure_memory=1 \
1622 -C cluster0.NUM_CORES=4 \
1623 -C cluster1.NUM_CORES=4 \
1624 -C cache_state_modelled=1 \
1625 -C cluster0.cpu0.RVBAR=0x04020000 \
1626 -C cluster0.cpu1.RVBAR=0x04020000 \
1627 -C cluster0.cpu2.RVBAR=0x04020000 \
1628 -C cluster0.cpu3.RVBAR=0x04020000 \
1629 -C cluster1.cpu0.RVBAR=0x04020000 \
1630 -C cluster1.cpu1.RVBAR=0x04020000 \
1631 -C cluster1.cpu2.RVBAR=0x04020000 \
1632 -C cluster1.cpu3.RVBAR=0x04020000 \
1633 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1634 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1635 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1636 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1637
1638Boot of a preloaded kernel image on Juno
1639~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001640
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001641The Trusted Firmware must be compiled in a similar way as for FVP explained
1642above. The process to load binaries to memory is the one explained in
1643`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001644
1645Running the software on FVP
1646---------------------------
1647
David Cunado7c032642018-03-12 18:47:05 +00001648The latest version of the AArch64 build of TF-A has been tested on the following
1649Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1650(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001651
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001652The FVP models used are Version 11.5 Build 33, unless otherwise stated.
David Cunado124415e2017-06-27 17:31:12 +01001653
David Cunado05845bf2017-12-19 16:33:25 +00001654- ``FVP_Base_AEMv8A-AEMv8A``
1655- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
David Cunado05845bf2017-12-19 16:33:25 +00001656- ``FVP_Base_RevC-2xAEMv8A``
1657- ``FVP_Base_Cortex-A32x4``
David Cunado124415e2017-06-27 17:31:12 +01001658- ``FVP_Base_Cortex-A35x4``
1659- ``FVP_Base_Cortex-A53x4``
David Cunado05845bf2017-12-19 16:33:25 +00001660- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1661- ``FVP_Base_Cortex-A55x4``
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001662- ``FVP_Base_Cortex-A57x1-A53x1``
1663- ``FVP_Base_Cortex-A57x2-A53x4``
David Cunado124415e2017-06-27 17:31:12 +01001664- ``FVP_Base_Cortex-A57x4-A53x4``
1665- ``FVP_Base_Cortex-A57x4``
1666- ``FVP_Base_Cortex-A72x4-A53x4``
1667- ``FVP_Base_Cortex-A72x4``
1668- ``FVP_Base_Cortex-A73x4-A53x4``
1669- ``FVP_Base_Cortex-A73x4``
David Cunado05845bf2017-12-19 16:33:25 +00001670- ``FVP_Base_Cortex-A75x4``
1671- ``FVP_Base_Cortex-A76x4``
Alexei Fedorov48009432019-04-04 16:26:34 +01001672- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
1673- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001674- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001675- ``FVP_Base_Deimos``
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001676- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001677- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1678- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
1679- ``FVP_RD_N1Edge`` (Version 11.3 build 42)
David Cunado05845bf2017-12-19 16:33:25 +00001680- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001681
1682The latest version of the AArch32 build of TF-A has been tested on the following
1683Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1684(64-bit host machine only).
1685
1686- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001687- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001688
David Cunado7c032642018-03-12 18:47:05 +00001689NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1690is not compatible with legacy GIC configurations. Therefore this FVP does not
1691support these legacy GIC configurations.
1692
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693NOTE: The build numbers quoted above are those reported by launching the FVP
1694with the ``--version`` parameter.
1695
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001696NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1697file systems that can be downloaded separately. To run an FVP with a virtio
1698file system image an additional FVP configuration option
1699``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1700used.
1701
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1703The commands below would report an ``unhandled argument`` error in this case.
1704
1705NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001706CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001707execution.
1708
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001709NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001710the internal synchronisation timings changed compared to older versions of the
1711models. The models can be launched with ``-Q 100`` option if they are required
1712to match the run time characteristics of the older versions.
1713
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001714The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001715downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001716
David Cunado124415e2017-06-27 17:31:12 +01001717The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001718`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001719
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001720Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001721parameter options. A brief description of the important ones that affect TF-A
1722and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001723
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001724Obtaining the Flattened Device Trees
1725~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1726
1727Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001728FDT files are required. FDT source files for the Foundation and Base FVPs can
1729be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1730a subset of the Base FVP components. For example, the Foundation FVP lacks
1731CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001732
1733Note: It is not recommended to use the FDTs built along the kernel because not
1734all FDTs are available from there.
1735
Soby Mathewecd94ad2018-05-09 13:59:29 +01001736The dynamic configuration capability is enabled in the firmware for FVPs.
1737This means that the firmware can authenticate and load the FDT if present in
1738FIP. A default FDT is packaged into FIP during the build based on
1739the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1740or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1741`Arm FVP platform specific build options`_ section for detail on the options).
1742
1743- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001744
David Cunado7c032642018-03-12 18:47:05 +00001745 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1746 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001747
Soby Mathewecd94ad2018-05-09 13:59:29 +01001748- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001749
David Cunado7c032642018-03-12 18:47:05 +00001750 For use with models such as the Cortex-A32 Base FVPs without shifted
1751 affinities and running Linux in AArch32 state with Base memory map
1752 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001753
Soby Mathewecd94ad2018-05-09 13:59:29 +01001754- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001755
David Cunado7c032642018-03-12 18:47:05 +00001756 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1757 affinities and with Base memory map configuration and Linux GICv3 support.
1758
Soby Mathewecd94ad2018-05-09 13:59:29 +01001759- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001760
1761 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1762 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1763
Soby Mathewecd94ad2018-05-09 13:59:29 +01001764- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001765
1766 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1767 single cluster, single threaded CPUs, Base memory map configuration and Linux
1768 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001769
Soby Mathewecd94ad2018-05-09 13:59:29 +01001770- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771
David Cunado7c032642018-03-12 18:47:05 +00001772 For use with models such as the Cortex-A32 Base FVPs without shifted
1773 affinities and running Linux in AArch32 state with Base memory map
1774 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001775
Soby Mathewecd94ad2018-05-09 13:59:29 +01001776- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001777
1778 For use with Foundation FVP with Base memory map configuration.
1779
Soby Mathewecd94ad2018-05-09 13:59:29 +01001780- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001781
1782 (Default) For use with Foundation FVP with Base memory map configuration
1783 and Linux GICv3 support.
1784
1785Running on the Foundation FVP with reset to BL1 entrypoint
1786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1787
1788The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017894 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001790
1791::
1792
1793 <path-to>/Foundation_Platform \
1794 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001795 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001796 --secure-memory \
1797 --visualization \
1798 --gicv3 \
1799 --data="<path-to>/<bl1-binary>"@0x0 \
1800 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001801 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001802 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001803
1804Notes:
1805
1806- BL1 is loaded at the start of the Trusted ROM.
1807- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001808- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1809 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001810- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1811 and enable the GICv3 device in the model. Note that without this option,
1812 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001813 is not supported by TF-A.
1814- In order for TF-A to run correctly on the Foundation FVP, the architecture
1815 versions must match. The Foundation FVP defaults to the highest v8.x
1816 version it supports but the default build for TF-A is for v8.0. To avoid
1817 issues either start the Foundation FVP to use v8.0 architecture using the
1818 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1819 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001820
1821Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1822~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1823
David Cunado7c032642018-03-12 18:47:05 +00001824The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001825with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001826
1827::
1828
David Cunado7c032642018-03-12 18:47:05 +00001829 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001830 -C pctl.startup=0.0.0.0 \
1831 -C bp.secure_memory=1 \
1832 -C bp.tzc_400.diagnostics=1 \
1833 -C cluster0.NUM_CORES=4 \
1834 -C cluster1.NUM_CORES=4 \
1835 -C cache_state_modelled=1 \
1836 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1837 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001838 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001839 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001840
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001841Note: The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
1842specific DTS for all the CPUs to be loaded.
1843
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001844Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1845~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1846
1847The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001848with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001849
1850::
1851
1852 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1853 -C pctl.startup=0.0.0.0 \
1854 -C bp.secure_memory=1 \
1855 -C bp.tzc_400.diagnostics=1 \
1856 -C cluster0.NUM_CORES=4 \
1857 -C cluster1.NUM_CORES=4 \
1858 -C cache_state_modelled=1 \
1859 -C cluster0.cpu0.CONFIG64=0 \
1860 -C cluster0.cpu1.CONFIG64=0 \
1861 -C cluster0.cpu2.CONFIG64=0 \
1862 -C cluster0.cpu3.CONFIG64=0 \
1863 -C cluster1.cpu0.CONFIG64=0 \
1864 -C cluster1.cpu1.CONFIG64=0 \
1865 -C cluster1.cpu2.CONFIG64=0 \
1866 -C cluster1.cpu3.CONFIG64=0 \
1867 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1868 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001869 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001870 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001871
1872Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1873~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1874
1875The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001876boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001877
1878::
1879
1880 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1881 -C pctl.startup=0.0.0.0 \
1882 -C bp.secure_memory=1 \
1883 -C bp.tzc_400.diagnostics=1 \
1884 -C cache_state_modelled=1 \
1885 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1886 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001887 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001888 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001889
1890Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1891~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1892
1893The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001894boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001895
1896::
1897
1898 <path-to>/FVP_Base_Cortex-A32x4 \
1899 -C pctl.startup=0.0.0.0 \
1900 -C bp.secure_memory=1 \
1901 -C bp.tzc_400.diagnostics=1 \
1902 -C cache_state_modelled=1 \
1903 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1904 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001905 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001906 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001907
1908Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1910
David Cunado7c032642018-03-12 18:47:05 +00001911The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001912with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001913
1914::
1915
David Cunado7c032642018-03-12 18:47:05 +00001916 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001917 -C pctl.startup=0.0.0.0 \
1918 -C bp.secure_memory=1 \
1919 -C bp.tzc_400.diagnostics=1 \
1920 -C cluster0.NUM_CORES=4 \
1921 -C cluster1.NUM_CORES=4 \
1922 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001923 -C cluster0.cpu0.RVBAR=0x04010000 \
1924 -C cluster0.cpu1.RVBAR=0x04010000 \
1925 -C cluster0.cpu2.RVBAR=0x04010000 \
1926 -C cluster0.cpu3.RVBAR=0x04010000 \
1927 -C cluster1.cpu0.RVBAR=0x04010000 \
1928 -C cluster1.cpu1.RVBAR=0x04010000 \
1929 -C cluster1.cpu2.RVBAR=0x04010000 \
1930 -C cluster1.cpu3.RVBAR=0x04010000 \
1931 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1932 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001933 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001934 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001935 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001936 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001937
1938Notes:
1939
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001940- If Position Independent Executable (PIE) support is enabled for BL31
Soby Mathewba678c32018-12-12 14:54:23 +00001941 in this config, it can be loaded at any valid address for execution.
1942
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001943- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1944 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1945 parameter is needed to load the individual bootloader images in memory.
1946 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001947 Payload. For the same reason, the FDT needs to be compiled from the DT source
1948 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1949 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001950
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001951- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
1952 specific DTS for all the CPUs to be loaded.
1953
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001954- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1955 X and Y are the cluster and CPU numbers respectively, is used to set the
1956 reset vector for each core.
1957
1958- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1959 changing the value of
1960 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1961 ``BL32_BASE``.
1962
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001963Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
1964~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001965
1966The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001967with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001968
1969::
1970
1971 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1972 -C pctl.startup=0.0.0.0 \
1973 -C bp.secure_memory=1 \
1974 -C bp.tzc_400.diagnostics=1 \
1975 -C cluster0.NUM_CORES=4 \
1976 -C cluster1.NUM_CORES=4 \
1977 -C cache_state_modelled=1 \
1978 -C cluster0.cpu0.CONFIG64=0 \
1979 -C cluster0.cpu1.CONFIG64=0 \
1980 -C cluster0.cpu2.CONFIG64=0 \
1981 -C cluster0.cpu3.CONFIG64=0 \
1982 -C cluster1.cpu0.CONFIG64=0 \
1983 -C cluster1.cpu1.CONFIG64=0 \
1984 -C cluster1.cpu2.CONFIG64=0 \
1985 -C cluster1.cpu3.CONFIG64=0 \
Soby Mathewba678c32018-12-12 14:54:23 +00001986 -C cluster0.cpu0.RVBAR=0x04002000 \
1987 -C cluster0.cpu1.RVBAR=0x04002000 \
1988 -C cluster0.cpu2.RVBAR=0x04002000 \
1989 -C cluster0.cpu3.RVBAR=0x04002000 \
1990 -C cluster1.cpu0.RVBAR=0x04002000 \
1991 -C cluster1.cpu1.RVBAR=0x04002000 \
1992 -C cluster1.cpu2.RVBAR=0x04002000 \
1993 -C cluster1.cpu3.RVBAR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001994 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001995 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001996 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001997 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001998 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001999
2000Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2001It should match the address programmed into the RVBAR register as well.
2002
2003Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2005
2006The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00002007boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002008
2009::
2010
2011 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2012 -C pctl.startup=0.0.0.0 \
2013 -C bp.secure_memory=1 \
2014 -C bp.tzc_400.diagnostics=1 \
2015 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002016 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2017 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2018 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2019 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2020 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2021 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2022 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2023 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2024 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2025 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002026 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002027 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002028 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002029 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002030
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002031Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002033
2034The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00002035boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002036
2037::
2038
2039 <path-to>/FVP_Base_Cortex-A32x4 \
2040 -C pctl.startup=0.0.0.0 \
2041 -C bp.secure_memory=1 \
2042 -C bp.tzc_400.diagnostics=1 \
2043 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002044 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2045 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2046 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2047 -C cluster0.cpu3.RVBARADDR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002048 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002049 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002050 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002051 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002052 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002053
2054Running the software on Juno
2055----------------------------
2056
Dan Handley610e7e12018-03-01 18:44:00 +00002057This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002058
2059To execute the software stack on Juno, the version of the Juno board recovery
2060image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2061earlier version installed or are unsure which version is installed, please
2062re-install the recovery image by following the
2063`Instructions for using Linaro's deliverables on Juno`_.
2064
Dan Handley610e7e12018-03-01 18:44:00 +00002065Preparing TF-A images
2066~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002067
Dan Handley610e7e12018-03-01 18:44:00 +00002068After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2069``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002070
2071Other Juno software information
2072~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2073
Dan Handley610e7e12018-03-01 18:44:00 +00002074Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002075software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002076get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002077configure it.
2078
2079Testing SYSTEM SUSPEND on Juno
2080~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2081
2082The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2083to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2084on Juno, at the linux shell prompt, issue the following command:
2085
2086::
2087
2088 echo +10 > /sys/class/rtc/rtc0/wakealarm
2089 echo -n mem > /sys/power/state
2090
2091The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2092wakeup interrupt from RTC.
2093
2094--------------
2095
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +00002096*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002097
Louis Mayencourt545a9ed2019-03-08 15:35:40 +00002098.. _arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
David Cunadob2de0992017-06-29 12:01:33 +01002099.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002100.. _Linaro Release: `Linaro Release Notes`_
Paul Beesley2437ddc2019-02-08 16:43:05 +00002101.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
2102.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
David Cunado82509be2017-12-19 16:33:25 +00002103.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002104.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Paul Beesley2437ddc2019-02-08 16:43:05 +00002105.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
Louis Mayencourt72ef3d42019-03-22 11:47:22 +00002106.. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
Paul Beesley8b4bdeb2019-01-21 12:06:24 +00002107.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
Sandrine Bailleux771535b2018-09-20 10:27:13 +02002108.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002109.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002110.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002111.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002112.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002113.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002114.. _Firmware Update: firmware-update.rst
2115.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002116.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2117.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002118.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002119.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002120.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002121.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Sandrine Bailleux604f0a42018-09-20 12:44:39 +02002122.. _Secure Partition Manager Design guide: secure-partition-manager-design.rst
Paul Beesley8b4bdeb2019-01-21 12:06:24 +00002123.. _`Trusted Firmware-A Coding Guidelines`: coding-guidelines.rst
Louis Mayencourt72ef3d42019-03-22 11:47:22 +00002124.. _`Library at ROM`: romlib-design.rst