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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00002 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Varun Wadekar423045d2022-05-25 12:45:22 +01003 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
Florian Lugoud4e25032021-09-08 12:40:24 +020082#define ICC_ASGI1R S3_0_C12_C11_6
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000083#define ICC_SRE_EL1 S3_0_C12_C12_5
84#define ICC_SRE_EL2 S3_4_C12_C9_5
85#define ICC_SRE_EL3 S3_6_C12_C12_5
86#define ICC_CTLR_EL1 S3_0_C12_C12_4
87#define ICC_CTLR_EL3 S3_6_C12_C12_4
88#define ICC_PMR_EL1 S3_0_C4_C6_0
89#define ICC_RPR_EL1 S3_0_C12_C11_3
90#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
91#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
92#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
93#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
94#define ICC_IAR0_EL1 S3_0_c12_c8_0
95#define ICC_IAR1_EL1 S3_0_c12_c12_0
96#define ICC_EOIR0_EL1 S3_0_c12_c8_1
97#define ICC_EOIR1_EL1 S3_0_c12_c12_1
98#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010099
100/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000101 * Definitions for EL2 system registers for save/restore routine
102 ******************************************************************************/
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Varun Wadekar423045d2022-05-25 12:45:22 +0100112#define MPAMVPM0_EL2 S3_4_C10_C6_0
113#define MPAMVPM1_EL2 S3_4_C10_C6_1
114#define MPAMVPM2_EL2 S3_4_C10_C6_2
115#define MPAMVPM3_EL2 S3_4_C10_C6_3
116#define MPAMVPM4_EL2 S3_4_C10_C6_4
117#define MPAMVPM5_EL2 S3_4_C10_C6_5
118#define MPAMVPM6_EL2 S3_4_C10_C6_6
119#define MPAMVPM7_EL2 S3_4_C10_C6_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
Andre Przywaraedc449d2023-01-27 14:09:20 +0000122#define VNCR_EL2 S3_4_C2_C2_0
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000123#define PMSCR_EL2 S3_4_C9_C9_0
124#define TFSR_EL2 S3_4_C5_C6_0
Andre Przywara98908b32022-11-17 16:42:09 +0000125#define CONTEXTIDR_EL2 S3_4_C13_C0_1
126#define TTBR1_EL2 S3_4_C2_C0_1
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000127
128/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000129 * Generic timer memory mapped registers & offsets
130 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700131#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200132#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700133#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000134
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700135#define CNTCR_EN (U(1) << 0)
136#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100137#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000138
139/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140 * System register bit definitions
141 ******************************************************************************/
142/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define LOUIS_SHIFT U(21)
144#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100145#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
148/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100151/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700152#define DCISW U(0x0)
153#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000154#if ERRATA_A53_827319
155#define DCCSW DCCISW
156#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700157#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000158#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159
160/* ID_AA64PFR0_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000161#define ID_AA64PFR0_EL0_SHIFT U(0)
162#define ID_AA64PFR0_EL1_SHIFT U(4)
163#define ID_AA64PFR0_EL2_SHIFT U(8)
164#define ID_AA64PFR0_EL3_SHIFT U(12)
165
166#define ID_AA64PFR0_AMU_SHIFT U(44)
167#define ID_AA64PFR0_AMU_MASK ULL(0xf)
168#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
169#define ID_AA64PFR0_AMU_V1 ULL(0x1)
170#define ID_AA64PFR0_AMU_V1P1 U(0x2)
171
172#define ID_AA64PFR0_ELX_MASK ULL(0xf)
173
174#define ID_AA64PFR0_GIC_SHIFT U(24)
175#define ID_AA64PFR0_GIC_WIDTH U(4)
176#define ID_AA64PFR0_GIC_MASK ULL(0xf)
177
178#define ID_AA64PFR0_SVE_SHIFT U(32)
179#define ID_AA64PFR0_SVE_MASK ULL(0xf)
180#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
181#define ID_AA64PFR0_SVE_LENGTH U(4)
182
183#define ID_AA64PFR0_SEL2_SHIFT U(36)
184#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
185
186#define ID_AA64PFR0_MPAM_SHIFT U(40)
187#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
188
189#define ID_AA64PFR0_DIT_SHIFT U(48)
190#define ID_AA64PFR0_DIT_MASK ULL(0xf)
191#define ID_AA64PFR0_DIT_LENGTH U(4)
192#define ID_AA64PFR0_DIT_SUPPORTED U(1)
193
194#define ID_AA64PFR0_CSV2_SHIFT U(56)
195#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
196#define ID_AA64PFR0_CSV2_LENGTH U(4)
197#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
198
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500199#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
200#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
201#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
202#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
203#define ID_AA64PFR0_FEAT_RME_V1 U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000205#define ID_AA64PFR0_RAS_SHIFT U(28)
206#define ID_AA64PFR0_RAS_MASK ULL(0xf)
207#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
208#define ID_AA64PFR0_RAS_LENGTH U(4)
209
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100210/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100211#define EL_IMPL_NONE ULL(0)
212#define EL_IMPL_A64ONLY ULL(1)
213#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000214
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100215/* ID_AA64DFR0_EL1.TraceVer definitions */
216#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
217#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
218#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
219#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100220#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
221#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
222#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
223#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100224
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100225/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000226#define ID_AA64DFR0_PMS_SHIFT U(32)
227#define ID_AA64DFR0_PMS_MASK ULL(0xf)
228#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
229#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
Achin Gupta92712a52015-09-03 14:18:02 +0100230
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100231/* ID_AA64DFR0_EL1.TraceBuffer definitions */
232#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
233#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
234#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
235
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000236/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
237#define ID_AA64DFR0_MTPMU_SHIFT U(48)
238#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
239#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
240
johpow0181865962022-01-28 17:06:20 -0600241/* ID_AA64DFR0_EL1.BRBE definitions */
242#define ID_AA64DFR0_BRBE_SHIFT U(52)
243#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
244#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
245
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000246/* ID_AA64ISAR0_EL1 definitions */
johpow019baade32021-07-08 14:14:00 -0500247#define ID_AA64ISAR0_RNDR_SHIFT U(60)
248#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000249
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000250/* ID_AA64ISAR1_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000251#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
252
253#define ID_AA64ISAR1_GPI_SHIFT U(28)
254#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
255#define ID_AA64ISAR1_GPA_SHIFT U(24)
256#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
257
258#define ID_AA64ISAR1_API_SHIFT U(8)
259#define ID_AA64ISAR1_API_MASK ULL(0xf)
260#define ID_AA64ISAR1_APA_SHIFT U(4)
261#define ID_AA64ISAR1_APA_MASK ULL(0xf)
262
263#define ID_AA64ISAR1_SB_SHIFT U(36)
264#define ID_AA64ISAR1_SB_MASK ULL(0xf)
265#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
266#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000267
Juan Pablo Condee089a172022-06-29 17:44:43 -0400268/* ID_AA64ISAR2_EL1 definitions */
269#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
270
271#define ID_AA64ISAR2_GPA3_SHIFT U(8)
272#define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
273
274#define ID_AA64ISAR2_APA3_SHIFT U(12)
275#define ID_AA64ISAR2_APA3_MASK ULL(0xf)
276
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000277/* ID_AA64MMFR0_EL1 definitions */
278#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
279#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
280
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700281#define PARANGE_0000 U(32)
282#define PARANGE_0001 U(36)
283#define PARANGE_0010 U(40)
284#define PARANGE_0011 U(42)
285#define PARANGE_0100 U(44)
286#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000287#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000288
Jimmy Brisson83573892020-04-16 10:48:02 -0500289#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
290#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
291#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
292#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
293#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
294
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500295#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
296#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
297#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
298#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
299
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100300#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100301#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
302#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
303#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100304
305#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100306#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
307#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
308#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100309
310#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100311#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
312#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
313#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100314
johpow013e24c162020-04-22 14:05:13 -0500315/* ID_AA64MMFR1_EL1 definitions */
316#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
317#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
318#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
319#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
320
Alexei Fedorovc082f032020-11-25 14:07:05 +0000321#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
322#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
323#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
324#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
325#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
326#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
327
Daniel Boulby44b43332020-11-25 16:36:46 +0000328#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
329#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
330
johpow019baade32021-07-08 14:14:00 -0500331#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
332#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
333#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
334#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -0500335
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000336/* ID_AA64MMFR2_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000337#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000338
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000339#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
340#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
Sathees Balya74155972019-01-25 11:36:01 +0000341
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000342#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
343#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
344#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
345
346#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
347#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
johpow0174b7e442021-12-01 13:18:30 -0600348
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000349#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
350#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
351#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
352#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
353#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000354
Mark Brownc37eee72023-03-14 20:13:03 +0000355/* ID_AA64MMFR3_EL1 definitions */
356#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
357
358#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
359#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
360
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000361/* ID_AA64PFR1_EL1 definitions */
362#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
363#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
364
365#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
366
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100367#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
368#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
369
370#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
371
Soby Mathew830f0ad2019-07-12 09:23:38 +0100372#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
373#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
374
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400375#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
376#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
377
378#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
379#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
380
Alexei Fedorovaf54f6e2020-12-01 13:22:25 +0000381/* Memory Tagging Extension is not implemented */
382#define MTE_UNIMPLEMENTED U(0)
383/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
384#define MTE_IMPLEMENTED_EL0 U(1)
385/* FEAT_MTE2: Full MTE is implemented */
386#define MTE_IMPLEMENTED_ELX U(2)
387/*
388 * FEAT_MTE3: MTE is implemented with support for
389 * asymmetric Tag Check Fault handling
390 */
391#define MTE_IMPLEMENTED_ASY U(3)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100392
Alexei Fedorov19933552020-05-26 13:16:41 +0100393#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
394#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
395
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000396#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
397#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
398#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
399#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
johpow019baade32021-07-08 14:14:00 -0500400
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700402#define ID_PFR1_VIRTEXT_SHIFT U(12)
403#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100404#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100405 & ID_PFR1_VIRTEXT_MASK)
406
407/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100408#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700409 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
410 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100411
John Powella5c66362020-03-20 14:21:05 -0500412#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
413 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Alexei Fedorovc082f032020-11-25 14:07:05 +0000414
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200415#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700416 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
417 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200418
David Cunadofee86532017-04-13 22:38:29 +0100419#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
420 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
421 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
422
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000423#define SCTLR_M_BIT (ULL(1) << 0)
424#define SCTLR_A_BIT (ULL(1) << 1)
425#define SCTLR_C_BIT (ULL(1) << 2)
426#define SCTLR_SA_BIT (ULL(1) << 3)
427#define SCTLR_SA0_BIT (ULL(1) << 4)
428#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000429#define SCTLR_nAA_BIT (ULL(1) << 6)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000430#define SCTLR_ITD_BIT (ULL(1) << 7)
431#define SCTLR_SED_BIT (ULL(1) << 8)
432#define SCTLR_UMA_BIT (ULL(1) << 9)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000433#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
434#define SCTLR_EOS_BIT (ULL(1) << 11)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000435#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100436#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000437#define SCTLR_DZE_BIT (ULL(1) << 14)
438#define SCTLR_UCT_BIT (ULL(1) << 15)
439#define SCTLR_NTWI_BIT (ULL(1) << 16)
440#define SCTLR_NTWE_BIT (ULL(1) << 18)
441#define SCTLR_WXN_BIT (ULL(1) << 19)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000442#define SCTLR_TSCXT_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000443#define SCTLR_IESB_BIT (ULL(1) << 21)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000444#define SCTLR_EIS_BIT (ULL(1) << 22)
445#define SCTLR_SPAN_BIT (ULL(1) << 23)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000446#define SCTLR_E0E_BIT (ULL(1) << 24)
447#define SCTLR_EE_BIT (ULL(1) << 25)
448#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100449#define SCTLR_EnDA_BIT (ULL(1) << 27)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000450#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
451#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100452#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000453#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100454#define SCTLR_BT0_BIT (ULL(1) << 35)
455#define SCTLR_BT1_BIT (ULL(1) << 36)
456#define SCTLR_BT_BIT (ULL(1) << 36)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000457#define SCTLR_ITFSB_BIT (ULL(1) << 37)
458#define SCTLR_TCF0_SHIFT U(38)
459#define SCTLR_TCF0_MASK ULL(3)
johpow019baade32021-07-08 14:14:00 -0500460#define SCTLR_ENTP2_BIT (ULL(1) << 60)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000461
462/* Tag Check Faults in EL0 have no effect on the PE */
463#define SCTLR_TCF0_NO_EFFECT U(0)
464/* Tag Check Faults in EL0 cause a synchronous exception */
465#define SCTLR_TCF0_SYNC U(1)
466/* Tag Check Faults in EL0 are asynchronously accumulated */
467#define SCTLR_TCF0_ASYNC U(2)
468/*
469 * Tag Check Faults in EL0 cause a synchronous exception on reads,
470 * and are asynchronously accumulated on writes
471 */
472#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
473
474#define SCTLR_TCF_SHIFT U(40)
475#define SCTLR_TCF_MASK ULL(3)
476
477/* Tag Check Faults in EL1 have no effect on the PE */
478#define SCTLR_TCF_NO_EFFECT U(0)
479/* Tag Check Faults in EL1 cause a synchronous exception */
480#define SCTLR_TCF_SYNC U(1)
481/* Tag Check Faults in EL1 are asynchronously accumulated */
482#define SCTLR_TCF_ASYNC U(2)
483/*
484 * Tag Check Faults in EL1 cause a synchronous exception on reads,
485 * and are asynchronously accumulated on writes
486 */
487#define SCTLR_TCF_SYNCR_ASYNCW U(3)
488
489#define SCTLR_ATA0_BIT (ULL(1) << 42)
490#define SCTLR_ATA_BIT (ULL(1) << 43)
Daniel Boulby44b43332020-11-25 16:36:46 +0000491#define SCTLR_DSSBS_SHIFT U(44)
492#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000493#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
494#define SCTLR_TWEDEL_SHIFT U(46)
495#define SCTLR_TWEDEL_MASK ULL(0xf)
496#define SCTLR_EnASR_BIT (ULL(1) << 54)
497#define SCTLR_EnAS0_BIT (ULL(1) << 55)
498#define SCTLR_EnALS_BIT (ULL(1) << 56)
499#define SCTLR_EPAN_BIT (ULL(1) << 57)
David Cunadofee86532017-04-13 22:38:29 +0100500#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100501
Alexei Fedorovc082f032020-11-25 14:07:05 +0000502/* CPACR_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700503#define CPACR_EL1_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500504#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
505#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
506#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100507
508/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700509#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500510#define SCR_NSE_SHIFT U(62)
511#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
512#define SCR_GPF_BIT (UL(1) << 48)
johpow013e24c162020-04-22 14:05:13 -0500513#define SCR_TWEDEL_SHIFT U(30)
514#define SCR_TWEDEL_MASK ULL(0xf)
Mark Brownc37eee72023-03-14 20:13:03 +0000515#define SCR_TCR2EN_BIT (UL(1) << 43)
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400516#define SCR_TRNDR_BIT (UL(1) << 40)
johpow019baade32021-07-08 14:14:00 -0500517#define SCR_HXEn_BIT (UL(1) << 38)
518#define SCR_ENTP2_SHIFT U(41)
519#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT)
John Powellcc799272022-03-29 00:25:59 -0500520#define SCR_AMVOFFEN_SHIFT U(35)
521#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT)
johpow013e24c162020-04-22 14:05:13 -0500522#define SCR_TWEDEn_BIT (UL(1) << 29)
johpow01fa59c6f2020-10-02 13:41:11 -0500523#define SCR_ECVEN_BIT (UL(1) << 28)
524#define SCR_FGTEN_BIT (UL(1) << 27)
Jimmy Brissoned202072020-08-04 16:18:52 -0500525#define SCR_ATA_BIT (UL(1) << 26)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500526#define SCR_EnSCXT_BIT (UL(1) << 25)
Jimmy Brissoned202072020-08-04 16:18:52 -0500527#define SCR_FIEN_BIT (UL(1) << 21)
528#define SCR_EEL2_BIT (UL(1) << 18)
529#define SCR_API_BIT (UL(1) << 17)
530#define SCR_APK_BIT (UL(1) << 16)
531#define SCR_TERR_BIT (UL(1) << 15)
532#define SCR_TWE_BIT (UL(1) << 13)
533#define SCR_TWI_BIT (UL(1) << 12)
534#define SCR_ST_BIT (UL(1) << 11)
535#define SCR_RW_BIT (UL(1) << 10)
536#define SCR_SIF_BIT (UL(1) << 9)
537#define SCR_HCE_BIT (UL(1) << 8)
538#define SCR_SMD_BIT (UL(1) << 7)
539#define SCR_EA_BIT (UL(1) << 3)
540#define SCR_FIQ_BIT (UL(1) << 2)
541#define SCR_IRQ_BIT (UL(1) << 1)
542#define SCR_NS_BIT (UL(1) << 0)
johpow019baade32021-07-08 14:14:00 -0500543#define SCR_VALID_BIT_MASK U(0x24000002F8F)
David Cunadofee86532017-04-13 22:38:29 +0100544#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100545
David Cunadofee86532017-04-13 22:38:29 +0100546/* MDCR_EL3 definitions */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100547#define MDCR_EnPMSN_BIT (ULL(1) << 36)
548#define MDCR_MPMX_BIT (ULL(1) << 35)
549#define MDCR_MCCD_BIT (ULL(1) << 34)
johpow0181865962022-01-28 17:06:20 -0600550#define MDCR_SBRBE_SHIFT U(32)
551#define MDCR_SBRBE_MASK ULL(0x3)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100552#define MDCR_NSTB(x) ((x) << 24)
553#define MDCR_NSTB_EL1 ULL(0x3)
554#define MDCR_NSTBE (ULL(1) << 26)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000555#define MDCR_MTPME_BIT (ULL(1) << 28)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100556#define MDCR_TDCC_BIT (ULL(1) << 27)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100557#define MDCR_SCCD_BIT (ULL(1) << 23)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100558#define MDCR_EPMAD_BIT (ULL(1) << 21)
559#define MDCR_EDAD_BIT (ULL(1) << 20)
560#define MDCR_TTRF_BIT (ULL(1) << 19)
561#define MDCR_STE_BIT (ULL(1) << 18)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100562#define MDCR_SPME_BIT (ULL(1) << 17)
563#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000564#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000565#define MDCR_SPD32_LEGACY ULL(0x0)
566#define MDCR_SPD32_DISABLE ULL(0x2)
567#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100568#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000569#define MDCR_NSPB_EL1 ULL(0x3)
570#define MDCR_TDOSA_BIT (ULL(1) << 10)
571#define MDCR_TDA_BIT (ULL(1) << 9)
572#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000573#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000574
David Cunadofee86532017-04-13 22:38:29 +0100575/* MDCR_EL2 definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000576#define MDCR_EL2_MTPME (U(1) << 28)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100577#define MDCR_EL2_HLP (U(1) << 26)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100578#define MDCR_EL2_E2TB(x) ((x) << 24)
579#define MDCR_EL2_E2TB_EL1 U(0x3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100580#define MDCR_EL2_HCCD (U(1) << 23)
581#define MDCR_EL2_TTRF (U(1) << 19)
582#define MDCR_EL2_HPMD (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100583#define MDCR_EL2_TPMS (U(1) << 14)
584#define MDCR_EL2_E2PB(x) ((x) << 12)
585#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100586#define MDCR_EL2_TDRA_BIT (U(1) << 11)
587#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
588#define MDCR_EL2_TDA_BIT (U(1) << 9)
589#define MDCR_EL2_TDE_BIT (U(1) << 8)
590#define MDCR_EL2_HPME_BIT (U(1) << 7)
591#define MDCR_EL2_TPM_BIT (U(1) << 6)
592#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
593#define MDCR_EL2_RESET_VAL U(0x0)
594
595/* HSTR_EL2 definitions */
596#define HSTR_EL2_RESET_VAL U(0x0)
597#define HSTR_EL2_T_MASK U(0xff)
598
599/* CNTHP_CTL_EL2 definitions */
600#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
601#define CNTHP_CTL_RESET_VAL U(0x0)
602
603/* VTTBR_EL2 definitions */
604#define VTTBR_RESET_VAL ULL(0x0)
605#define VTTBR_VMID_MASK ULL(0xff)
606#define VTTBR_VMID_SHIFT U(48)
607#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
608#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000609
Achin Gupta4f6ad662013-10-25 09:08:21 +0100610/* HCR definitions */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600611#define HCR_RESET_VAL ULL(0x0)
Chris Kaya5fde282021-05-26 11:58:23 +0100612#define HCR_AMVOFFEN_SHIFT U(51)
613#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600614#define HCR_TEA_BIT (ULL(1) << 47)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100615#define HCR_API_BIT (ULL(1) << 41)
616#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100617#define HCR_E2H_BIT (ULL(1) << 34)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600618#define HCR_HCD_BIT (ULL(1) << 29)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000619#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700620#define HCR_RW_SHIFT U(31)
621#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600622#define HCR_TWE_BIT (ULL(1) << 14)
623#define HCR_TWI_BIT (ULL(1) << 13)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100624#define HCR_AMO_BIT (ULL(1) << 5)
625#define HCR_IMO_BIT (ULL(1) << 4)
626#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100627
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100628/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700629#define ISR_A_SHIFT U(8)
630#define ISR_I_SHIFT U(7)
631#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100632
Achin Gupta4f6ad662013-10-25 09:08:21 +0100633/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100634#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700635#define EVNTEN_BIT (U(1) << 2)
636#define EL1PCEN_BIT (U(1) << 1)
637#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100638
639/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700640#define EL0PTEN_BIT (U(1) << 9)
641#define EL0VTEN_BIT (U(1) << 8)
642#define EL0PCTEN_BIT (U(1) << 0)
643#define EL0VCTEN_BIT (U(1) << 1)
644#define EVNTEN_BIT (U(1) << 2)
645#define EVNTDIR_BIT (U(1) << 3)
646#define EVNTI_SHIFT U(4)
647#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100648
649/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700650#define TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100651#define TAM_SHIFT U(30)
652#define TAM_BIT (U(1) << TAM_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700653#define TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500654#define ESM_BIT (U(1) << 12)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700655#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100656#define CPTR_EZ_BIT (U(1) << 8)
johpow019baade32021-07-08 14:14:00 -0500657#define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \
658 ~(CPTR_EZ_BIT | ESM_BIT))
David Cunadofee86532017-04-13 22:38:29 +0100659
660/* CPTR_EL2 definitions */
661#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
662#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100663#define CPTR_EL2_TAM_SHIFT U(30)
664#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
johpow019baade32021-07-08 14:14:00 -0500665#define CPTR_EL2_SMEN_MASK ULL(0x3)
666#define CPTR_EL2_SMEN_SHIFT U(24)
David Cunadofee86532017-04-13 22:38:29 +0100667#define CPTR_EL2_TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500668#define CPTR_EL2_TSM_BIT (U(1) << 12)
David Cunadofee86532017-04-13 22:38:29 +0100669#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100670#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100671#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100672
Manish Pandey5693afe2021-10-06 17:28:09 +0100673/* VTCR_EL2 definitions */
johpow019baade32021-07-08 14:14:00 -0500674#define VTCR_RESET_VAL U(0x0)
675#define VTCR_EL2_MSA (U(1) << 31)
Manish Pandey5693afe2021-10-06 17:28:09 +0100676
Achin Gupta4f6ad662013-10-25 09:08:21 +0100677/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700678#define DAIF_FIQ_BIT (U(1) << 0)
679#define DAIF_IRQ_BIT (U(1) << 1)
680#define DAIF_ABT_BIT (U(1) << 2)
681#define DAIF_DBG_BIT (U(1) << 3)
682#define SPSR_DAIF_SHIFT U(6)
683#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100684
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700685#define SPSR_AIF_SHIFT U(6)
686#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100687
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700688#define SPSR_E_SHIFT U(9)
689#define SPSR_E_MASK U(0x1)
690#define SPSR_E_LITTLE U(0x0)
691#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100692
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700693#define SPSR_T_SHIFT U(5)
694#define SPSR_T_MASK U(0x1)
695#define SPSR_T_ARM U(0x0)
696#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100697
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000698#define SPSR_M_SHIFT U(4)
699#define SPSR_M_MASK U(0x1)
700#define SPSR_M_AARCH64 U(0x0)
701#define SPSR_M_AARCH32 U(0x1)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500702#define SPSR_M_EL2H U(0x9)
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000703
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000704#define SPSR_EL_SHIFT U(2)
705#define SPSR_EL_WIDTH U(2)
706
Daniel Boulby44b43332020-11-25 16:36:46 +0000707#define SPSR_SSBS_SHIFT_AARCH64 U(12)
708#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
709#define SPSR_SSBS_SHIFT_AARCH32 U(23)
710#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
711
712#define SPSR_PAN_BIT BIT_64(22)
713
714#define SPSR_DIT_BIT BIT(24)
715
716#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
John Tsichritzis55534172019-07-23 11:12:41 +0100717
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100718#define DISABLE_ALL_EXCEPTIONS \
719 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
720
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000721#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
722
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000723/*
724 * RMR_EL3 definitions
725 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700726#define RMR_EL3_RR_BIT (U(1) << 1)
727#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000728
729/*
730 * HI-VECTOR address for AArch32 state
731 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000732#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100733
734/*
735 * TCR defintions
736 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000737#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100738#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700739#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100740#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700741#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700742
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100743#define TCR_TxSZ_MIN ULL(16)
744#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000745#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100746
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000747#define TCR_T0SZ_SHIFT U(0)
748#define TCR_T1SZ_SHIFT U(16)
749
Lin Ma741a3822014-06-27 16:56:30 -0700750/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100751#define TCR_PS_BITS_4GB ULL(0x0)
752#define TCR_PS_BITS_64GB ULL(0x1)
753#define TCR_PS_BITS_1TB ULL(0x2)
754#define TCR_PS_BITS_4TB ULL(0x3)
755#define TCR_PS_BITS_16TB ULL(0x4)
756#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100757
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700758#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
759#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
760#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
761#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
762#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
763#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100764
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100765#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
766#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
767#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
768#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100769
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100770#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
771#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
772#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
773#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100774
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100775#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
776#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
777#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100778
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000779#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
780#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
781#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
782#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
783
784#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
785#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
786#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
787#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
788
789#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
790#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
791#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
792
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100793#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100794#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100795#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
796#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
797#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
798
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000799#define TCR_TG1_SHIFT U(30)
800#define TCR_TG1_MASK ULL(3)
801#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
802#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
803#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
804
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100805#define TCR_EPD0_BIT (ULL(1) << 7)
806#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100807
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700808#define MODE_SP_SHIFT U(0x0)
809#define MODE_SP_MASK U(0x1)
810#define MODE_SP_EL0 U(0x0)
811#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100812
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700813#define MODE_RW_SHIFT U(0x4)
814#define MODE_RW_MASK U(0x1)
815#define MODE_RW_64 U(0x0)
816#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100817
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700818#define MODE_EL_SHIFT U(0x2)
819#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000820#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700821#define MODE_EL3 U(0x3)
822#define MODE_EL2 U(0x2)
823#define MODE_EL1 U(0x1)
824#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100825
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700826#define MODE32_SHIFT U(0)
827#define MODE32_MASK U(0xf)
828#define MODE32_usr U(0x0)
829#define MODE32_fiq U(0x1)
830#define MODE32_irq U(0x2)
831#define MODE32_svc U(0x3)
832#define MODE32_mon U(0x6)
833#define MODE32_abt U(0x7)
834#define MODE32_hyp U(0xa)
835#define MODE32_und U(0xb)
836#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100837
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100838#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
839#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
840#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
841#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100842
John Tsichritzis55534172019-07-23 11:12:41 +0100843#define SPSR_64(el, sp, daif) \
844 (((MODE_RW_64 << MODE_RW_SHIFT) | \
845 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
846 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
847 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
848 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100849
850#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100851 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700852 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
853 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
854 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100855 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
856 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100857
Dan Handley0cdebbd2015-03-30 17:15:16 +0100858/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100859 * TTBR Definitions
860 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100861#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100862
863/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100864 * CTR_EL0 definitions
865 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700866#define CTR_CWG_SHIFT U(24)
867#define CTR_CWG_MASK U(0xf)
868#define CTR_ERG_SHIFT U(20)
869#define CTR_ERG_MASK U(0xf)
870#define CTR_DMINLINE_SHIFT U(16)
871#define CTR_DMINLINE_MASK U(0xf)
872#define CTR_L1IP_SHIFT U(14)
873#define CTR_L1IP_MASK U(0x3)
874#define CTR_IMINLINE_SHIFT U(0)
875#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100876
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700877#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100878
Achin Gupta405406d2014-05-09 12:00:17 +0100879/* Physical timer control register bit fields shifts and masks */
johpow01fa59c6f2020-10-02 13:41:11 -0500880#define CNTP_CTL_ENABLE_SHIFT U(0)
881#define CNTP_CTL_IMASK_SHIFT U(1)
882#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100883
johpow01fa59c6f2020-10-02 13:41:11 -0500884#define CNTP_CTL_ENABLE_MASK U(1)
885#define CNTP_CTL_IMASK_MASK U(1)
886#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100887
Varun Wadekar787a1292018-06-18 16:15:51 -0700888/* Physical timer control macros */
889#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
890#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
891
Achin Gupta4f6ad662013-10-25 09:08:21 +0100892/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700893#define ESR_EC_SHIFT U(26)
894#define ESR_EC_MASK U(0x3f)
895#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100896#define ESR_ISS_SHIFT U(0)
897#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700898#define EC_UNKNOWN U(0x0)
899#define EC_WFE_WFI U(0x1)
900#define EC_AARCH32_CP15_MRC_MCR U(0x3)
901#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
902#define EC_AARCH32_CP14_MRC_MCR U(0x5)
903#define EC_AARCH32_CP14_LDC_STC U(0x6)
904#define EC_FP_SIMD U(0x7)
905#define EC_AARCH32_CP10_MRC U(0x8)
906#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
907#define EC_ILLEGAL U(0xe)
908#define EC_AARCH32_SVC U(0x11)
909#define EC_AARCH32_HVC U(0x12)
910#define EC_AARCH32_SMC U(0x13)
911#define EC_AARCH64_SVC U(0x15)
912#define EC_AARCH64_HVC U(0x16)
913#define EC_AARCH64_SMC U(0x17)
914#define EC_AARCH64_SYS U(0x18)
915#define EC_IABORT_LOWER_EL U(0x20)
916#define EC_IABORT_CUR_EL U(0x21)
917#define EC_PC_ALIGN U(0x22)
918#define EC_DABORT_LOWER_EL U(0x24)
919#define EC_DABORT_CUR_EL U(0x25)
920#define EC_SP_ALIGN U(0x26)
921#define EC_AARCH32_FP U(0x28)
922#define EC_AARCH64_FP U(0x2c)
923#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100924#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100925
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000926/*
927 * External Abort bit in Instruction and Data Aborts synchronous exception
928 * syndromes.
929 */
930#define ESR_ISS_EABORT_EA_BIT U(9)
931
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700932#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100933
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800934/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700935#define RMR_RESET_REQUEST_SHIFT U(0x1)
936#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800937
Dan Handleyed6ff952014-05-14 17:44:19 +0100938/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000939 * Definitions of register offsets, fields and macros for CPU system
940 * instructions.
941 ******************************************************************************/
942
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700943#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000944#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
945#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
946
947/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100948 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
949 * system level implementation of the Generic Timer.
950 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100951#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700952#define CNTNSAR U(0x4)
953#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100954
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700955#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
956#define CNTACR_RPCT_SHIFT U(0x0)
957#define CNTACR_RVCT_SHIFT U(0x1)
958#define CNTACR_RFRQ_SHIFT U(0x2)
959#define CNTACR_RVOFF_SHIFT U(0x3)
960#define CNTACR_RWVT_SHIFT U(0x4)
961#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100962
Soby Mathew2d9f7952018-06-11 16:21:30 +0100963/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000964 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100965 * system level implementation of the Generic Timer.
966 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000967/* Physical Count register. */
968#define CNTPCT_LO U(0x0)
969/* Counter Frequency register. */
970#define CNTBASEN_CNTFRQ U(0x10)
971/* Physical Timer CompareValue register. */
972#define CNTP_CVAL_LO U(0x20)
973/* Physical Timer Control register. */
974#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100975
David Cunado5f55e282016-10-31 17:37:34 +0000976/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100977#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700978#define PMCR_EL0_N_SHIFT U(11)
979#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000980#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100981#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +0100982#define PMCR_EL0_LC_BIT (U(1) << 6)
983#define PMCR_EL0_DP_BIT (U(1) << 5)
984#define PMCR_EL0_X_BIT (U(1) << 4)
985#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100986#define PMCR_EL0_C_BIT (U(1) << 2)
987#define PMCR_EL0_P_BIT (U(1) << 1)
988#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +0000989
Isla Mitchell02c63072017-07-21 14:44:36 +0100990/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100991 * Definitions for system register interface to SVE
992 ******************************************************************************/
993#define ZCR_EL3 S3_6_C1_C2_0
994#define ZCR_EL2 S3_4_C1_C2_0
995
996/* ZCR_EL3 definitions */
997#define ZCR_EL3_LEN_MASK U(0xf)
998
999/* ZCR_EL2 definitions */
1000#define ZCR_EL2_LEN_MASK U(0xf)
1001
1002/*******************************************************************************
johpow019baade32021-07-08 14:14:00 -05001003 * Definitions for system register interface to SME as needed in EL3
1004 ******************************************************************************/
1005#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5
1006#define SMCR_EL3 S3_6_C1_C2_6
1007
1008/* ID_AA64SMFR0_EL1 definitions */
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +00001009#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
1010#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
1011#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
johpow019baade32021-07-08 14:14:00 -05001012
1013/* SMCR_ELx definitions */
1014#define SMCR_ELX_LEN_SHIFT U(0)
1015#define SMCR_ELX_LEN_MASK U(0x1ff)
1016#define SMCR_ELX_FA64_BIT (U(1) << 31)
1017
1018/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +01001019 * Definitions of MAIR encodings for device and normal memory
1020 ******************************************************************************/
1021/*
1022 * MAIR encodings for device memory attributes.
1023 */
1024#define MAIR_DEV_nGnRnE ULL(0x0)
1025#define MAIR_DEV_nGnRE ULL(0x4)
1026#define MAIR_DEV_nGRE ULL(0x8)
1027#define MAIR_DEV_GRE ULL(0xc)
1028
1029/*
1030 * MAIR encodings for normal memory attributes.
1031 *
1032 * Cache Policy
1033 * WT: Write Through
1034 * WB: Write Back
1035 * NC: Non-Cacheable
1036 *
1037 * Transient Hint
1038 * NTR: Non-Transient
1039 * TR: Transient
1040 *
1041 * Allocation Policy
1042 * RA: Read Allocate
1043 * WA: Write Allocate
1044 * RWA: Read and Write Allocate
1045 * NA: No Allocation
1046 */
1047#define MAIR_NORM_WT_TR_WA ULL(0x1)
1048#define MAIR_NORM_WT_TR_RA ULL(0x2)
1049#define MAIR_NORM_WT_TR_RWA ULL(0x3)
1050#define MAIR_NORM_NC ULL(0x4)
1051#define MAIR_NORM_WB_TR_WA ULL(0x5)
1052#define MAIR_NORM_WB_TR_RA ULL(0x6)
1053#define MAIR_NORM_WB_TR_RWA ULL(0x7)
1054#define MAIR_NORM_WT_NTR_NA ULL(0x8)
1055#define MAIR_NORM_WT_NTR_WA ULL(0x9)
1056#define MAIR_NORM_WT_NTR_RA ULL(0xa)
1057#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1058#define MAIR_NORM_WB_NTR_NA ULL(0xc)
1059#define MAIR_NORM_WB_NTR_WA ULL(0xd)
1060#define MAIR_NORM_WB_NTR_RA ULL(0xe)
1061#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1062
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001063#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +01001064
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001065#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
1066 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +01001067
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001068/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001069#define PAR_F_SHIFT U(0)
1070#define PAR_F_MASK ULL(0x1)
1071#define PAR_ADDR_SHIFT U(12)
1072#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001073
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01001074/*******************************************************************************
1075 * Definitions for system register interface to SPE
1076 ******************************************************************************/
1077#define PMBLIMITR_EL1 S3_0_C9_C10_0
1078
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001079/*******************************************************************************
Rohit Mathew3dc3cad2022-11-11 18:45:11 +00001080 * Definitions for system register interface, shifts and masks for MPAM
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001081 ******************************************************************************/
1082#define MPAMIDR_EL1 S3_0_C10_C4_4
1083#define MPAM2_EL2 S3_4_C10_C5_0
1084#define MPAMHCR_EL2 S3_4_C10_C4_0
1085#define MPAM3_EL3 S3_6_C10_C5_0
1086
Andre Przywara84b86532022-11-17 16:42:09 +00001087#define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18)
1088#define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001089/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001090 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001091 ******************************************************************************/
1092#define AMCR_EL0 S3_3_C13_C2_0
1093#define AMCFGR_EL0 S3_3_C13_C2_1
1094#define AMCGCR_EL0 S3_3_C13_C2_2
1095#define AMUSERENR_EL0 S3_3_C13_C2_3
1096#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
1097#define AMCNTENSET0_EL0 S3_3_C13_C2_5
1098#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
1099#define AMCNTENSET1_EL0 S3_3_C13_C3_1
1100
1101/* Activity Monitor Group 0 Event Counter Registers */
1102#define AMEVCNTR00_EL0 S3_3_C13_C4_0
1103#define AMEVCNTR01_EL0 S3_3_C13_C4_1
1104#define AMEVCNTR02_EL0 S3_3_C13_C4_2
1105#define AMEVCNTR03_EL0 S3_3_C13_C4_3
1106
1107/* Activity Monitor Group 0 Event Type Registers */
1108#define AMEVTYPER00_EL0 S3_3_C13_C6_0
1109#define AMEVTYPER01_EL0 S3_3_C13_C6_1
1110#define AMEVTYPER02_EL0 S3_3_C13_C6_2
1111#define AMEVTYPER03_EL0 S3_3_C13_C6_3
1112
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001113/* Activity Monitor Group 1 Event Counter Registers */
1114#define AMEVCNTR10_EL0 S3_3_C13_C12_0
1115#define AMEVCNTR11_EL0 S3_3_C13_C12_1
1116#define AMEVCNTR12_EL0 S3_3_C13_C12_2
1117#define AMEVCNTR13_EL0 S3_3_C13_C12_3
1118#define AMEVCNTR14_EL0 S3_3_C13_C12_4
1119#define AMEVCNTR15_EL0 S3_3_C13_C12_5
1120#define AMEVCNTR16_EL0 S3_3_C13_C12_6
1121#define AMEVCNTR17_EL0 S3_3_C13_C12_7
1122#define AMEVCNTR18_EL0 S3_3_C13_C13_0
1123#define AMEVCNTR19_EL0 S3_3_C13_C13_1
1124#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
1125#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
1126#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
1127#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
1128#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
1129#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
1130
1131/* Activity Monitor Group 1 Event Type Registers */
1132#define AMEVTYPER10_EL0 S3_3_C13_C14_0
1133#define AMEVTYPER11_EL0 S3_3_C13_C14_1
1134#define AMEVTYPER12_EL0 S3_3_C13_C14_2
1135#define AMEVTYPER13_EL0 S3_3_C13_C14_3
1136#define AMEVTYPER14_EL0 S3_3_C13_C14_4
1137#define AMEVTYPER15_EL0 S3_3_C13_C14_5
1138#define AMEVTYPER16_EL0 S3_3_C13_C14_6
1139#define AMEVTYPER17_EL0 S3_3_C13_C14_7
1140#define AMEVTYPER18_EL0 S3_3_C13_C15_0
1141#define AMEVTYPER19_EL0 S3_3_C13_C15_1
1142#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
1143#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
1144#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
1145#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
1146#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
1147#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
1148
Chris Kaya5fde282021-05-26 11:58:23 +01001149/* AMCNTENSET0_EL0 definitions */
1150#define AMCNTENSET0_EL0_Pn_SHIFT U(0)
1151#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1152
1153/* AMCNTENSET1_EL0 definitions */
1154#define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1155#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1156
1157/* AMCNTENCLR0_EL0 definitions */
1158#define AMCNTENCLR0_EL0_Pn_SHIFT U(0)
1159#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1160
1161/* AMCNTENCLR1_EL0 definitions */
1162#define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1163#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1164
Alexei Fedorov7e6306b2020-07-14 08:17:56 +01001165/* AMCFGR_EL0 definitions */
1166#define AMCFGR_EL0_NCG_SHIFT U(28)
1167#define AMCFGR_EL0_NCG_MASK U(0xf)
1168#define AMCFGR_EL0_N_SHIFT U(0)
1169#define AMCFGR_EL0_N_MASK U(0xff)
1170
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001171/* AMCGCR_EL0 definitions */
Chris Kaya40141d2021-05-25 12:33:18 +01001172#define AMCGCR_EL0_CG0NC_SHIFT U(0)
1173#define AMCGCR_EL0_CG0NC_MASK U(0xff)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001174#define AMCGCR_EL0_CG1NC_SHIFT U(8)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001175#define AMCGCR_EL0_CG1NC_MASK U(0xff)
1176
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001177/* MPAM register definitions */
1178#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001179#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1180
1181#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1182#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001183
1184#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1185
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001186/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001187 * Definitions for system register interface to AMU for FEAT_AMUv1p1
1188 ******************************************************************************/
1189
1190/* Definition for register defining which virtual offsets are implemented. */
1191#define AMCG1IDR_EL0 S3_3_C13_C2_6
1192#define AMCG1IDR_CTR_MASK ULL(0xffff)
1193#define AMCG1IDR_CTR_SHIFT U(0)
1194#define AMCG1IDR_VOFF_MASK ULL(0xffff)
1195#define AMCG1IDR_VOFF_SHIFT U(16)
1196
1197/* New bit added to AMCR_EL0 */
Chris Kaya5fde282021-05-26 11:58:23 +01001198#define AMCR_CG1RZ_SHIFT U(17)
1199#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)
johpow01fa59c6f2020-10-02 13:41:11 -05001200
1201/*
1202 * Definitions for virtual offset registers for architected activity monitor
1203 * event counters.
1204 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
1205 */
1206#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
1207#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
1208#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
1209
1210/*
1211 * Definitions for virtual offset registers for auxiliary activity monitor event
1212 * counters.
1213 */
1214#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
1215#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
1216#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
1217#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
1218#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
1219#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
1220#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
1221#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
1222#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
1223#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
1224#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
1225#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
1226#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
1227#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
1228#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
1229#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
1230
1231/*******************************************************************************
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001232 * Realm management extension register definitions
1233 ******************************************************************************/
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001234#define GPCCR_EL3 S3_6_C2_C1_6
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001235#define GPTBR_EL3 S3_6_C2_C1_4
1236
Andre Przywara3edbfa72023-03-28 16:55:06 +01001237#define SCXTNUM_EL2 S3_4_C13_C0_7
1238
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001239/*******************************************************************************
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001240 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +00001241 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001242#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001243#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001244
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001245#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001246#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001247
1248#define ERRSELR_EL1 S3_0_C5_C3_1
1249
1250/* System register access to Standard Error Record registers */
1251#define ERXFR_EL1 S3_0_C5_C4_0
1252#define ERXCTLR_EL1 S3_0_C5_C4_1
1253#define ERXSTATUS_EL1 S3_0_C5_C4_2
1254#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001255#define ERXPFGF_EL1 S3_0_C5_C4_4
1256#define ERXPFGCTL_EL1 S3_0_C5_C4_5
1257#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +02001258#define ERXMISC0_EL1 S3_0_C5_C5_0
1259#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001260
johpow017d52a8f2022-03-09 16:23:04 -06001261#define ERXCTLR_ED_SHIFT U(0)
1262#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001263#define ERXCTLR_UE_BIT (U(1) << 4)
1264
1265#define ERXPFGCTL_UC_BIT (U(1) << 1)
1266#define ERXPFGCTL_UEU_BIT (U(1) << 2)
1267#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1268
1269/*******************************************************************************
1270 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +00001271 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001272#define APIAKeyLo_EL1 S3_0_C2_C1_0
1273#define APIAKeyHi_EL1 S3_0_C2_C1_1
1274#define APIBKeyLo_EL1 S3_0_C2_C1_2
1275#define APIBKeyHi_EL1 S3_0_C2_C1_3
1276#define APDAKeyLo_EL1 S3_0_C2_C2_0
1277#define APDAKeyHi_EL1 S3_0_C2_C2_1
1278#define APDBKeyLo_EL1 S3_0_C2_C2_2
1279#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001280#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001281#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001282
Sathees Balya0911df12018-12-06 13:33:24 +00001283/*******************************************************************************
1284 * Armv8.4 Data Independent Timing Registers
1285 ******************************************************************************/
1286#define DIT S3_3_C4_C2_5
1287#define DIT_BIT BIT(24)
1288
John Tsichritzis1f9ff492019-03-04 16:41:26 +00001289/*******************************************************************************
1290 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1291 ******************************************************************************/
1292#define SSBS S3_3_C4_C2_6
1293
Justin Chadwell1c7c13a2019-07-18 14:25:33 +01001294/*******************************************************************************
1295 * Armv8.5 - Memory Tagging Extension Registers
1296 ******************************************************************************/
1297#define TFSRE0_EL1 S3_0_C5_C6_1
1298#define TFSR_EL1 S3_0_C5_C6_0
1299#define RGSR_EL1 S3_0_C1_C0_5
1300#define GCR_EL1 S3_0_C1_C0_6
1301
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001302/*******************************************************************************
Andre Przywarabdc76f12022-11-21 17:07:25 +00001303 * Armv8.5 - Random Number Generator Registers
1304 ******************************************************************************/
1305#define RNDR S3_3_C2_C4_0
1306#define RNDRRS S3_3_C2_C4_1
1307
1308/*******************************************************************************
johpow01f91e59f2021-08-04 19:38:18 -05001309 * FEAT_HCX - Extended Hypervisor Configuration Register
1310 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -05001311#define HCRX_EL2 S3_4_C1_C2_2
1312#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4)
1313#define HCRX_EL2_FnXS_BIT (UL(1) << 3)
1314#define HCRX_EL2_EnASR_BIT (UL(1) << 2)
1315#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
1316#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
johpow01f91e59f2021-08-04 19:38:18 -05001317
1318/*******************************************************************************
Mark Brownc37eee72023-03-14 20:13:03 +00001319 * FEAT_TCR2 - Extended Translation Control Register
1320 ******************************************************************************/
1321#define TCR2_EL2 S3_4_C2_C0_3
1322
1323/*******************************************************************************
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001324 * Definitions for DynamicIQ Shared Unit registers
1325 ******************************************************************************/
1326#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
1327
1328/* CLUSTERPWRDN_EL1 register definitions */
1329#define DSU_CLUSTER_PWR_OFF 0
1330#define DSU_CLUSTER_PWR_ON 1
1331#define DSU_CLUSTER_PWR_MASK U(1)
1332
Chris Kay03be39d2021-05-05 13:38:30 +01001333/*******************************************************************************
1334 * Definitions for CPU Power/Performance Management registers
1335 ******************************************************************************/
1336
1337#define CPUPPMCR_EL3 S3_6_C15_C2_0
1338#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0)
1339#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1)
1340
1341#define CPUMPMMCR_EL3 S3_6_C15_C2_1
1342#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
1343#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
1344
Andre Przywarac735f1c2022-11-25 14:10:13 +00001345/* alternative system register encoding for the "sb" speculation barrier */
1346#define SYSREG_SB S0_3_C3_C0_7
1347
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01001348#endif /* ARCH_H */