Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
Manish Pandey | 3880a36 | 2020-01-24 11:54:44 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 7 | #ifndef NEOVERSE_N1_H |
| 8 | #define NEOVERSE_N1_H |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 11 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 12 | /* Neoverse N1 MIDR for revision 0 */ |
| 13 | #define NEOVERSE_N1_MIDR U(0x410fd0c0) |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 14 | |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 15 | /* Exception Syndrome register EC code for IC Trap */ |
| 16 | #define NEOVERSE_N1_EC_IC_TRAP U(0x1f) |
| 17 | |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 18 | /******************************************************************************* |
Louis Mayencourt | b58142b | 2019-04-18 14:34:11 +0100 | [diff] [blame] | 19 | * CPU Power Control register specific definitions. |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 20 | ******************************************************************************/ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 21 | #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 22 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 23 | /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ |
| 24 | #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 25 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 26 | #define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4) |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 27 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 28 | #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) |
| 29 | #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 30 | |
Louis Mayencourt | b58142b | 2019-04-18 14:34:11 +0100 | [diff] [blame] | 31 | /******************************************************************************* |
| 32 | * CPU Extended Control register specific definitions. |
| 33 | ******************************************************************************/ |
| 34 | #define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 35 | |
lauwal01 | 197f14c | 2019-06-24 11:38:53 -0500 | [diff] [blame] | 36 | #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) |
lauwal01 | 00396bf | 2019-06-24 11:47:30 -0500 | [diff] [blame] | 37 | #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) |
Manish Pandey | 3880a36 | 2020-01-24 11:54:44 +0000 | [diff] [blame] | 38 | #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) |
lauwal01 | 197f14c | 2019-06-24 11:38:53 -0500 | [diff] [blame] | 39 | |
Louis Mayencourt | b58142b | 2019-04-18 14:34:11 +0100 | [diff] [blame] | 40 | /******************************************************************************* |
| 41 | * CPU Auxiliary Control register specific definitions. |
| 42 | ******************************************************************************/ |
lauwal01 | bd555f4 | 2019-06-24 11:23:50 -0500 | [diff] [blame] | 43 | #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 44 | |
| 45 | #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) |
lauwal01 | 42771af | 2019-06-24 11:44:58 -0500 | [diff] [blame] | 46 | #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) |
lauwal01 | bd555f4 | 2019-06-24 11:23:50 -0500 | [diff] [blame] | 47 | |
Louis Mayencourt | b58142b | 2019-04-18 14:34:11 +0100 | [diff] [blame] | 48 | #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 49 | |
lauwal01 | f2adb13 | 2019-06-24 11:32:40 -0500 | [diff] [blame] | 50 | #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 51 | #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) |
lauwal01 | e159044 | 2019-06-24 11:35:37 -0500 | [diff] [blame] | 52 | #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) |
lauwal01 | f2adb13 | 2019-06-24 11:32:40 -0500 | [diff] [blame] | 53 | #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 54 | #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) |
lauwal01 | 363ee3c | 2019-06-24 11:28:34 -0500 | [diff] [blame] | 55 | #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) |
| 56 | |
lauwal01 | 07c2a23 | 2019-06-24 11:42:02 -0500 | [diff] [blame] | 57 | #define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2 |
| 58 | |
| 59 | #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) |
Louis Mayencourt | b58142b | 2019-04-18 14:34:11 +0100 | [diff] [blame] | 60 | |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 61 | /* Instruction patching registers */ |
| 62 | #define CPUPSELR_EL3 S3_6_C15_C8_0 |
| 63 | #define CPUPCR_EL3 S3_6_C15_C8_1 |
| 64 | #define CPUPOR_EL3 S3_6_C15_C8_2 |
| 65 | #define CPUPMR_EL3 S3_6_C15_C8_3 |
| 66 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 67 | #endif /* NEOVERSE_N1_H */ |