| commit | 42771afa7b2f9d63515b3b0a723fbfc8d5b7b1f7 | [log] [tgz] |
|---|---|---|
| author | lauwal01 <lauren.wehrmeister@arm.com> | Mon Jun 24 11:44:58 2019 -0500 |
| committer | lauwal01 <lauren.wehrmeister@arm.com> | Tue Jul 02 09:16:54 2019 -0500 |
| tree | 1ed19f9f44816e4c7fdaafb00457b5d51361e0d3 | |
| parent | 07c2a23fd12df77ea88d379364508da6ecc8fb2b [diff] [blame] |
Workaround for Neoverse N1 erratum 1262606 Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 0e9ddb8..8f0ecf2 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -38,6 +38,7 @@ #define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1