| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
| Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 7 | #ifndef CORTEX_ARES_H |
| 8 | #define CORTEX_ARES_H |
| 9 | |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame^] | 10 | #include <lib/utils_def.h> |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 11 | |
| 12 | /* Cortex-ARES MIDR for revision 0 */ |
| Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 13 | #define CORTEX_ARES_MIDR U(0x410fd0c0) |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 19 | #define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 20 | |
| 21 | /* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ |
| Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 22 | #define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1) |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 23 | |
| Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 24 | #define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) |
| 25 | |
| 26 | #define CORTEX_ARES_AMU_NR_COUNTERS U(5) |
| 27 | #define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) |
| 28 | |
| Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 29 | /* Instruction patching registers */ |
| 30 | #define CPUPSELR_EL3 S3_6_C15_C8_0 |
| 31 | #define CPUPCR_EL3 S3_6_C15_C8_1 |
| 32 | #define CPUPOR_EL3 S3_6_C15_C8_2 |
| 33 | #define CPUPMR_EL3 S3_6_C15_C8_3 |
| 34 | |
| Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 35 | #endif /* CORTEX_ARES_H */ |