commit 197f14cffcc6af58e5464027e347df4d79a6de87
author lauwal01 <lauren.wehrmeister@arm.com> Mon Jun 24 11:38:53 2019 -0500
committer lauwal01 <lauren.wehrmeister@arm.com> Tue Jul 02 09:16:10 2019 -0500
tree c0d19c0446266b7ac3d4a6fb5df0132140e0c334
parent e159044483980a26b7ebdee6c4b1d34b0373468d

Workaround for Neoverse N1 erratum 1220197

Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

include/lib/cpus/aarch64/neoverse_n1.h

diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index 8925827..952ae6e 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -30,6 +30,8 @@
  ******************************************************************************/
 #define NEOVERSE_N1_CPUECTLR_EL1	S3_0_C15_C1_4
 
+#define NEOVERSE_N1_WS_THR_L2_MASK	(ULL(3) << 24)
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/