| commit | 363ee3cb547b3249ae52f0673965f9aeea9b5597 | [log] [tgz] |
|---|---|---|
| author | lauwal01 <lauren.wehrmeister@arm.com> | Mon Jun 24 11:28:34 2019 -0500 |
| committer | lauwal01 <lauren.wehrmeister@arm.com> | Tue Jul 02 09:14:54 2019 -0500 |
| tree | 0838213c1b952a10706c0198187a124f36a802a7 | |
| parent | bd555f4610aa49a7956b31820d744750c1210479 [diff] [blame] |
Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9048f43..9042d70 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -41,6 +41,8 @@ #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0