| commit | f2adb13549b38e930864cc04ece5c9cf6c8e2a4c | [log] [tgz] |
|---|---|---|
| author | lauwal01 <lauren.wehrmeister@arm.com> | Mon Jun 24 11:32:40 2019 -0500 |
| committer | lauwal01 <lauren.wehrmeister@arm.com> | Tue Jul 02 09:15:15 2019 -0500 |
| tree | 2df7811cdcf4159d4c36de40a65b57ed825e4811 | |
| parent | 363ee3cb547b3249ae52f0673965f9aeea9b5597 [diff] [blame] |
Workaround for Neoverse N1 erratum 1165347 Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9042d70..7950cd2 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -39,7 +39,9 @@ #define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)