Workaround for Neoverse N1 erratum 1073348
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index b66aeb8..9048f43 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -33,6 +33,10 @@
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
+#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0
+
+#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
+
#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)