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Ryan Harkin25cff832014-01-13 12:37:03 +00001#
Madhukar Pappireddye17c82a2024-01-10 14:01:37 -06002# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
Ryan Harkin25cff832014-01-13 12:37:03 +00003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Ryan Harkin25cff832014-01-13 12:37:03 +00005#
6
Chris Kaye9272152021-09-28 15:52:14 +01007include common/fdt_wrappers.mk
8
Soby Mathewb6f3b1f2016-04-07 17:40:04 +01009# Use the GICv3 driver on the FVP by default
10FVP_USE_GIC_DRIVER := FVP_GICV3
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000011
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000012# Default cluster count for FVP
13FVP_CLUSTER_COUNT := 2
14
Jeenu Viswambharan75421132018-01-31 14:52:08 +000015# Default number of CPUs per cluster on FVP
16FVP_MAX_CPUS_PER_CLUSTER := 4
17
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000018# Default number of threads per CPU on FVP
19FVP_MAX_PE_PER_CPU := 1
20
Manish V Badarkheb24c6372021-01-24 03:26:50 +000021# Disable redistributor frame of inactive/fused CPU cores by marking it as read
22# only; enable redistributor frames of all CPU cores by default.
23FVP_GICR_REGION_PROTECTION := 0
24
Soby Mathew5f6412a2018-02-08 11:39:38 +000025FVP_DT_PREFIX := fvp-base-gicv3-psci
26
Chris Kay91dd2532023-06-05 17:22:54 +010027# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
28# the FVP platform. This option defaults to 256.
29FVP_TRUSTED_SRAM_SIZE := 256
30
Madhukar Pappireddy3b228e12023-08-24 16:57:22 -050031# Macro to enable helpers for running SPM tests. Disabled by default.
32PLAT_TEST_SPM := 0
33
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010034# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's
35# progbits limit. We need a way to build all useful configurations while waiting
36# on the fvp to increase its SRAM size. The problem is twofild:
37# 1. the cleanup that introduced these enables cleaned up tf-a a little too
38# well and things that previously (incorrectly) were enabled, no longer are.
39# A bunch of CI configs build subtly incorrectly and this combo makes it
40# necessary to forcefully and unconditionally enable them here.
41# 2. the progbits limit is exceeded only when the tsp is involved. However,
42# there are tsp CI configs that run on very high architecture revisions so
43# disabling everything isn't an option.
44# The fix is to enable everything, as before. When the tsp is included, though,
45# we need to slim the size down. In that case, disable all optional features,
46# that will not be present in CI when the tsp is.
Boyan Karatotev7b7bc132023-04-04 14:48:04 +010047# Similarly, DRTM support is only tested on v8.0 models. Disable everything just
48# for it.
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010049# TODO: make all of this unconditional (or only base the condition on
50# ARM_ARCH_* when the makefile supports it).
Boyan Karatotev7b7bc132023-04-04 14:48:04 +010051ifneq (${DRTM_SUPPORT}, 1)
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010052ifneq (${SPD}, tspd)
53 ENABLE_FEAT_AMU := 2
54 ENABLE_FEAT_AMUv1p1 := 2
55 ENABLE_FEAT_HCX := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010056 ENABLE_FEAT_RNG := 2
57 ENABLE_FEAT_TWED := 2
Mark Brown326f2952023-03-14 21:33:04 +000058 ENABLE_FEAT_GCS := 2
Jayanth Dodderi Chidanandc8395cf2023-04-28 15:14:27 +010059ifeq (${ARCH}, aarch64)
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010060ifeq (${SPM_MM}, 0)
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010061ifeq (${CTX_INCLUDE_FPREGS}, 0)
62 ENABLE_SME_FOR_NS := 2
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +000063 ENABLE_SME2_FOR_NS := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010064endif
65endif
66endif
67endif
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010068
69# enable unconditionally for all builds
70ifeq (${ARCH}, aarch64)
Govindraj Raja60f52662023-10-12 16:57:46 -050071 ENABLE_BRBE_FOR_NS := 2
Govindraj Raja28b525c2023-09-20 15:31:45 -050072 ENABLE_TRBE_FOR_NS := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010073endif
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010074ENABLE_SYS_REG_TRACE_FOR_NS := 2
75ENABLE_FEAT_CSV2_2 := 2
Sona Mathew3b84c962023-10-25 16:48:19 -050076ENABLE_FEAT_CSV2_3 := 2
Andre Przywara1f55c412023-01-26 16:47:52 +000077ENABLE_FEAT_DIT := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010078ENABLE_FEAT_PAN := 2
Maksims Svecovsdf4ad842023-03-24 13:05:09 +000079ENABLE_FEAT_MTE_PERM := 2
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010080ENABLE_FEAT_VHE := 2
81CTX_INCLUDE_NEVE_REGS := 2
82ENABLE_FEAT_SEL2 := 2
83ENABLE_TRF_FOR_NS := 2
84ENABLE_FEAT_ECV := 2
85ENABLE_FEAT_FGT := 2
86ENABLE_FEAT_TCR2 := 2
Mark Brown293a6612023-03-14 20:48:43 +000087ENABLE_FEAT_S2PIE := 2
88ENABLE_FEAT_S1PIE := 2
89ENABLE_FEAT_S2POE := 2
90ENABLE_FEAT_S1POE := 2
Boyan Karatotev7b7bc132023-04-04 14:48:04 +010091endif
Boyan Karatotev3e0e7892023-03-30 14:56:45 +010092
Achin Gupta1fa7eb62015-11-03 14:18:34 +000093# The FVP platform depends on this macro to build with correct GIC driver.
94$(eval $(call add_define,FVP_USE_GIC_DRIVER))
95
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000096# Pass FVP_CLUSTER_COUNT to the build system.
Soby Mathew47e43f22016-02-01 14:04:34 +000097$(eval $(call add_define,FVP_CLUSTER_COUNT))
Soby Mathew7356b1e2016-03-24 10:12:42 +000098
Jeenu Viswambharan75421132018-01-31 14:52:08 +000099# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system.
100$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER))
101
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000102# Pass FVP_MAX_PE_PER_CPU to the build system.
103$(eval $(call add_define,FVP_MAX_PE_PER_CPU))
104
Manish V Badarkheb24c6372021-01-24 03:26:50 +0000105# Pass FVP_GICR_REGION_PROTECTION to the build system.
106$(eval $(call add_define,FVP_GICR_REGION_PROTECTION))
107
Chris Kay91dd2532023-06-05 17:22:54 +0100108# Pass FVP_TRUSTED_SRAM_SIZE to the build system.
109$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE))
110
Soby Mathew7356b1e2016-03-24 10:12:42 +0000111# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2,
112# choose the CCI driver , else the CCN driver
113ifeq ($(FVP_CLUSTER_COUNT), 0)
114$(error "Incorrect cluster count specified for FVP port")
115else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2))
116FVP_INTERCONNECT_DRIVER := FVP_CCI
117else
118FVP_INTERCONNECT_DRIVER := FVP_CCN
Soby Mathew47e43f22016-02-01 14:04:34 +0000119endif
120
Soby Mathew7356b1e2016-03-24 10:12:42 +0000121$(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
122
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000123# Choose the GIC sources depending upon the how the FVP will be invoked
Andre Przywarae1cc1302020-03-25 15:50:38 +0000124ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000125
Andre Przywarae1cc1302020-03-25 15:50:38 +0000126# The GIC model (GIC-600 or GIC-500) will be detected at runtime
127GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000128GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
129
130# Include GICv3 driver files
131include drivers/arm/gic/v3/gicv3.mk
132
133FVP_GIC_SOURCES := ${GICV3_SOURCES} \
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000134 plat/common/plat_gicv3.c \
135 plat/arm/common/arm_gicv3.c
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000136
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600137 ifeq ($(filter 1,${RESET_TO_BL2} \
138 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
laurenw-armdc5e9a22020-05-12 10:58:11 -0500139 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
140 endif
141
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000142else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +0100143
144# No GICv4 extension
145GIC_ENABLE_V4_EXTN := 0
146$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
147
Alexei Fedorovcaa18022020-07-14 10:47:25 +0100148# Include GICv2 driver files
149include drivers/arm/gic/v2/gicv2.mk
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +0100150
Alexei Fedorovcaa18022020-07-14 10:47:25 +0100151FVP_GIC_SOURCES := ${GICV2_SOURCES} \
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000152 plat/common/plat_gicv2.c \
153 plat/arm/common/arm_gicv2.c
Soby Mathew5f6412a2018-02-08 11:39:38 +0000154
155FVP_DT_PREFIX := fvp-base-gicv2-psci
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000156else
157$(error "Incorrect GIC driver chosen on FVP port")
158endif
159
Soby Mathew7356b1e2016-03-24 10:12:42 +0000160ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI)
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100161FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
Soby Mathew7356b1e2016-03-24 10:12:42 +0000162else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN)
163FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
164 plat/arm/common/arm_ccn.c
165else
166$(error "Incorrect CCN driver chosen on FVP port")
167endif
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000168
Soby Mathew9c708b52016-02-26 14:23:19 +0000169FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000170 plat/arm/board/fvp/fvp_security.c \
171 plat/arm/common/arm_tzc400.c
172
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000173
Manish V Badarkhe7ac59582023-03-24 08:22:33 +0000174PLAT_INCLUDES := -Iplat/arm/board/fvp/include \
175 -Iinclude/lib/psa
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100176
Ryan Harkin25cff832014-01-13 12:37:03 +0000177
Soby Mathewcc037c12016-04-08 16:42:58 +0100178PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
Ryan Harkin25cff832014-01-13 12:37:03 +0000179
Soby Mathew0d268dc2016-07-11 14:13:56 +0100180FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
181
182ifeq (${ARCH}, aarch64)
John Tsichritzisfe6df392019-03-19 17:20:52 +0000183
John Tsichritzis7557c662019-06-03 13:54:30 +0100184# select a different set of CPU files, depending on whether we compile for
185# hardware assisted coherency cores or not
John Tsichritzisfe6df392019-03-19 17:20:52 +0000186ifeq (${HW_ASSISTED_COHERENCY}, 0)
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100187# Cores used without DSU
John Tsichritzisfe6df392019-03-19 17:20:52 +0000188 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
Soby Mathewc704cbc2014-08-14 11:33:56 +0100189 lib/cpus/aarch64/cortex_a53.S \
190 lib/cpus/aarch64/cortex_a57.S \
Yatharth Kochar63af6872016-02-09 12:00:03 +0000191 lib/cpus/aarch64/cortex_a72.S \
John Tsichritzisfe6df392019-03-19 17:20:52 +0000192 lib/cpus/aarch64/cortex_a73.S
193else
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100194# Cores used with DSU only
John Tsichritzis7557c662019-06-03 13:54:30 +0100195 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100196 # AArch64-only cores
Boyan Karatotevf154cbd2023-04-06 10:31:09 +0100197 # TODO: add all cores to the appropriate lists
198 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \
199 lib/cpus/aarch64/cortex_a65ae.S \
200 lib/cpus/aarch64/cortex_a76.S \
John Tsichritzis7557c662019-06-03 13:54:30 +0100201 lib/cpus/aarch64/cortex_a76ae.S \
Balint Dobszaycc942642019-07-03 13:02:56 +0200202 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson7ec175e2020-06-01 16:49:34 -0500203 lib/cpus/aarch64/cortex_a78.S \
Juan Pablo Condef4a70f22023-05-24 22:08:28 -0500204 lib/cpus/aarch64/cortex_a78_ae.S \
Boyan Karatotevf154cbd2023-04-06 10:31:09 +0100205 lib/cpus/aarch64/cortex_a78c.S \
206 lib/cpus/aarch64/cortex_a710.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100207 lib/cpus/aarch64/neoverse_n_common.S \
John Tsichritzis7557c662019-06-03 13:54:30 +0100208 lib/cpus/aarch64/neoverse_n1.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100209 lib/cpus/aarch64/neoverse_n2.S \
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500210 lib/cpus/aarch64/neoverse_v1.S \
Boyan Karatotevf154cbd2023-04-06 10:31:09 +0100211 lib/cpus/aarch64/neoverse_e1.S \
Juan Pablo Condec9fe7ce2023-07-05 11:57:50 -0500212 lib/cpus/aarch64/cortex_x2.S \
Juan Pablo Conde49f70662023-07-06 15:38:59 -0500213 lib/cpus/aarch64/cortex_gelas.S \
Juan Pablo Conde16d31082023-09-19 14:57:29 -0500214 lib/cpus/aarch64/nevis.S \
215 lib/cpus/aarch64/travis.S
John Tsichritzis7557c662019-06-03 13:54:30 +0100216 endif
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100217 # AArch64/AArch32 cores
218 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
219 lib/cpus/aarch64/cortex_a75.S
John Tsichritzisfe6df392019-03-19 17:20:52 +0000220endif
John Tsichritzis6deaf9c2018-10-08 17:09:43 +0100221
Yatharth Kochara4c219a2016-07-12 15:47:03 +0100222else
Boyan Karatotevf3581342023-01-27 10:58:42 +0000223FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
Jayanth Dodderi Chidanand5d478412023-05-09 14:12:48 +0100224 lib/cpus/aarch32/cortex_a57.S \
225 lib/cpus/aarch32/cortex_a53.S
Soby Mathew0d268dc2016-07-11 14:13:56 +0100226endif
Sandrine Bailleuxdd505792016-01-13 09:04:26 +0000227
Alexei Fedorov896799a2019-05-09 12:14:40 +0100228BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
229 drivers/arm/sp805/sp805.c \
Alexei Fedorov7131d832019-08-16 14:15:59 +0100230 drivers/delay_timer/delay_timer.c \
Aditya Angadi20b48412019-04-16 11:29:14 +0530231 drivers/io/io_semihosting.c \
Dan Handley2b6b5742015-03-19 19:17:53 +0000232 lib/semihosting/semihosting.c \
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100233 lib/semihosting/${ARCH}/semihosting_call.S \
234 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
Dan Handleyd617f662015-04-27 19:17:18 +0100235 plat/arm/board/fvp/fvp_bl1_setup.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100236 plat/arm/board/fvp/fvp_err.c \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000237 plat/arm/board/fvp/fvp_io_storage.c \
238 ${FVP_CPU_LIBS} \
239 ${FVP_INTERCONNECT_SOURCES}
240
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500241ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100242BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
243else
244BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c
245endif
246
Ryan Harkin25cff832014-01-13 12:37:03 +0000247
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100248BL2_SOURCES += drivers/arm/sp805/sp805.c \
249 drivers/io/io_semihosting.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100250 lib/utils/mem_region.c \
Dan Handley2b6b5742015-03-19 19:17:53 +0000251 lib/semihosting/semihosting.c \
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100252 lib/semihosting/${ARCH}/semihosting_call.S \
Dan Handleyd617f662015-04-27 19:17:18 +0100253 plat/arm/board/fvp/fvp_bl2_setup.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100254 plat/arm/board/fvp/fvp_err.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100255 plat/arm/board/fvp/fvp_io_storage.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100256 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000257 ${FVP_SECURITY_SOURCES}
Ryan Harkin25cff832014-01-13 12:37:03 +0000258
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100259
Manish V Badarkhe09a192c2020-08-23 09:58:44 +0100260ifeq (${COT_DESC_IN_DTB},1)
261BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c
262endif
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100263
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500264ifeq (${ENABLE_RME},1)
265BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S
Manish V Badarkhe37f9ac22023-03-12 21:34:44 +0000266
Soby Mathewf05d93a2022-03-22 16:21:19 +0000267BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \
268 plat/arm/board/fvp/fvp_realm_attest_key.c
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500269endif
270
Andre Przywarabdc76f12022-11-21 17:07:25 +0000271ifeq (${ENABLE_FEAT_RNG_TRAP},1)
272BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c
273endif
274
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600275ifeq (${RESET_TO_BL2},1)
Roberto Vargas52207802017-11-17 13:22:18 +0000276BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
277 plat/arm/board/fvp/fvp_bl2_el3_setup.c \
278 ${FVP_CPU_LIBS} \
279 ${FVP_INTERCONNECT_SOURCES}
280endif
281
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500282ifeq (${USE_SP804_TIMER},1)
Antonio Nino Diaz664adb62016-05-17 09:48:10 +0100283BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
Antonio Nino Diaz664adb62016-05-17 09:48:10 +0100284endif
285
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100286BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000287 ${FVP_SECURITY_SOURCES}
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100288
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500289ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100290BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
291endif
292
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +0000293BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
294 drivers/arm/smmu/smmu_v3.c \
Alexei Fedorov7131d832019-08-16 14:15:59 +0100295 drivers/delay_timer/delay_timer.c \
Antonio Nino Diazd7da2f82018-10-10 11:14:44 +0100296 drivers/cfi/v2m/v2m_flash.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100297 lib/utils/mem_region.c \
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100298 plat/arm/board/fvp/fvp_bl31_setup.c \
Madhukar Pappireddyd0cf0a92020-04-16 17:54:25 -0500299 plat/arm/board/fvp/fvp_console.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100300 plat/arm/board/fvp/fvp_pm.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100301 plat/arm/board/fvp/fvp_topology.c \
302 plat/arm/board/fvp/aarch64/fvp_helpers.S \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100303 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000304 ${FVP_CPU_LIBS} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000305 ${FVP_GIC_SOURCES} \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000306 ${FVP_INTERCONNECT_SOURCES} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000307 ${FVP_SECURITY_SOURCES}
Juan Castillo5e29c752015-01-07 10:39:25 +0000308
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600309# Support for fconf in BL31
310# Added separately from the above list for better readability
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600311ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
Chris Kaye9272152021-09-28 15:52:14 +0100312BL31_SOURCES += lib/fconf/fconf.c \
Manish V Badarkhe8717e032020-05-30 17:40:44 +0100313 lib/fconf/fconf_dyn_cfg_getter.c \
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600314 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500315
Chris Kaye9272152021-09-28 15:52:14 +0100316BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
317
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500318ifeq (${SEC_INT_DESC_IN_FCONF},1)
319BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c
320endif
321
Madhukar Pappireddyaa1121f2020-03-13 13:00:17 -0500322endif
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600323
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500324ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100325BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
326else
327BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
328endif
329
Soby Mathewa684e582018-02-27 11:17:14 +0000330# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
331ifdef UNIX_MK
Soby Mathew5f6412a2018-02-08 11:39:38 +0000332FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts
Soby Mathewb6814842018-04-04 09:40:32 +0100333FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000334 ${PLAT}_fw_config.dts \
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100335 ${PLAT}_tb_fw_config.dts \
Soby Mathewb6814842018-04-04 09:40:32 +0100336 ${PLAT}_soc_fw_config.dts \
337 ${PLAT}_nt_fw_config.dts \
338 )
339
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100340FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
341FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Soby Mathewb6814842018-04-04 09:40:32 +0100342FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb
343FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
344
345ifeq (${SPD},tspd)
346FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts
347FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb
348
349# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100350$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100351endif
Soby Mathew5f6412a2018-02-08 11:39:38 +0000352
Harrison Mutai1dcaf962023-08-08 15:10:07 +0100353ifeq (${TRANSFER_LIST}, 1)
354include lib/transfer_list/transfer_list.mk
355endif
356
Achin Guptada6ef0e2019-10-11 14:54:48 +0100357ifeq (${SPD},spmd)
Olivier Deprezbcaa0682020-04-01 21:28:26 +0200358
359ifeq ($(ARM_SPMC_MANIFEST_DTS),)
360ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts
361endif
362
363FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
364FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
Achin Guptada6ef0e2019-10-11 14:54:48 +0100365
366# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100367$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Achin Guptada6ef0e2019-10-11 14:54:48 +0100368endif
369
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100370# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100371$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG}))
Soby Mathew5f6412a2018-02-08 11:39:38 +0000372# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100373$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100374# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100375$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100376# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100377$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG}))
Soby Mathew5f6412a2018-02-08 11:39:38 +0000378
379FDT_SOURCES += ${FVP_HW_CONFIG_DTS}
380$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
381
382# Add the HW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
Soby Mathewa684e582018-02-27 11:17:14 +0000384endif
Soby Mathew5f6412a2018-02-08 11:39:38 +0000385
Dimitris Papastamos756b8dc2018-05-31 14:10:06 +0100386# Enable dynamic mitigation support by default
387DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
388
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000389ifneq (${ENABLE_FEAT_AMU},0)
John Tsichritzisfe6df392019-03-19 17:20:52 +0000390BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
Dimitris Papastamos0b00f8a2018-02-14 10:00:06 +0000391 lib/cpus/aarch64/cpuamu_helpers.S
John Tsichritzisfe6df392019-03-19 17:20:52 +0000392
393ifeq (${HW_ASSISTED_COHERENCY}, 1)
394BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
395 lib/cpus/aarch64/neoverse_n1_pubsub.c
396endif
Dimitris Papastamosd7e2e9e2017-12-11 11:45:35 +0000397endif
398
Manish Pandeyf90a73c2023-10-10 15:42:19 +0100399ifeq (${HANDLE_EA_EL3_FIRST_NS},1)
Madhukar Pappireddye17c82a2024-01-10 14:01:37 -0600400 ifeq (${ENABLE_FEAT_RAS},1)
401 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1)
402 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c
403 else
404 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
405 endif
406 else
407 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
408 endif
Jeenu Viswambharana490fe02018-06-08 08:44:36 +0100409endif
410
Douglas Raillard306593d2017-02-24 18:14:15 +0000411ifneq (${ENABLE_STACK_PROTECTOR},0)
412PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
413endif
414
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000415# Enable the dynamic translation tables library.
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600416ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000417 ifeq (${ARCH},aarch32)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900418 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Manish V Badarkhe86854e72022-03-15 16:05:58 +0000419 else # AArch64
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900420 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Antonio Nino Diaz60ef6752019-02-12 13:32:03 +0000421 endif
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000422endif
423
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000424ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
425 ifeq (${ARCH},aarch32)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900426 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000427 else # AArch64
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900428 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000429 ifeq (${SPD},tspd)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900430 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000431 endif
432 endif
433endif
434
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100435ifeq (${USE_DEBUGFS},1)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900436 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100437endif
438
Soby Mathew3b5156e2017-10-05 12:27:33 +0100439# Add support for platform supplied linker script for BL31 build
440$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
441
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600442ifneq (${RESET_TO_BL2}, 0)
Roberto Vargas9f412482018-01-16 10:35:23 +0000443 override BL1_SOURCES =
444endif
445
Juan Castillo31a68f02015-04-14 12:49:03 +0100446include plat/arm/board/common/board_common.mk
Dan Handley2b6b5742015-03-19 19:17:53 +0000447include plat/arm/common/arm_common.mk
Soby Mathew45e39e22018-03-26 15:16:46 +0100448
Alexei Fedorov61369a22020-07-13 14:59:02 +0100449ifeq (${MEASURED_BOOT},1)
Manish V Badarkhea74d9632021-09-14 23:12:42 +0100450BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
Tamas Banb0f83252022-02-11 09:49:36 +0100451 plat/arm/board/fvp/fvp_bl1_measured_boot.c \
452 lib/psa/measured_boot.c
453
Manish V Badarkhea74d9632021-09-14 23:12:42 +0100454BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
Tamas Banb0f83252022-02-11 09:49:36 +0100455 plat/arm/board/fvp/fvp_bl2_measured_boot.c \
456 lib/psa/measured_boot.c
Alexei Fedorov61369a22020-07-13 14:59:02 +0100457endif
458
Lucian Paul-Trifu5ee4f4e2022-06-22 18:45:30 +0100459ifeq (${DRTM_SUPPORT}, 1)
Manish V Badarkhefcfe4312022-07-12 21:48:04 +0100460BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \
461 plat/arm/board/fvp/fvp_drtm_dma_prot.c \
462 plat/arm/board/fvp/fvp_drtm_err.c \
johpow01baa3e6c2022-03-11 17:50:58 -0600463 plat/arm/board/fvp/fvp_drtm_measurement.c \
464 plat/arm/board/fvp/fvp_drtm_stub.c \
Manish V Badarkhefcfe4312022-07-12 21:48:04 +0100465 plat/arm/common/arm_dyn_cfg.c \
466 plat/arm/board/fvp/fvp_err.c
Lucian Paul-Trifu5ee4f4e2022-06-22 18:45:30 +0100467endif
468
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000469ifeq (${TRUSTED_BOARD_BOOT}, 1)
470BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
471BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
472
Soby Mathew45e39e22018-03-26 15:16:46 +0100473# FVP being a development platform, enable capability to disable Authentication
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100474# dynamically if TRUSTED_BOARD_BOOT is set.
Max Shvetsov06dba292019-12-06 11:50:12 +0000475DYN_DISABLE_AUTH := 1
Soby Mathew45e39e22018-03-26 15:16:46 +0100476endif
Manish V Badarkhe2d49ef32021-08-24 14:42:35 +0100477
Marc Bonnicic66fc1b2021-12-16 18:31:02 +0000478ifeq (${SPMC_AT_EL3}, 1)
479PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c
480endif
Wing Li05364b92023-01-26 18:33:43 -0800481
482PSCI_OS_INIT_MODE := 1
Manish Pandey03d87492023-04-24 10:46:21 +0100483
Manish Pandeyc25ab022023-04-24 14:58:55 +0100484ifeq (${SPD},spmd)
485BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
486endif
487
488# Test specific macros, keep them at bottom of this file
Manish Pandey03d87492023-04-24 10:46:21 +0100489$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
490ifeq (${PLATFORM_TEST_EA_FFH}, 1)
Manish Pandeyf90a73c2023-10-10 15:42:19 +0100491 ifeq (${FFH_SUPPORT}, 0)
492 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1")
Manish Pandey03d87492023-04-24 10:46:21 +0100493 endif
Manish Pandeyf90a73c2023-10-10 15:42:19 +0100494
Manish Pandey03d87492023-04-24 10:46:21 +0100495endif
Madhukar Pappireddy042043b2023-03-02 16:33:25 -0600496
Manish Pandeyc25ab022023-04-24 14:58:55 +0100497$(eval $(call add_define,PLATFORM_TEST_RAS_FFH))
498ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
Manish Pandeyf90a73c2023-10-10 15:42:19 +0100499 ifeq (${ENABLE_FEAT_RAS}, 0)
500 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1")
501 endif
502 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
503 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1")
Manish Pandeyc25ab022023-04-24 14:58:55 +0100504 endif
Madhukar Pappireddy042043b2023-03-02 16:33:25 -0600505endif
Sona Mathewd28f8552023-03-14 17:58:13 -0500506
Madhukar Pappireddye17c82a2024-01-10 14:01:37 -0600507$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP))
508ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1)
509 ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
510 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP")
511 endif
512 ifeq (${ENABLE_SPMD_LP}, 0)
513 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1")
514 endif
515 ifeq (${ENABLE_FEAT_RAS}, 0)
516 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1")
517 endif
518 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
519 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1")
520 endif
521endif
522
Sona Mathewd28f8552023-03-14 17:58:13 -0500523ifeq (${ERRATA_ABI_SUPPORT}, 1)
524include plat/arm/board/fvp/fvp_cpu_errata.mk
525endif
Madhukar Pappireddy3b228e12023-08-24 16:57:22 -0500526
527# Build macro necessary for running SPM tests on FVP platform
528$(eval $(call add_define,PLAT_TEST_SPM))