Rework use of interconnect drivers
ARM Trusted Firmware supports 2 different interconnect peripheral
drivers: CCI and CCN. ARM platforms are implemented using either of the
interconnect peripherals.
This patch adds a layer of abstraction to help ARM platform ports to
choose the right interconnect driver and corresponding platform support.
This is as described below:
1. A set of ARM common functions have been implemented to initialise an
interconnect and for entering/exiting a cluster from coherency. These
functions are prefixed as "plat_arm_interconnect_". Weak definitions of
these functions have been provided for each type of driver.
2.`plat_print_interconnect_regs` macro used for printing CCI registers is
moved from a common arm_macros.S to cci_macros.S.
3. The `ARM_CONFIG_HAS_CCI` flag used in `arm_config_flags` structure
is renamed to `ARM_CONFIG_HAS_INTERCONNECT`.
Change-Id: I02f31184fbf79b784175892d5ce1161b65a0066c
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 3cd39ce..c82c21a 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -57,10 +57,14 @@
$(error "Incorrect GIC driver chosen on FVP port")
endif
+FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
+ plat/arm/common/arm_cci.c
+
FVP_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
plat/arm/board/fvp/fvp_security.c \
plat/arm/common/arm_tzc400.c
+
PLAT_INCLUDES := -Iplat/arm/board/fvp/include
@@ -73,13 +77,15 @@
lib/cpus/aarch64/cortex_a72.S
BL1_SOURCES += drivers/io/io_semihosting.c \
- ${FVP_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl1_setup.c \
plat/arm/board/fvp/fvp_err.c \
- plat/arm/board/fvp/fvp_io_storage.c
+ plat/arm/board/fvp/fvp_io_storage.c \
+ ${FVP_CPU_LIBS} \
+ ${FVP_INTERCONNECT_SOURCES}
+
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
drivers/io/io_semihosting.c \
@@ -94,13 +100,14 @@
BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
${FVP_SECURITY_SOURCES}
-BL31_SOURCES += ${FVP_CPU_LIBS} \
- plat/arm/board/fvp/fvp_bl31_setup.c \
+BL31_SOURCES += plat/arm/board/fvp/fvp_bl31_setup.c \
plat/arm/board/fvp/fvp_pm.c \
plat/arm/board/fvp/fvp_topology.c \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \
+ ${FVP_CPU_LIBS} \
${FVP_GIC_SOURCES} \
+ ${FVP_INTERCONNECT_SOURCES} \
${FVP_SECURITY_SOURCES}
# Disable the PSCI platform compatibility layer