Rework use of interconnect drivers
ARM Trusted Firmware supports 2 different interconnect peripheral
drivers: CCI and CCN. ARM platforms are implemented using either of the
interconnect peripherals.
This patch adds a layer of abstraction to help ARM platform ports to
choose the right interconnect driver and corresponding platform support.
This is as described below:
1. A set of ARM common functions have been implemented to initialise an
interconnect and for entering/exiting a cluster from coherency. These
functions are prefixed as "plat_arm_interconnect_". Weak definitions of
these functions have been provided for each type of driver.
2.`plat_print_interconnect_regs` macro used for printing CCI registers is
moved from a common arm_macros.S to cci_macros.S.
3. The `ARM_CONFIG_HAS_CCI` flag used in `arm_config_flags` structure
is renamed to `ARM_CONFIG_HAS_INTERCONNECT`.
Change-Id: I02f31184fbf79b784175892d5ce1161b65a0066c
diff --git a/plat/arm/board/fvp/aarch64/fvp_common.c b/plat/arm/board/fvp/aarch64/fvp_common.c
index 305505d..f684d97 100644
--- a/plat/arm/board/fvp/aarch64/fvp_common.c
+++ b/plat/arm/board/fvp/aarch64/fvp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,7 +30,6 @@
#include <arm_config.h>
#include <arm_def.h>
-#include <cci.h>
#include <debug.h>
#include <gicv2.h>
#include <mmio.h>
@@ -50,9 +49,9 @@
/*******************************************************************************
* arm_config holds the characteristics of the differences between the three FVP
* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
- * at each boot stage by the primary before enabling the MMU (to allow cci
- * configuration) & used thereafter. Each BL will have its own copy to allow
- * independent operation.
+ * at each boot stage by the primary before enabling the MMU (to allow
+ * interconnect configuration) & used thereafter. Each BL will have its own copy
+ * to allow independent operation.
******************************************************************************/
arm_config_t arm_config;
@@ -209,7 +208,7 @@
break;
case HBI_BASE_FVP:
arm_config.flags |= ARM_CONFIG_BASE_MMAP |
- ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC;
+ ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC;
/*
* Check for supported revisions
@@ -230,23 +229,20 @@
}
-void fvp_cci_init(void)
+void fvp_interconnect_init(void)
{
- /*
- * Initialize CCI-400 driver
- */
- if (arm_config.flags & ARM_CONFIG_HAS_CCI)
- arm_cci_init();
+ if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
+ plat_arm_interconnect_init();
}
-void fvp_cci_enable(void)
+void fvp_interconnect_enable(void)
{
- if (arm_config.flags & ARM_CONFIG_HAS_CCI)
- cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+ if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
+ plat_arm_interconnect_enter_coherency();
}
-void fvp_cci_disable(void)
+void fvp_interconnect_disable(void)
{
- if (arm_config.flags & ARM_CONFIG_HAS_CCI)
- cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+ if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
+ plat_arm_interconnect_exit_coherency();
}
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index 91bc9c4..cc7feae 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -44,14 +44,14 @@
fvp_config_setup();
/*
- * Initialize CCI for this cluster during cold boot.
+ * Initialize Interconnect for this cluster during cold boot.
* No need for locks as no other CPU is active.
*/
- fvp_cci_init();
+ fvp_interconnect_init();
/*
- * Enable CCI coherency for the primary CPU's cluster.
+ * Enable coherency in Interconnect for the primary CPU's cluster.
*/
- fvp_cci_enable();
+ fvp_interconnect_enable();
}
/*******************************************************************************
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index f29af64..2ee3ba5 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -41,17 +41,17 @@
fvp_config_setup();
/*
- * Initialize CCI for this cluster during cold boot.
- * No need for locks as no other CPU is active.
+ * Initialize the correct interconnect for this cluster during cold
+ * boot. No need for locks as no other CPU is active.
*/
- fvp_cci_init();
+ fvp_interconnect_init();
/*
- * Enable CCI coherency for the primary CPU's cluster.
+ * Enable coherency in interconnect for the primary CPU's cluster.
* Earlier bootloader stages might already do this (e.g. Trusted
* Firmware's BL1 does it) but we can't assume so. There is no harm in
* executing this code twice anyway.
* FVP PSCI code will enable coherency for other clusters.
*/
- fvp_cci_enable();
+ fvp_interconnect_enable();
}
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index f959fab..3976ef2 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -86,7 +86,7 @@
uint64_t mpidr = read_mpidr_el1();
/* Disable coherency if this cluster is to be turned off */
- fvp_cci_disable();
+ fvp_interconnect_disable();
/* Program the power controller to turn the cluster off */
fvp_pwrc_write_pcoffr(mpidr);
@@ -117,7 +117,7 @@
fvp_pwrc_write_pponr(mpidr);
/* Enable coherency if this cluster was off */
- fvp_cci_enable();
+ fvp_interconnect_enable();
}
/*
diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h
index e88a45e..bb115e1 100644
--- a/plat/arm/board/fvp/fvp_private.h
+++ b/plat/arm/board/fvp/fvp_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -39,9 +39,9 @@
void fvp_config_setup(void);
-void fvp_cci_init(void);
-void fvp_cci_enable(void);
-void fvp_cci_disable(void);
+void fvp_interconnect_init(void);
+void fvp_interconnect_enable(void);
+void fvp_interconnect_disable(void);
#endif /* __FVP_PRIVATE_H__ */
diff --git a/plat/arm/board/fvp/include/plat_macros.S b/plat/arm/board/fvp/include/plat_macros.S
index 2117843..df66a52 100644
--- a/plat/arm/board/fvp/include/plat_macros.S
+++ b/plat/arm/board/fvp/include/plat_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,7 @@
#define __PLAT_MACROS_S__
#include <arm_macros.S>
+#include <cci_macros.S>
#include <v2m_def.h>
#include "../fvp_def.h"
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 3cd39ce..c82c21a 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -57,10 +57,14 @@
$(error "Incorrect GIC driver chosen on FVP port")
endif
+FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
+ plat/arm/common/arm_cci.c
+
FVP_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
plat/arm/board/fvp/fvp_security.c \
plat/arm/common/arm_tzc400.c
+
PLAT_INCLUDES := -Iplat/arm/board/fvp/include
@@ -73,13 +77,15 @@
lib/cpus/aarch64/cortex_a72.S
BL1_SOURCES += drivers/io/io_semihosting.c \
- ${FVP_CPU_LIBS} \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl1_setup.c \
plat/arm/board/fvp/fvp_err.c \
- plat/arm/board/fvp/fvp_io_storage.c
+ plat/arm/board/fvp/fvp_io_storage.c \
+ ${FVP_CPU_LIBS} \
+ ${FVP_INTERCONNECT_SOURCES}
+
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
drivers/io/io_semihosting.c \
@@ -94,13 +100,14 @@
BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
${FVP_SECURITY_SOURCES}
-BL31_SOURCES += ${FVP_CPU_LIBS} \
- plat/arm/board/fvp/fvp_bl31_setup.c \
+BL31_SOURCES += plat/arm/board/fvp/fvp_bl31_setup.c \
plat/arm/board/fvp/fvp_pm.c \
plat/arm/board/fvp/fvp_topology.c \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \
+ ${FVP_CPU_LIBS} \
${FVP_GIC_SOURCES} \
+ ${FVP_INTERCONNECT_SOURCES} \
${FVP_SECURITY_SOURCES}
# Disable the PSCI platform compatibility layer
diff --git a/plat/arm/board/juno/include/plat_macros.S b/plat/arm/board/juno/include/plat_macros.S
index db0c1d2..d2a88ed 100644
--- a/plat/arm/board/juno/include/plat_macros.S
+++ b/plat/arm/board/juno/include/plat_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,6 +30,7 @@
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
+#include <cci_macros.S>
#include <css_macros.S>
/*
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 77014a1..3ffc7e7 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -34,10 +34,14 @@
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
+JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
+ plat/arm/common/arm_cci.c
+
JUNO_SECURITY_SOURCES := drivers/arm/tzc400/tzc400.c \
plat/arm/board/juno/juno_security.c \
plat/arm/common/arm_tzc400.c
+
PLAT_INCLUDES := -Iplat/arm/board/juno/include
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S
@@ -46,7 +50,8 @@
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
plat/arm/board/juno/juno_bl1_setup.c \
- plat/arm/board/juno/juno_err.c
+ plat/arm/board/juno/juno_err.c \
+ ${JUNO_INTERCONNECT_SOURCES}
BL2_SOURCES += plat/arm/board/juno/juno_err.c \
${JUNO_SECURITY_SOURCES}
@@ -58,6 +63,7 @@
lib/cpus/aarch64/cortex_a72.S \
plat/arm/board/juno/juno_pm.c \
${JUNO_GIC_SOURCES} \
+ ${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
# Enable workarounds for selected Cortex-A57 erratas.