Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Elizabeth Ho | 4fc00d2 | 2023-07-18 14:10:25 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <platform_def.h> |
| 8 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | #include <arch.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 10 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <bl31/ea_handle.h> |
| 12 | #include <bl31/interrupt_mgmt.h> |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 13 | #include <bl31/sync_handle.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <common/runtime_svc.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 15 | #include <context.h> |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 16 | #include <el3_common_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <lib/el3_runtime/cpu_data.h> |
| 18 | #include <lib/smccc.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 19 | |
| 20 | .globl runtime_exceptions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 21 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 22 | .globl sync_exception_sp_el0 |
| 23 | .globl irq_sp_el0 |
| 24 | .globl fiq_sp_el0 |
| 25 | .globl serror_sp_el0 |
| 26 | |
| 27 | .globl sync_exception_sp_elx |
| 28 | .globl irq_sp_elx |
| 29 | .globl fiq_sp_elx |
| 30 | .globl serror_sp_elx |
| 31 | |
| 32 | .globl sync_exception_aarch64 |
| 33 | .globl irq_aarch64 |
| 34 | .globl fiq_aarch64 |
| 35 | .globl serror_aarch64 |
| 36 | |
| 37 | .globl sync_exception_aarch32 |
| 38 | .globl irq_aarch32 |
| 39 | .globl fiq_aarch32 |
| 40 | .globl serror_aarch32 |
| 41 | |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 42 | /* |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 43 | * Save LR and make x30 available as most of the routines in vector entry |
| 44 | * need a free register |
| 45 | */ |
| 46 | .macro save_x30 |
| 47 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 48 | .endm |
| 49 | |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 50 | .macro restore_x30 |
| 51 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 52 | .endm |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 53 | |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 54 | /* |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 55 | * Macro that synchronizes errors (EA) and checks for pending SError. |
| 56 | * On detecting a pending SError it either reflects it back to lower |
| 57 | * EL (KFH) or handles it in EL3 (FFH) based on EA routing model. |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 58 | */ |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 59 | .macro sync_and_handle_pending_serror |
Manish Pandey | 6b5721f | 2023-06-26 17:46:14 +0100 | [diff] [blame^] | 60 | synchronize_errors |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 61 | mrs x30, ISR_EL1 |
| 62 | tbz x30, #ISR_A_SHIFT, 2f |
| 63 | #if HANDLE_EA_EL3_FIRST_NS |
| 64 | mrs x30, scr_el3 |
| 65 | tst x30, #SCR_EA_BIT |
| 66 | b.eq 1f |
| 67 | bl handle_pending_async_ea |
| 68 | b 2f |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 69 | #endif |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 70 | 1: |
| 71 | /* This function never returns, but need LR for decision making */ |
| 72 | bl reflect_pending_async_ea_to_lower_el |
| 73 | 2: |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 74 | .endm |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 75 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 76 | /* --------------------------------------------------------------------- |
| 77 | * This macro handles Synchronous exceptions. |
| 78 | * Only SMC exceptions are supported. |
| 79 | * --------------------------------------------------------------------- |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 80 | */ |
| 81 | .macro handle_sync_exception |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 82 | #if ENABLE_RUNTIME_INSTRUMENTATION |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 83 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 84 | * Read the timestamp value and store it in per-cpu data. The value |
| 85 | * will be extracted from per-cpu data by the C level SMC handler and |
| 86 | * saved to the PMF timestamp region. |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 87 | */ |
| 88 | mrs x30, cntpct_el0 |
| 89 | str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 90 | mrs x29, tpidr_el3 |
| 91 | str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] |
| 92 | ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 93 | #endif |
| 94 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 95 | mrs x30, esr_el3 |
| 96 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 97 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 98 | /* Handle SMC exceptions separately from other synchronous exceptions */ |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 99 | cmp x30, #EC_AARCH32_SMC |
| 100 | b.eq smc_handler32 |
| 101 | |
| 102 | cmp x30, #EC_AARCH64_SMC |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 103 | b.eq sync_handler64 |
| 104 | |
| 105 | cmp x30, #EC_AARCH64_SYS |
| 106 | b.eq sync_handler64 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 107 | |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 108 | /* Synchronous exceptions other than the above are assumed to be EA */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 109 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Manish Pandey | c918c18 | 2023-01-11 21:53:02 +0000 | [diff] [blame] | 110 | b handle_lower_el_sync_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 111 | .endm |
| 112 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 113 | vector_base runtime_exceptions |
| 114 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 115 | /* --------------------------------------------------------------------- |
| 116 | * Current EL with SP_EL0 : 0x0 - 0x200 |
| 117 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 118 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 119 | vector_entry sync_exception_sp_el0 |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 120 | #ifdef MONITOR_TRAPS |
| 121 | stp x29, x30, [sp, #-16]! |
| 122 | |
| 123 | mrs x30, esr_el3 |
| 124 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 125 | |
| 126 | /* Check for BRK */ |
| 127 | cmp x30, #EC_BRK |
| 128 | b.eq brk_handler |
| 129 | |
| 130 | ldp x29, x30, [sp], #16 |
| 131 | #endif /* MONITOR_TRAPS */ |
| 132 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 133 | /* We don't expect any synchronous exceptions from EL3 */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 134 | b report_unhandled_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 135 | end_vector_entry sync_exception_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 137 | vector_entry irq_sp_el0 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 138 | /* |
| 139 | * EL3 code is non-reentrant. Any asynchronous exception is a serious |
| 140 | * error. Loop infinitely. |
| 141 | */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 142 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 143 | end_vector_entry irq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 144 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 145 | |
| 146 | vector_entry fiq_sp_el0 |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 147 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 148 | end_vector_entry fiq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 150 | |
| 151 | vector_entry serror_sp_el0 |
Jeenu Viswambharan | 911fcc9 | 2018-07-06 16:50:06 +0100 | [diff] [blame] | 152 | no_ret plat_handle_el3_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 153 | end_vector_entry serror_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 155 | /* --------------------------------------------------------------------- |
| 156 | * Current EL with SP_ELx: 0x200 - 0x400 |
| 157 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 158 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 159 | vector_entry sync_exception_sp_elx |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 160 | /* |
| 161 | * This exception will trigger if anything went wrong during a previous |
| 162 | * exception entry or exit or while handling an earlier unexpected |
| 163 | * synchronous exception. There is a high probability that SP_EL3 is |
| 164 | * corrupted. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 165 | */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 166 | b report_unhandled_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 167 | end_vector_entry sync_exception_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 168 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 169 | vector_entry irq_sp_elx |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 170 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 171 | end_vector_entry irq_sp_elx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 172 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 173 | vector_entry fiq_sp_elx |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 174 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 175 | end_vector_entry fiq_sp_elx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 176 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 177 | vector_entry serror_sp_elx |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 178 | #if HANDLE_EA_EL3_FIRST_NS |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 179 | /* |
| 180 | * This will trigger if the exception was taken due to SError in EL3 or |
| 181 | * because of pending asynchronous external aborts from lower EL that got |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 182 | * triggered due to implicit/explicit synchronization in EL3 (SCR_EL3.EA=1) |
| 183 | * during EL3 entry. For the former case we continue with "plat_handle_el3_ea". |
| 184 | * The later case will occur when PSTATE.A bit is cleared in |
| 185 | * "handle_pending_async_ea". This means we are doing a nested |
| 186 | * exception in EL3. Call the handler for async EA which will eret back to |
| 187 | * original el3 handler if it is nested exception. Also, unmask EA so that we |
| 188 | * catch any further EA arise when handling this nested exception at EL3. |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 189 | */ |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 190 | save_x30 |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 191 | ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] |
| 192 | cbz x30, 1f |
| 193 | /* |
| 194 | * This is nested exception handling, clear the flag to avoid taking this |
| 195 | * path for further exceptions caused by EA handling |
| 196 | */ |
| 197 | str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] |
| 198 | unmask_async_ea |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 199 | b handle_lower_el_async_ea |
| 200 | 1: |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 201 | restore_x30 |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 202 | #endif |
Jeenu Viswambharan | 911fcc9 | 2018-07-06 16:50:06 +0100 | [diff] [blame] | 203 | no_ret plat_handle_el3_ea |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 204 | |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 205 | end_vector_entry serror_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 206 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 207 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 208 | * Lower EL using AArch64 : 0x400 - 0x600 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 209 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 210 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 211 | vector_entry sync_exception_aarch64 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 212 | /* |
| 213 | * This exception vector will be the entry point for SMCs and traps |
| 214 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 215 | * to a valid cpu context where the general purpose and system register |
| 216 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 217 | */ |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 218 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 219 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 220 | sync_and_handle_pending_serror |
| 221 | unmask_async_ea |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 222 | handle_sync_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 223 | end_vector_entry sync_exception_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 224 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 225 | vector_entry irq_aarch64 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 226 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 227 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 228 | sync_and_handle_pending_serror |
| 229 | unmask_async_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 230 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 231 | end_vector_entry irq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 232 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 233 | vector_entry fiq_aarch64 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 234 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 235 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 236 | sync_and_handle_pending_serror |
| 237 | unmask_async_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 238 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 239 | end_vector_entry fiq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 240 | |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 241 | /* |
| 242 | * Need to synchronize any outstanding SError since we can get a burst of errors. |
| 243 | * So reuse the sync mechanism to catch any further errors which are pending. |
| 244 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 245 | vector_entry serror_aarch64 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 246 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 247 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 248 | sync_and_handle_pending_serror |
| 249 | unmask_async_ea |
Manish Pandey | c918c18 | 2023-01-11 21:53:02 +0000 | [diff] [blame] | 250 | b handle_lower_el_async_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 251 | end_vector_entry serror_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 252 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 253 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 254 | * Lower EL using AArch32 : 0x600 - 0x800 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 255 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 256 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 257 | vector_entry sync_exception_aarch32 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 258 | /* |
| 259 | * This exception vector will be the entry point for SMCs and traps |
| 260 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 261 | * to a valid cpu context where the general purpose and system register |
| 262 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 263 | */ |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 264 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 265 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 266 | sync_and_handle_pending_serror |
| 267 | unmask_async_ea |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 268 | handle_sync_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 269 | end_vector_entry sync_exception_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 270 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 271 | vector_entry irq_aarch32 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 272 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 273 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 274 | sync_and_handle_pending_serror |
| 275 | unmask_async_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 276 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 277 | end_vector_entry irq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 278 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 279 | vector_entry fiq_aarch32 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 280 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 281 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 282 | sync_and_handle_pending_serror |
| 283 | unmask_async_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 284 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 285 | end_vector_entry fiq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 286 | |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 287 | /* |
| 288 | * Need to synchronize any outstanding SError since we can get a burst of errors. |
| 289 | * So reuse the sync mechanism to catch any further errors which are pending. |
| 290 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 291 | vector_entry serror_aarch32 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 292 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 293 | apply_at_speculative_wa |
Manish Pandey | 07952fb | 2023-05-25 13:46:14 +0100 | [diff] [blame] | 294 | sync_and_handle_pending_serror |
| 295 | unmask_async_ea |
Manish Pandey | c918c18 | 2023-01-11 21:53:02 +0000 | [diff] [blame] | 296 | b handle_lower_el_async_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 297 | end_vector_entry serror_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 298 | |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 299 | #ifdef MONITOR_TRAPS |
| 300 | .section .rodata.brk_string, "aS" |
| 301 | brk_location: |
| 302 | .asciz "Error at instruction 0x" |
| 303 | brk_message: |
| 304 | .asciz "Unexpected BRK instruction with value 0x" |
| 305 | #endif /* MONITOR_TRAPS */ |
| 306 | |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 307 | /* --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 308 | * The following code handles secure monitor calls. |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 309 | * Depending upon the execution state from where the SMC has been |
| 310 | * invoked, it frees some general purpose registers to perform the |
| 311 | * remaining tasks. They involve finding the runtime service handler |
| 312 | * that is the target of the SMC & switching to runtime stacks (SP_EL0) |
| 313 | * before calling the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 314 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 315 | * Note that x30 has been explicitly saved and can be used here |
| 316 | * --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 317 | */ |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 318 | func sync_exception_handler |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 319 | smc_handler32: |
| 320 | /* Check whether aarch32 issued an SMC64 */ |
| 321 | tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited |
| 322 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 323 | sync_handler64: |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 324 | /* NOTE: The code below must preserve x0-x4 */ |
| 325 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 326 | /* |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 327 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
Boyan Karatotev | ed85cf7 | 2022-12-06 09:03:42 +0000 | [diff] [blame] | 328 | * Also save PMCR_EL0 and set the PSTATE to a known state. |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 329 | */ |
Daniel Boulby | 95fb1aa | 2022-01-19 11:20:05 +0000 | [diff] [blame] | 330 | bl prepare_el3_entry |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 331 | |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 332 | #if ENABLE_PAUTH |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 333 | /* Load and program APIAKey firmware key */ |
| 334 | bl pauth_load_bl31_apiakey |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 335 | #endif |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 336 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 337 | /* |
| 338 | * Populate the parameters for the SMC handler. |
| 339 | * We already have x0-x4 in place. x5 will point to a cookie (not used |
| 340 | * now). x6 will point to the context structure (SP_EL3) and x7 will |
Dimitris Papastamos | 0415951 | 2018-01-22 11:53:04 +0000 | [diff] [blame] | 341 | * contain flags we need to pass to the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 342 | */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 343 | mov x5, xzr |
| 344 | mov x6, sp |
| 345 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 346 | /* |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 347 | * Restore the saved C runtime stack value which will become the new |
| 348 | * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' |
| 349 | * structure prior to the last ERET from EL3. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 350 | */ |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 351 | ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 352 | |
| 353 | /* Switch to SP_EL0 */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 354 | msr spsel, #MODE_SP_EL0 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 355 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 356 | /* |
Manish Pandey | 70bbdbd | 2022-12-07 13:04:20 +0000 | [diff] [blame] | 357 | * Save the SPSR_EL3 and ELR_EL3 in case there is a world |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 358 | * switch during SMC handling. |
| 359 | * TODO: Revisit if all system registers can be saved later. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 360 | */ |
| 361 | mrs x16, spsr_el3 |
| 362 | mrs x17, elr_el3 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 363 | stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
Manish Pandey | 70bbdbd | 2022-12-07 13:04:20 +0000 | [diff] [blame] | 364 | |
| 365 | /* Load SCR_EL3 */ |
| 366 | mrs x18, scr_el3 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 367 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 368 | /* check for system register traps */ |
| 369 | mrs x16, esr_el3 |
| 370 | ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 371 | cmp x17, #EC_AARCH64_SYS |
| 372 | b.eq sysreg_handler64 |
| 373 | |
Zelalem Aweke | 4d666ac | 2021-07-08 17:13:09 -0500 | [diff] [blame] | 374 | /* Clear flag register */ |
| 375 | mov x7, xzr |
| 376 | |
| 377 | #if ENABLE_RME |
| 378 | /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ |
Elizabeth Ho | 4fc00d2 | 2023-07-18 14:10:25 +0100 | [diff] [blame] | 379 | ubfx x7, x18, #SCR_NSE_SHIFT, #1 |
Zelalem Aweke | 4d666ac | 2021-07-08 17:13:09 -0500 | [diff] [blame] | 380 | |
| 381 | /* |
| 382 | * Shift copied SCR_EL3.NSE bit by 5 to create space for |
Olivier Deprez | 33dd845 | 2022-10-11 15:38:27 +0200 | [diff] [blame] | 383 | * SCR_EL3.NS bit. Bit 5 of the flag corresponds to |
Zelalem Aweke | 4d666ac | 2021-07-08 17:13:09 -0500 | [diff] [blame] | 384 | * the SCR_EL3.NSE bit. |
| 385 | */ |
| 386 | lsl x7, x7, #5 |
| 387 | #endif /* ENABLE_RME */ |
| 388 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 389 | /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ |
| 390 | bfi x7, x18, #0, #1 |
| 391 | |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 392 | mov sp, x12 |
| 393 | |
| 394 | /* |
| 395 | * Per SMCCC documentation, bits [23:17] must be zero for Fast |
| 396 | * SMCs. Other values are reserved for future use. Ensure that |
| 397 | * these bits are zeroes, if not report as unknown SMC. |
| 398 | */ |
| 399 | tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/ |
| 400 | tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT) |
| 401 | b.ne smc_unknown |
| 402 | |
Olivier Deprez | 33dd845 | 2022-10-11 15:38:27 +0200 | [diff] [blame] | 403 | /* |
| 404 | * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID |
| 405 | * passed through x0. Copy the SVE hint bit to flags and mask the |
| 406 | * bit in smc_fid passed to the standard service dispatcher. |
| 407 | * A service/dispatcher can retrieve the SVE hint bit state from |
| 408 | * flags using the appropriate helper. |
| 409 | */ |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 410 | 2: |
Olivier Deprez | 62cc109 | 2023-05-24 17:42:00 +0200 | [diff] [blame] | 411 | and x16, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) |
| 412 | orr x7, x7, x16 |
Olivier Deprez | 33dd845 | 2022-10-11 15:38:27 +0200 | [diff] [blame] | 413 | bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) |
| 414 | |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 415 | /* Get the unique owning entity number */ |
| 416 | ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH |
| 417 | ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH |
| 418 | orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH |
| 419 | |
| 420 | /* Load descriptor index from array of indices */ |
Madhukar Pappireddy | f4e6ea6 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 421 | adrp x14, rt_svc_descs_indices |
| 422 | add x14, x14, :lo12:rt_svc_descs_indices |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 423 | ldrb w15, [x14, x16] |
| 424 | |
| 425 | /* Any index greater than 127 is invalid. Check bit 7. */ |
| 426 | tbnz w15, 7, smc_unknown |
| 427 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 428 | /* |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 429 | * Get the descriptor using the index |
| 430 | * x11 = (base + off), w15 = index |
| 431 | * |
| 432 | * handler = (base + off) + (index << log2(size)) |
| 433 | */ |
| 434 | adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) |
| 435 | lsl w10, w15, #RT_SVC_SIZE_LOG2 |
| 436 | ldr x15, [x11, w10, uxtw] |
| 437 | |
| 438 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 439 | * Call the Secure Monitor Call handler and then drop directly into |
| 440 | * el3_exit() which will program any remaining architectural state |
| 441 | * prior to issuing the ERET to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 442 | */ |
| 443 | #if DEBUG |
| 444 | cbz x15, rt_svc_fw_critical_error |
| 445 | #endif |
| 446 | blr x15 |
| 447 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 448 | b el3_exit |
| 449 | |
| 450 | sysreg_handler64: |
| 451 | mov x0, x16 /* ESR_EL3, containing syndrome information */ |
| 452 | mov x1, x6 /* lower EL's context */ |
| 453 | mov x19, x6 /* save context pointer for after the call */ |
| 454 | mov sp, x12 /* EL3 runtime stack, as loaded above */ |
| 455 | |
| 456 | /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */ |
| 457 | bl handle_sysreg_trap |
| 458 | /* |
| 459 | * returns: |
| 460 | * -1: unhandled trap, panic |
| 461 | * 0: handled trap, return to the trapping instruction (repeating it) |
| 462 | * 1: handled trap, return to the next instruction |
| 463 | */ |
| 464 | |
| 465 | tst w0, w0 |
Govindraj Raja | b6709b0 | 2023-02-21 17:43:55 +0000 | [diff] [blame] | 466 | b.mi elx_panic /* negative return value: panic */ |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 467 | b.eq 1f /* zero: do not change ELR_EL3 */ |
| 468 | |
| 469 | /* advance the PC to continue after the instruction */ |
| 470 | ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] |
| 471 | add x1, x1, #4 |
| 472 | str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] |
| 473 | 1: |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 474 | b el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 475 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 476 | smc_unknown: |
| 477 | /* |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 478 | * Unknown SMC call. Populate return value with SMC_UNK and call |
| 479 | * el3_exit() which will restore the remaining architectural state |
| 480 | * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 481 | * to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 482 | */ |
Antonio Nino Diaz | e4794b7 | 2018-02-14 14:22:29 +0000 | [diff] [blame] | 483 | mov x0, #SMC_UNK |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 484 | str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 485 | b el3_exit |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 486 | |
| 487 | smc_prohibited: |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 488 | restore_ptw_el1_sys_regs |
| 489 | ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 490 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Antonio Nino Diaz | e4794b7 | 2018-02-14 14:22:29 +0000 | [diff] [blame] | 491 | mov x0, #SMC_UNK |
Anthony Steinhauser | 0f7e601 | 2020-01-07 15:44:06 -0800 | [diff] [blame] | 492 | exception_return |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 493 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 494 | #if DEBUG |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 495 | rt_svc_fw_critical_error: |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 496 | /* Switch to SP_ELx */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 497 | msr spsel, #MODE_SP_ELX |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 498 | no_ret report_unhandled_exception |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 499 | #endif |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 500 | endfunc sync_exception_handler |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 501 | |
| 502 | /* --------------------------------------------------------------------- |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 503 | * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS |
| 504 | * interrupts. |
| 505 | * |
| 506 | * Note that x30 has been explicitly saved and can be used here |
| 507 | * --------------------------------------------------------------------- |
| 508 | */ |
| 509 | func handle_interrupt_exception |
| 510 | /* |
| 511 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
| 512 | * Also save PMCR_EL0 and set the PSTATE to a known state. |
| 513 | */ |
| 514 | bl prepare_el3_entry |
| 515 | |
| 516 | #if ENABLE_PAUTH |
| 517 | /* Load and program APIAKey firmware key */ |
| 518 | bl pauth_load_bl31_apiakey |
| 519 | #endif |
| 520 | |
| 521 | /* Save the EL3 system registers needed to return from this exception */ |
| 522 | mrs x0, spsr_el3 |
| 523 | mrs x1, elr_el3 |
| 524 | stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 525 | |
| 526 | /* Switch to the runtime stack i.e. SP_EL0 */ |
| 527 | ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 528 | mov x20, sp |
| 529 | msr spsel, #MODE_SP_EL0 |
| 530 | mov sp, x2 |
| 531 | |
| 532 | /* |
| 533 | * Find out whether this is a valid interrupt type. |
| 534 | * If the interrupt controller reports a spurious interrupt then return |
| 535 | * to where we came from. |
| 536 | */ |
| 537 | bl plat_ic_get_pending_interrupt_type |
| 538 | cmp x0, #INTR_TYPE_INVAL |
| 539 | b.eq interrupt_exit |
| 540 | |
| 541 | /* |
| 542 | * Get the registered handler for this interrupt type. |
| 543 | * A NULL return value could be 'cause of the following conditions: |
| 544 | * |
| 545 | * a. An interrupt of a type was routed correctly but a handler for its |
| 546 | * type was not registered. |
| 547 | * |
| 548 | * b. An interrupt of a type was not routed correctly so a handler for |
| 549 | * its type was not registered. |
| 550 | * |
| 551 | * c. An interrupt of a type was routed correctly to EL3, but was |
| 552 | * deasserted before its pending state could be read. Another |
| 553 | * interrupt of a different type pended at the same time and its |
| 554 | * type was reported as pending instead. However, a handler for this |
| 555 | * type was not registered. |
| 556 | * |
| 557 | * a. and b. can only happen due to a programming error. The |
| 558 | * occurrence of c. could be beyond the control of Trusted Firmware. |
| 559 | * It makes sense to return from this exception instead of reporting an |
| 560 | * error. |
| 561 | */ |
| 562 | bl get_interrupt_type_handler |
| 563 | cbz x0, interrupt_exit |
| 564 | mov x21, x0 |
| 565 | |
| 566 | mov x0, #INTR_ID_UNAVAILABLE |
| 567 | |
| 568 | /* Set the current security state in the 'flags' parameter */ |
| 569 | mrs x2, scr_el3 |
| 570 | ubfx x1, x2, #0, #1 |
| 571 | |
| 572 | /* Restore the reference to the 'handle' i.e. SP_EL3 */ |
| 573 | mov x2, x20 |
| 574 | |
| 575 | /* x3 will point to a cookie (not used now) */ |
| 576 | mov x3, xzr |
| 577 | |
| 578 | /* Call the interrupt type handler */ |
| 579 | blr x21 |
| 580 | |
| 581 | interrupt_exit: |
| 582 | /* Return from exception, possibly in a different security state */ |
| 583 | b el3_exit |
| 584 | endfunc handle_interrupt_exception |
| 585 | |
| 586 | /* --------------------------------------------------------------------- |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 587 | * The following code handles exceptions caused by BRK instructions. |
| 588 | * Following a BRK instruction, the only real valid cause of action is |
| 589 | * to print some information and panic, as the code that caused it is |
| 590 | * likely in an inconsistent internal state. |
| 591 | * |
| 592 | * This is initially intended to be used in conjunction with |
| 593 | * __builtin_trap. |
| 594 | * --------------------------------------------------------------------- |
| 595 | */ |
| 596 | #ifdef MONITOR_TRAPS |
| 597 | func brk_handler |
| 598 | /* Extract the ISS */ |
| 599 | mrs x10, esr_el3 |
| 600 | ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH |
| 601 | |
| 602 | /* Ensure the console is initialized */ |
| 603 | bl plat_crash_console_init |
| 604 | |
| 605 | adr x4, brk_location |
| 606 | bl asm_print_str |
| 607 | mrs x4, elr_el3 |
| 608 | bl asm_print_hex |
| 609 | bl asm_print_newline |
| 610 | |
| 611 | adr x4, brk_message |
| 612 | bl asm_print_str |
| 613 | mov x4, x10 |
| 614 | mov x5, #28 |
| 615 | bl asm_print_hex_bits |
| 616 | bl asm_print_newline |
| 617 | |
| 618 | no_ret plat_panic_handler |
| 619 | endfunc brk_handler |
| 620 | #endif /* MONITOR_TRAPS */ |