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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dimitris Papastamos04159512018-01-22 11:53:04 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +01008#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <context.h>
dp-arm3cac7862016-09-19 11:18:44 +010010#include <cpu_data.h>
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000011#include <ea_handle.h>
Achin Gupta9cf2bb72014-05-09 11:07:09 +010012#include <interrupt_mgmt.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010013#include <platform_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <runtime_svc.h>
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +010015#include <smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010016
17 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019 .globl sync_exception_sp_el0
20 .globl irq_sp_el0
21 .globl fiq_sp_el0
22 .globl serror_sp_el0
23
24 .globl sync_exception_sp_elx
25 .globl irq_sp_elx
26 .globl fiq_sp_elx
27 .globl serror_sp_elx
28
29 .globl sync_exception_aarch64
30 .globl irq_aarch64
31 .globl fiq_aarch64
32 .globl serror_aarch64
33
34 .globl sync_exception_aarch32
35 .globl irq_aarch32
36 .globl fiq_aarch32
37 .globl serror_aarch32
38
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000039 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010040 * Macro that prepares entry to EL3 upon taking an exception.
41 *
42 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
43 * instruction. When an error is thus synchronized, the handling is
44 * delegated to platform EA handler.
45 *
46 * Without RAS_EXTENSION, this macro just saves x30, and unmasks
47 * Asynchronous External Aborts.
48 */
49 .macro check_and_unmask_ea
50#if RAS_EXTENSION
51 /* Synchronize pending External Aborts */
52 esb
53
54 /* Unmask the SError interrupt */
55 msr daifclr, #DAIF_ABT_BIT
56
57 /*
58 * Explicitly save x30 so as to free up a register and to enable
59 * branching
60 */
61 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
62
63 /* Check for SErrors synchronized by the ESB instruction */
64 mrs x30, DISR_EL1
65 tbz x30, #DISR_A_BIT, 1f
66
67 /* Save GP registers and restore them afterwards */
68 bl save_gp_registers
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010069 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010070 bl restore_gp_registers
71
721:
73#else
74 /* Unmask the SError interrupt */
75 msr daifclr, #DAIF_ABT_BIT
76
77 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
78#endif
79 .endm
80
Douglas Raillard0980eed2016-11-09 17:48:27 +000081 /* ---------------------------------------------------------------------
82 * This macro handles Synchronous exceptions.
83 * Only SMC exceptions are supported.
84 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010085 */
86 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +010087#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +010088 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +000089 * Read the timestamp value and store it in per-cpu data. The value
90 * will be extracted from per-cpu data by the C level SMC handler and
91 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +010092 */
93 mrs x30, cntpct_el0
94 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
95 mrs x29, tpidr_el3
96 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
97 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
98#endif
99
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100100 mrs x30, esr_el3
101 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
102
Douglas Raillard0980eed2016-11-09 17:48:27 +0000103 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100104 cmp x30, #EC_AARCH32_SMC
105 b.eq smc_handler32
106
107 cmp x30, #EC_AARCH64_SMC
108 b.eq smc_handler64
109
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100110 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700111 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100112 b enter_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100113 .endm
114
115
Douglas Raillard0980eed2016-11-09 17:48:27 +0000116 /* ---------------------------------------------------------------------
117 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
118 * interrupts.
119 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100120 */
121 .macro handle_interrupt_exception label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100122 bl save_gp_registers
Douglas Raillard0980eed2016-11-09 17:48:27 +0000123 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100124 mrs x0, spsr_el3
125 mrs x1, elr_el3
126 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
127
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100128 /* Switch to the runtime stack i.e. SP_EL0 */
129 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
130 mov x20, sp
131 msr spsel, #0
132 mov sp, x2
133
134 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000135 * Find out whether this is a valid interrupt type.
136 * If the interrupt controller reports a spurious interrupt then return
137 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100138 */
Dan Handley701fea72014-05-27 16:17:21 +0100139 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100140 cmp x0, #INTR_TYPE_INVAL
141 b.eq interrupt_exit_\label
142
143 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000144 * Get the registered handler for this interrupt type.
145 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100146 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000147 * a. An interrupt of a type was routed correctly but a handler for its
148 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100149 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000150 * b. An interrupt of a type was not routed correctly so a handler for
151 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100152 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000153 * c. An interrupt of a type was routed correctly to EL3, but was
154 * deasserted before its pending state could be read. Another
155 * interrupt of a different type pended at the same time and its
156 * type was reported as pending instead. However, a handler for this
157 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100158 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000159 * a. and b. can only happen due to a programming error. The
160 * occurrence of c. could be beyond the control of Trusted Firmware.
161 * It makes sense to return from this exception instead of reporting an
162 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100163 */
164 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100165 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100166 mov x21, x0
167
168 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100169
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100170 /* Set the current security state in the 'flags' parameter */
171 mrs x2, scr_el3
172 ubfx x1, x2, #0, #1
173
174 /* Restore the reference to the 'handle' i.e. SP_EL3 */
175 mov x2, x20
176
Douglas Raillard0980eed2016-11-09 17:48:27 +0000177 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100178 mov x3, xzr
179
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100180 /* Call the interrupt type handler */
181 blr x21
182
183interrupt_exit_\label:
184 /* Return from exception, possibly in a different security state */
185 b el3_exit
186
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100187 .endm
188
189
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100190vector_base runtime_exceptions
191
Douglas Raillard0980eed2016-11-09 17:48:27 +0000192 /* ---------------------------------------------------------------------
193 * Current EL with SP_EL0 : 0x0 - 0x200
194 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100196vector_entry sync_exception_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000197 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700198 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100199end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100201vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000202 /*
203 * EL3 code is non-reentrant. Any asynchronous exception is a serious
204 * error. Loop infinitely.
205 */
Julius Werner67ebde72017-07-27 14:59:34 -0700206 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100207end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100209
210vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700211 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100212end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100214
215vector_entry serror_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700216 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100217end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218
Douglas Raillard0980eed2016-11-09 17:48:27 +0000219 /* ---------------------------------------------------------------------
220 * Current EL with SP_ELx: 0x200 - 0x400
221 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100223vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000224 /*
225 * This exception will trigger if anything went wrong during a previous
226 * exception entry or exit or while handling an earlier unexpected
227 * synchronous exception. There is a high probability that SP_EL3 is
228 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000229 */
Julius Werner67ebde72017-07-27 14:59:34 -0700230 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100231end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100233vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700234 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100235end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000236
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100237vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700238 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100239end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000240
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100241vector_entry serror_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700242 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100243end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244
Douglas Raillard0980eed2016-11-09 17:48:27 +0000245 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100246 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000247 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100249vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000250 /*
251 * This exception vector will be the entry point for SMCs and traps
252 * that are unhandled at lower ELs most commonly. SP_EL3 should point
253 * to a valid cpu context where the general purpose and system register
254 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000255 */
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100256 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000257 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100258end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100260vector_entry irq_aarch64
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100261 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100262 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100263end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100265vector_entry fiq_aarch64
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100266 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100267 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100268end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100269
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100270vector_entry serror_aarch64
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000271 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100272 b enter_lower_el_async_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100273end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274
Douglas Raillard0980eed2016-11-09 17:48:27 +0000275 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100276 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000277 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100279vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000280 /*
281 * This exception vector will be the entry point for SMCs and traps
282 * that are unhandled at lower ELs most commonly. SP_EL3 should point
283 * to a valid cpu context where the general purpose and system register
284 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000285 */
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100286 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000287 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100288end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100290vector_entry irq_aarch32
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100291 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100292 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100293end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100295vector_entry fiq_aarch32
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100296 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100297 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100298end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100299
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100300vector_entry serror_aarch32
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000301 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100302 b enter_lower_el_async_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100303end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000304
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000305
Douglas Raillard0980eed2016-11-09 17:48:27 +0000306 /* ---------------------------------------------------------------------
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100307 * This macro takes an argument in x16 that is the index in the
308 * 'rt_svc_descs_indices' array, checks that the value in the array is
309 * valid, and loads in x15 the pointer to the handler of that service.
310 * ---------------------------------------------------------------------
311 */
312 .macro load_rt_svc_desc_pointer
313 /* Load descriptor index from array of indices */
314 adr x14, rt_svc_descs_indices
315 ldrb w15, [x14, x16]
316
317#if SMCCC_MAJOR_VERSION == 1
318 /* Any index greater than 127 is invalid. Check bit 7. */
319 tbnz w15, 7, smc_unknown
320#elif SMCCC_MAJOR_VERSION == 2
321 /* Verify that the top 3 bits of the loaded index are 0 (w15 <= 31) */
322 cmp w15, #31
323 b.hi smc_unknown
324#endif /* SMCCC_MAJOR_VERSION */
325
326 /*
327 * Get the descriptor using the index
328 * x11 = (base + off), w15 = index
329 *
330 * handler = (base + off) + (index << log2(size))
331 */
332 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
333 lsl w10, w15, #RT_SVC_SIZE_LOG2
334 ldr x15, [x11, w10, uxtw]
335 .endm
336
337 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000338 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000339 * Depending upon the execution state from where the SMC has been
340 * invoked, it frees some general purpose registers to perform the
341 * remaining tasks. They involve finding the runtime service handler
342 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
343 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000344 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000345 * Note that x30 has been explicitly saved and can be used here
346 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000347 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000348func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000349smc_handler32:
350 /* Check whether aarch32 issued an SMC64 */
351 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
352
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000353smc_handler64:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000354 /*
355 * Populate the parameters for the SMC handler.
356 * We already have x0-x4 in place. x5 will point to a cookie (not used
357 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000358 * contain flags we need to pass to the handler.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000359 *
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100360 * Save x4-x29 and sp_el0.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000361 */
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000362 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
363 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
364 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
365 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
366 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
367 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
368 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
369 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
370 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
371 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
372 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
373 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
374 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
375 mrs x18, sp_el0
376 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100377
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000378 mov x5, xzr
379 mov x6, sp
380
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100381#if SMCCC_MAJOR_VERSION == 1
382
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000383 /* Get the unique owning entity number */
384 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
385 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
386 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
387
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100388 load_rt_svc_desc_pointer
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000389
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100390#elif SMCCC_MAJOR_VERSION == 2
391
392 /* Bit 31 must be set */
393 tbz x0, #FUNCID_TYPE_SHIFT, smc_unknown
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000394
Douglas Raillard0980eed2016-11-09 17:48:27 +0000395 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100396 * Check MSB of namespace to decide between compatibility/vendor and
397 * SPCI/SPRT
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000398 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100399 tbz x0, #(FUNCID_NAMESPACE_SHIFT + 1), compat_or_vendor
400
401 /* Namespaces SPRT and SPCI currently unimplemented */
402 b smc_unknown
403
404compat_or_vendor:
405
406 /* Namespace is b'00 (compatibility) or b'01 (vendor) */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000407
408 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100409 * Add the LSB of the namespace (bit [28]) to the OEN [27:24] to create
410 * a 5-bit index into the rt_svc_descs_indices array.
411 *
412 * The low 16 entries of the rt_svc_descs_indices array correspond to
413 * OENs of the compatibility namespace and the top 16 entries of the
414 * array are assigned to the vendor namespace descriptor.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000415 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100416 ubfx x16, x0, #FUNCID_OEN_SHIFT, #(FUNCID_OEN_WIDTH + 1)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000417
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100418 load_rt_svc_desc_pointer
419
420#endif /* SMCCC_MAJOR_VERSION */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000421
Douglas Raillard0980eed2016-11-09 17:48:27 +0000422 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100423 * Restore the saved C runtime stack value which will become the new
424 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
425 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000426 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100427 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
428
429 /* Switch to SP_EL0 */
430 msr spsel, #0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000431
Douglas Raillard0980eed2016-11-09 17:48:27 +0000432 /*
433 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
434 * switch during SMC handling.
435 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000436 */
437 mrs x16, spsr_el3
438 mrs x17, elr_el3
439 mrs x18, scr_el3
440 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100441 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000442
443 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
444 bfi x7, x18, #0, #1
445
446 mov sp, x12
447
Douglas Raillard0980eed2016-11-09 17:48:27 +0000448 /*
449 * Call the Secure Monitor Call handler and then drop directly into
450 * el3_exit() which will program any remaining architectural state
451 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000452 */
453#if DEBUG
454 cbz x15, rt_svc_fw_critical_error
455#endif
456 blr x15
457
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100458 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100459
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000460smc_unknown:
461 /*
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000462 * Unknown SMC call. Populate return value with SMC_UNK, restore
463 * GP registers, and return to caller.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000464 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000465 mov x0, #SMC_UNK
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000466 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
467 b restore_gp_registers_eret
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000468
469smc_prohibited:
Soby Mathew6c5192a2014-04-30 15:36:37 +0100470 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000471 mov x0, #SMC_UNK
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000472 eret
473
474rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000475 /* Switch to SP_ELx */
476 msr spsel, #1
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000477 no_ret report_unhandled_exception
Kévin Petita877c252015-03-24 14:03:57 +0000478endfunc smc_handler