fix(pmu): unconditionally save PMCR_EL0
Reading back a RES0 bit does not necessarily mean it will be read as 0.
The Arm ARM explicitly warns against doing this. The PMU initialisation
code tries to set such bits to 1 (in MDCR_EL3) regardless of whether
they are in use or are RES0, checking their value could be wrong and
PMCR_EL0 might not end up being saved.
Save PMCR_EL0 unconditionally to prevent this. Remove the security state
change as the outgoing state is not relevant to what the root world
context should look like.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id43667d37b0e2da3ded0beaf23fa0d4f9013f470
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 2fa9f06..b02e8bb 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -72,9 +72,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -164,9 +162,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -440,9 +436,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry