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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Govindraj Rajab6709b02023-02-21 17:43:55 +00002 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
Andre Przywarafa914d82022-11-21 17:04:10 +000013#include <bl31/sync_handle.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010015#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010016#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/el3_runtime/cpu_data.h>
18#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
20 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010021
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000022 .globl sync_exception_sp_el0
23 .globl irq_sp_el0
24 .globl fiq_sp_el0
25 .globl serror_sp_el0
26
27 .globl sync_exception_sp_elx
28 .globl irq_sp_elx
29 .globl fiq_sp_elx
30 .globl serror_sp_elx
31
32 .globl sync_exception_aarch64
33 .globl irq_aarch64
34 .globl fiq_aarch64
35 .globl serror_aarch64
36
37 .globl sync_exception_aarch32
38 .globl irq_aarch32
39 .globl fiq_aarch32
40 .globl serror_aarch32
41
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000042 /*
Manish Pandey66a056e2023-01-11 21:41:07 +000043 * Save LR and make x30 available as most of the routines in vector entry
44 * need a free register
45 */
46 .macro save_x30
47 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
48 .endm
49
50 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010051 * Macro that prepares entry to EL3 upon taking an exception.
52 *
Manish Pandeyd419e222023-02-13 12:39:17 +000053 * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an
54 * ESB instruction. When an error is thus synchronized, the handling is
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010055 * delegated to platform EA handler.
56 *
Manish Pandeyd419e222023-02-13 12:39:17 +000057 * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +000058 * a DSB, unmasks Asynchronous External Aborts and saves X30 before
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050059 * setting the flag CTX_IS_IN_EL3.
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010060 */
61 .macro check_and_unmask_ea
Manish Pandeyd419e222023-02-13 12:39:17 +000062#if RAS_FFH_SUPPORT
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010063 /* Synchronize pending External Aborts */
64 esb
65
66 /* Unmask the SError interrupt */
67 msr daifclr, #DAIF_ABT_BIT
68
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010069 /* Check for SErrors synchronized by the ESB instruction */
70 mrs x30, DISR_EL1
71 tbz x30, #DISR_A_BIT, 1f
72
Alexei Fedorov503bbf32019-08-13 15:17:53 +010073 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010074 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
Boyan Karatoteved85cf72022-12-06 09:03:42 +000075 * Also save PMCR_EL0 and set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010076 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +000077 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +010078
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010079 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010080
Alexei Fedorovf41355c2019-09-13 14:11:59 +010081 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
82 bl restore_gp_pmcr_pauth_regs
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100831:
84#else
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050085 /*
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050086 * Note 1: The explicit DSB at the entry of various exception vectors
87 * for handling exceptions from lower ELs can inadvertently trigger an
88 * SError exception in EL3 due to pending asynchronous aborts in lower
89 * ELs. This will end up being handled by serror_sp_elx which will
90 * ultimately panic and die.
91 * The way to workaround is to update a flag to indicate if the exception
92 * truly came from EL3. This flag is allocated in the cpu_context
93 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
94 * This is not a bullet proof solution to the problem at hand because
95 * we assume the instructions following "isb" that help to update the
96 * flag execute without causing further exceptions.
97 */
98
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050099 /*
Manish Pandeyb3c61982023-01-06 13:38:03 +0000100 * For SoCs which do not implement RAS, use DSB as a barrier to
101 * synchronize pending external aborts.
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500102 */
103 dsb sy
104
105 /* Unmask the SError interrupt */
106 msr daifclr, #DAIF_ABT_BIT
107
108 /* Use ISB for the above unmask operation to take effect immediately */
109 isb
110
Manish Pandey66a056e2023-01-11 21:41:07 +0000111 /* Refer Note 1. */
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500112 mov x30, #1
113 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
114 dmb sy
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500115#endif
Manish Pandeyb3c61982023-01-06 13:38:03 +0000116 .endm
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500117
Douglas Raillard0980eed2016-11-09 17:48:27 +0000118 /* ---------------------------------------------------------------------
119 * This macro handles Synchronous exceptions.
120 * Only SMC exceptions are supported.
121 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100122 */
123 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +0100124#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +0100125 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000126 * Read the timestamp value and store it in per-cpu data. The value
127 * will be extracted from per-cpu data by the C level SMC handler and
128 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +0100129 */
130 mrs x30, cntpct_el0
131 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
132 mrs x29, tpidr_el3
133 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
134 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
135#endif
136
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100137 mrs x30, esr_el3
138 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
139
Douglas Raillard0980eed2016-11-09 17:48:27 +0000140 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100141 cmp x30, #EC_AARCH32_SMC
142 b.eq smc_handler32
143
144 cmp x30, #EC_AARCH64_SMC
Andre Przywarafa914d82022-11-21 17:04:10 +0000145 b.eq sync_handler64
146
147 cmp x30, #EC_AARCH64_SYS
148 b.eq sync_handler64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100149
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100150 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700151 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Manish Pandeyc918c182023-01-11 21:53:02 +0000152 b handle_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100153 .endm
154
155
Douglas Raillard0980eed2016-11-09 17:48:27 +0000156 /* ---------------------------------------------------------------------
157 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
158 * interrupts.
159 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100160 */
161 .macro handle_interrupt_exception label
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000162
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100163 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100164 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
Boyan Karatoteved85cf72022-12-06 09:03:42 +0000165 * Also save PMCR_EL0 and set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100166 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000167 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100168
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000169#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100170 /* Load and program APIAKey firmware key */
171 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000172#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000173
Douglas Raillard0980eed2016-11-09 17:48:27 +0000174 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100175 mrs x0, spsr_el3
176 mrs x1, elr_el3
177 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
178
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100179 /* Switch to the runtime stack i.e. SP_EL0 */
180 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
181 mov x20, sp
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100182 msr spsel, #MODE_SP_EL0
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100183 mov sp, x2
184
185 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000186 * Find out whether this is a valid interrupt type.
187 * If the interrupt controller reports a spurious interrupt then return
188 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100189 */
Dan Handley701fea72014-05-27 16:17:21 +0100190 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100191 cmp x0, #INTR_TYPE_INVAL
192 b.eq interrupt_exit_\label
193
194 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000195 * Get the registered handler for this interrupt type.
196 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100197 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000198 * a. An interrupt of a type was routed correctly but a handler for its
199 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100200 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000201 * b. An interrupt of a type was not routed correctly so a handler for
202 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100203 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000204 * c. An interrupt of a type was routed correctly to EL3, but was
205 * deasserted before its pending state could be read. Another
206 * interrupt of a different type pended at the same time and its
207 * type was reported as pending instead. However, a handler for this
208 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100209 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000210 * a. and b. can only happen due to a programming error. The
211 * occurrence of c. could be beyond the control of Trusted Firmware.
212 * It makes sense to return from this exception instead of reporting an
213 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100214 */
215 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100216 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100217 mov x21, x0
218
219 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100220
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100221 /* Set the current security state in the 'flags' parameter */
222 mrs x2, scr_el3
223 ubfx x1, x2, #0, #1
224
225 /* Restore the reference to the 'handle' i.e. SP_EL3 */
226 mov x2, x20
227
Douglas Raillard0980eed2016-11-09 17:48:27 +0000228 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100229 mov x3, xzr
230
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100231 /* Call the interrupt type handler */
232 blr x21
233
234interrupt_exit_\label:
235 /* Return from exception, possibly in a different security state */
236 b el3_exit
237
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100238 .endm
239
240
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100241vector_base runtime_exceptions
242
Douglas Raillard0980eed2016-11-09 17:48:27 +0000243 /* ---------------------------------------------------------------------
244 * Current EL with SP_EL0 : 0x0 - 0x200
245 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100247vector_entry sync_exception_sp_el0
Justin Chadwell83e04882019-08-20 11:01:52 +0100248#ifdef MONITOR_TRAPS
249 stp x29, x30, [sp, #-16]!
250
251 mrs x30, esr_el3
252 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
253
254 /* Check for BRK */
255 cmp x30, #EC_BRK
256 b.eq brk_handler
257
258 ldp x29, x30, [sp], #16
259#endif /* MONITOR_TRAPS */
260
Douglas Raillard0980eed2016-11-09 17:48:27 +0000261 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700262 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100263end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100265vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000266 /*
267 * EL3 code is non-reentrant. Any asynchronous exception is a serious
268 * error. Loop infinitely.
269 */
Julius Werner67ebde72017-07-27 14:59:34 -0700270 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100271end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100273
274vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700275 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100276end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100278
279vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100280 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100281end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100282
Douglas Raillard0980eed2016-11-09 17:48:27 +0000283 /* ---------------------------------------------------------------------
284 * Current EL with SP_ELx: 0x200 - 0x400
285 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100287vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000288 /*
289 * This exception will trigger if anything went wrong during a previous
290 * exception entry or exit or while handling an earlier unexpected
291 * synchronous exception. There is a high probability that SP_EL3 is
292 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000293 */
Julius Werner67ebde72017-07-27 14:59:34 -0700294 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100295end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100296
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100297vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700298 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100299end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000300
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100301vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700302 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100303end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000304
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100305vector_entry serror_sp_elx
Manish Pandeyd419e222023-02-13 12:39:17 +0000306#if !RAS_FFH_SUPPORT
Manish Pandeyb3c61982023-01-06 13:38:03 +0000307 /*
308 * This will trigger if the exception was taken due to SError in EL3 or
309 * because of pending asynchronous external aborts from lower EL that got
310 * triggered due to explicit synchronization in EL3. Refer Note 1.
311 */
312 /* Assumes SP_EL3 on entry */
Manish Pandey66a056e2023-01-11 21:41:07 +0000313 save_x30
Manish Pandeyb3c61982023-01-06 13:38:03 +0000314 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
315 cbnz x30, 1f
316
317 /* Handle asynchronous external abort from lower EL */
318 b handle_lower_el_async_ea
3191:
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500320#endif
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100321 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100322end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100323
Douglas Raillard0980eed2016-11-09 17:48:27 +0000324 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100325 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000326 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100328vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000329 /*
330 * This exception vector will be the entry point for SMCs and traps
331 * that are unhandled at lower ELs most commonly. SP_EL3 should point
332 * to a valid cpu context where the general purpose and system register
333 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000334 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000335 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100336 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100337 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000338 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100339end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100340
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100341vector_entry irq_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000342 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100343 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100344 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100345 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100346end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100347
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100348vector_entry fiq_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000349 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100350 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100351 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100352 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100353end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100354
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100355vector_entry serror_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000356 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100357 apply_at_speculative_wa
Manish Pandeyd419e222023-02-13 12:39:17 +0000358#if RAS_FFH_SUPPORT
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000359 msr daifclr, #DAIF_ABT_BIT
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500360#else
Manish Pandeyb3c61982023-01-06 13:38:03 +0000361 check_and_unmask_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500362#endif
Manish Pandeyc918c182023-01-11 21:53:02 +0000363 b handle_lower_el_async_ea
364
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100365end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100366
Douglas Raillard0980eed2016-11-09 17:48:27 +0000367 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100368 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000369 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100370 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100371vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000372 /*
373 * This exception vector will be the entry point for SMCs and traps
374 * that are unhandled at lower ELs most commonly. SP_EL3 should point
375 * to a valid cpu context where the general purpose and system register
376 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000377 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000378 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100379 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100380 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000381 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100382end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100383
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100384vector_entry irq_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000385 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100386 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100387 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100388 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100389end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100390
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100391vector_entry fiq_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000392 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100393 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100394 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100395 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100396end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100398vector_entry serror_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000399 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100400 apply_at_speculative_wa
Manish Pandeyd419e222023-02-13 12:39:17 +0000401#if RAS_FFH_SUPPORT
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000402 msr daifclr, #DAIF_ABT_BIT
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500403#else
Manish Pandeyb3c61982023-01-06 13:38:03 +0000404 check_and_unmask_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500405#endif
Manish Pandeyc918c182023-01-11 21:53:02 +0000406 b handle_lower_el_async_ea
407
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100408end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000409
Justin Chadwell83e04882019-08-20 11:01:52 +0100410#ifdef MONITOR_TRAPS
411 .section .rodata.brk_string, "aS"
412brk_location:
413 .asciz "Error at instruction 0x"
414brk_message:
415 .asciz "Unexpected BRK instruction with value 0x"
416#endif /* MONITOR_TRAPS */
417
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100418 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000419 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000420 * Depending upon the execution state from where the SMC has been
421 * invoked, it frees some general purpose registers to perform the
422 * remaining tasks. They involve finding the runtime service handler
423 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
424 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000425 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000426 * Note that x30 has been explicitly saved and can be used here
427 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000428 */
Andre Przywarafa914d82022-11-21 17:04:10 +0000429func sync_exception_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000430smc_handler32:
431 /* Check whether aarch32 issued an SMC64 */
432 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
433
Andre Przywarafa914d82022-11-21 17:04:10 +0000434sync_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000435 /* NOTE: The code below must preserve x0-x4 */
436
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100437 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100438 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
Boyan Karatoteved85cf72022-12-06 09:03:42 +0000439 * Also save PMCR_EL0 and set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100440 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000441 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100442
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000443#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100444 /* Load and program APIAKey firmware key */
445 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000446#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000447
Douglas Raillard0980eed2016-11-09 17:48:27 +0000448 /*
449 * Populate the parameters for the SMC handler.
450 * We already have x0-x4 in place. x5 will point to a cookie (not used
451 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000452 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000453 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000454 mov x5, xzr
455 mov x6, sp
456
Douglas Raillard0980eed2016-11-09 17:48:27 +0000457 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100458 * Restore the saved C runtime stack value which will become the new
459 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
460 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000461 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100462 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
463
464 /* Switch to SP_EL0 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100465 msr spsel, #MODE_SP_EL0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000466
Douglas Raillard0980eed2016-11-09 17:48:27 +0000467 /*
Manish Pandey70bbdbd2022-12-07 13:04:20 +0000468 * Save the SPSR_EL3 and ELR_EL3 in case there is a world
Douglas Raillard0980eed2016-11-09 17:48:27 +0000469 * switch during SMC handling.
470 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000471 */
472 mrs x16, spsr_el3
473 mrs x17, elr_el3
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000474 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Manish Pandey70bbdbd2022-12-07 13:04:20 +0000475
476 /* Load SCR_EL3 */
477 mrs x18, scr_el3
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000478
Andre Przywarafa914d82022-11-21 17:04:10 +0000479 /* check for system register traps */
480 mrs x16, esr_el3
481 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH
482 cmp x17, #EC_AARCH64_SYS
483 b.eq sysreg_handler64
484
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500485 /* Clear flag register */
486 mov x7, xzr
487
488#if ENABLE_RME
489 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
490 ubfx x7, x18, #SCR_NSE_SHIFT, 1
491
492 /*
493 * Shift copied SCR_EL3.NSE bit by 5 to create space for
Olivier Deprez33dd8452022-10-11 15:38:27 +0200494 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500495 * the SCR_EL3.NSE bit.
496 */
497 lsl x7, x7, #5
498#endif /* ENABLE_RME */
499
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000500 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
501 bfi x7, x18, #0, #1
502
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +0000503 mov sp, x12
504
505 /*
506 * Per SMCCC documentation, bits [23:17] must be zero for Fast
507 * SMCs. Other values are reserved for future use. Ensure that
508 * these bits are zeroes, if not report as unknown SMC.
509 */
510 tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/
511 tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT)
512 b.ne smc_unknown
513
Olivier Deprez33dd8452022-10-11 15:38:27 +0200514 /*
515 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID
516 * passed through x0. Copy the SVE hint bit to flags and mask the
517 * bit in smc_fid passed to the standard service dispatcher.
518 * A service/dispatcher can retrieve the SVE hint bit state from
519 * flags using the appropriate helper.
520 */
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +00005212:
Olivier Deprez33dd8452022-10-11 15:38:27 +0200522 bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK
523 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
524
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500525 /* Get the unique owning entity number */
526 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
527 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
528 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
529
530 /* Load descriptor index from array of indices */
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -0600531 adrp x14, rt_svc_descs_indices
532 add x14, x14, :lo12:rt_svc_descs_indices
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500533 ldrb w15, [x14, x16]
534
535 /* Any index greater than 127 is invalid. Check bit 7. */
536 tbnz w15, 7, smc_unknown
537
Douglas Raillard0980eed2016-11-09 17:48:27 +0000538 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500539 * Get the descriptor using the index
540 * x11 = (base + off), w15 = index
541 *
542 * handler = (base + off) + (index << log2(size))
543 */
544 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
545 lsl w10, w15, #RT_SVC_SIZE_LOG2
546 ldr x15, [x11, w10, uxtw]
547
548 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000549 * Call the Secure Monitor Call handler and then drop directly into
550 * el3_exit() which will program any remaining architectural state
551 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000552 */
553#if DEBUG
554 cbz x15, rt_svc_fw_critical_error
555#endif
556 blr x15
557
Andre Przywarafa914d82022-11-21 17:04:10 +0000558 b el3_exit
559
560sysreg_handler64:
561 mov x0, x16 /* ESR_EL3, containing syndrome information */
562 mov x1, x6 /* lower EL's context */
563 mov x19, x6 /* save context pointer for after the call */
564 mov sp, x12 /* EL3 runtime stack, as loaded above */
565
566 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */
567 bl handle_sysreg_trap
568 /*
569 * returns:
570 * -1: unhandled trap, panic
571 * 0: handled trap, return to the trapping instruction (repeating it)
572 * 1: handled trap, return to the next instruction
573 */
574
575 tst w0, w0
Govindraj Rajab6709b02023-02-21 17:43:55 +0000576 b.mi elx_panic /* negative return value: panic */
Andre Przywarafa914d82022-11-21 17:04:10 +0000577 b.eq 1f /* zero: do not change ELR_EL3 */
578
579 /* advance the PC to continue after the instruction */
580 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
581 add x1, x1, #4
582 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
5831:
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100584 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100585
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000586smc_unknown:
587 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500588 * Unknown SMC call. Populate return value with SMC_UNK and call
589 * el3_exit() which will restore the remaining architectural state
590 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +0000591 * to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000592 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000593 mov x0, #SMC_UNK
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500594 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
595 b el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000596
597smc_prohibited:
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100598 restore_ptw_el1_sys_regs
599 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100600 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000601 mov x0, #SMC_UNK
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800602 exception_return
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000603
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100604#if DEBUG
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000605rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000606 /* Switch to SP_ELx */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100607 msr spsel, #MODE_SP_ELX
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000608 no_ret report_unhandled_exception
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100609#endif
Andre Przywarafa914d82022-11-21 17:04:10 +0000610endfunc sync_exception_handler
Justin Chadwell83e04882019-08-20 11:01:52 +0100611
612 /* ---------------------------------------------------------------------
613 * The following code handles exceptions caused by BRK instructions.
614 * Following a BRK instruction, the only real valid cause of action is
615 * to print some information and panic, as the code that caused it is
616 * likely in an inconsistent internal state.
617 *
618 * This is initially intended to be used in conjunction with
619 * __builtin_trap.
620 * ---------------------------------------------------------------------
621 */
622#ifdef MONITOR_TRAPS
623func brk_handler
624 /* Extract the ISS */
625 mrs x10, esr_el3
626 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
627
628 /* Ensure the console is initialized */
629 bl plat_crash_console_init
630
631 adr x4, brk_location
632 bl asm_print_str
633 mrs x4, elr_el3
634 bl asm_print_hex
635 bl asm_print_newline
636
637 adr x4, brk_message
638 bl asm_print_str
639 mov x4, x10
640 mov x5, #28
641 bl asm_print_hex_bits
642 bl asm_print_newline
643
644 no_ret plat_panic_handler
645endfunc brk_handler
646#endif /* MONITOR_TRAPS */