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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Harrison Mutaie420d1a2023-04-19 09:30:15 +01002 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Masahiro Yamadac5864d82020-04-22 10:50:12 +09007/*
Chris Kay4b7660a2022-09-29 14:36:53 +01008 * The .data section gets copied from ROM to RAM at runtime. Its LMA should be
9 * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it.
Masahiro Yamadac5864d82020-04-22 10:50:12 +090010 * Its VMA must be page-aligned as it marks the first read/write page.
11 */
12#define DATA_ALIGN 16
13
Masahiro Yamada0b67e562020-03-09 17:39:48 +090014#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010016
17OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
18OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000019ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
21MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010022 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
23 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010024}
25
Chris Kay4b7660a2022-09-29 14:36:53 +010026SECTIONS {
Harrison Mutaie420d1a2023-04-19 09:30:15 +010027 ROM_REGION_START = ORIGIN(ROM);
28 ROM_REGION_LENGTH = LENGTH(ROM);
29 RAM_REGION_START = ORIGIN(RAM);
30 RAM_REGION_LENGTH = LENGTH(RAM);
31
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010032 . = BL1_RO_BASE;
Chris Kay4b7660a2022-09-29 14:36:53 +010033
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000034 ASSERT(. == ALIGN(PAGE_SIZE),
Chris Kay4b7660a2022-09-29 14:36:53 +010035 "BL1_RO_BASE address is not aligned on a page boundary.")
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010036
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010037#if SEPARATE_CODE_AND_RODATA
38 .text . : {
Andrey Skvortsov08526ad2023-09-05 22:09:25 +030039 ASSERT(. == ALIGN(PAGE_SIZE),
40 ".text address is not aligned on a page boundary.");
41
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010042 __TEXT_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010043
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010044 *bl1_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050045 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010046 *(.vectors)
Michal Simek80c530e2023-04-27 14:26:03 +020047 __TEXT_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010048
Roberto Vargasd93fde32018-04-11 11:53:31 +010049 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010050
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010051 __TEXT_END__ = .;
Jorge Troncosoda284d52022-10-20 21:42:06 -070052 } >ROM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010053
Chris Kay4b7660a2022-09-29 14:36:53 +010054 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
Jorge Troncosoda284d52022-10-20 21:42:06 -070055 .ARM.extab . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010056 *(.ARM.extab* .gnu.linkonce.armextab.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070057 } >ROM
Roberto Vargas1d04c632018-05-10 11:01:16 +010058
Jorge Troncosoda284d52022-10-20 21:42:06 -070059 .ARM.exidx . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010060 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070061 } >ROM
Roberto Vargas1d04c632018-05-10 11:01:16 +010062
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010063 .rodata . : {
64 __RODATA_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010065
Samuel Holland23f5e542019-10-20 16:11:25 -050066 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010067
Chris Kay4b7660a2022-09-29 14:36:53 +010068 RODATA_COMMON
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010069
70 /*
71 * No need to pad out the .rodata section to a page boundary. Next is
72 * the .data section, which can mapped in ROM with the same memory
73 * attributes as the .rodata section.
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080074 *
Chris Kay4b7660a2022-09-29 14:36:53 +010075 * Pad out to 16 bytes though as .data section needs to be 16-byte
76 * aligned and lld does not align the LMA to the alignment specified
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -080077 * on the .data section.
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010078 */
Michal Simek80c530e2023-04-27 14:26:03 +020079 __RODATA_END_UNALIGNED__ = .;
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010080 __RODATA_END__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010081
82 . = ALIGN(16);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010083 } >ROM
Chris Kay4b7660a2022-09-29 14:36:53 +010084#else /* SEPARATE_CODE_AND_RODATA */
Chris Kay33bfc5e2023-02-14 11:30:04 +000085 .ro . : {
Andrey Skvortsov08526ad2023-09-05 22:09:25 +030086 ASSERT(. == ALIGN(PAGE_SIZE),
87 ".ro address is not aligned on a page boundary.");
88
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000089 __RO_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010090
Andrew Thoelkee01ea342014-03-18 07:13:52 +000091 *bl1_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050092 *(SORT_BY_ALIGNMENT(.text*))
93 *(SORT_BY_ALIGNMENT(.rodata*))
Soby Mathewc704cbc2014-08-14 11:33:56 +010094
Chris Kay4b7660a2022-09-29 14:36:53 +010095 RODATA_COMMON
Soby Mathewc704cbc2014-08-14 11:33:56 +010096
Achin Guptab739f222014-01-18 16:50:09 +000097 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010098
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000099 __RO_END__ = .;
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -0800100
101 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100102 * Pad out to 16 bytes as the .data section needs to be 16-byte aligned
103 * and lld does not align the LMA to the alignment specified on the
104 * .data section.
Arve Hjønnevåg1488cbe2020-02-07 14:12:35 -0800105 */
Chris Kay4b7660a2022-09-29 14:36:53 +0100106 . = ALIGN(16);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 } >ROM
Chris Kay4b7660a2022-09-29 14:36:53 +0100108#endif /* SEPARATE_CODE_AND_RODATA */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109
Soby Mathewc704cbc2014-08-14 11:33:56 +0100110 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
Chris Kay4b7660a2022-09-29 14:36:53 +0100111 "cpu_ops not defined for this platform.")
Soby Mathewc704cbc2014-08-14 11:33:56 +0100112
Harrison Mutaie420d1a2023-04-19 09:30:15 +0100113 ROM_REGION_END = .;
Douglas Raillard306593d2017-02-24 18:14:15 +0000114 . = BL1_RW_BASE;
Chris Kay4b7660a2022-09-29 14:36:53 +0100115
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000116 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
Chris Kay4b7660a2022-09-29 14:36:53 +0100117 "BL1_RW_BASE address is not aligned on a page boundary.")
Douglas Raillard306593d2017-02-24 18:14:15 +0000118
Masahiro Yamadac5864d82020-04-22 10:50:12 +0900119 DATA_SECTION >RAM AT>ROM
Chris Kay4b7660a2022-09-29 14:36:53 +0100120
Masahiro Yamadac5864d82020-04-22 10:50:12 +0900121 __DATA_RAM_START__ = __DATA_START__;
122 __DATA_RAM_END__ = __DATA_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123
Masahiro Yamada403990e2020-04-07 13:04:24 +0900124 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +0900125 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +0900126 XLAT_TABLE_SECTION >RAM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000127
Soby Mathew2ae20432015-01-08 18:02:44 +0000128#if USE_COHERENT_MEM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000129 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100130 * The base address of the coherent memory section must be page-aligned to
131 * guarantee that the coherent data are stored on their own pages and are
132 * not mixed with normal data. This is required to set up the correct memory
133 * attributes for the coherent data page tables.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000134 */
Chris Kay33bfc5e2023-02-14 11:30:04 +0000135 .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000136 __COHERENT_RAM_START__ = .;
Chris Kay33bfc5e2023-02-14 11:30:04 +0000137 *(.tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000138 __COHERENT_RAM_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +0100139
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000140 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100141 * Memory page(s) mapped to this section will be marked as device
142 * memory. No other unexpected data must creep in. Ensure the rest of
143 * the current memory page is unused.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000144 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100145 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +0100146
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000147 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +0100149#endif /* USE_COHERENT_MEM */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000151 __BL1_RAM_START__ = ADDR(.data);
152 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000154 __DATA_ROM_START__ = LOADADDR(.data);
155 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100156
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100157 /*
158 * The .data section is the last PROGBITS section so its end marks the end
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100159 * of BL1's actual content in Trusted ROM.
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100160 */
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100161 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
Chris Kay4b7660a2022-09-29 14:36:53 +0100162
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100163 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
Chris Kay4b7660a2022-09-29 14:36:53 +0100164 "BL1's ROM content has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100165
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000166 __BSS_SIZE__ = SIZEOF(.bss);
167
Soby Mathew2ae20432015-01-08 18:02:44 +0000168#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000169 __COHERENT_RAM_UNALIGNED_SIZE__ =
170 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Chris Kay4b7660a2022-09-29 14:36:53 +0100171#endif /* USE_COHERENT_MEM */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100173 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Harrison Mutaie420d1a2023-04-19 09:30:15 +0100174 RAM_REGION_END = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175}