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Isla Mitchellea84d6b2017-08-03 16:04:46 +01001/*
Manish Pandey3880a362020-01-24 11:54:44 +00002 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
Isla Mitchellea84d6b2017-08-03 16:04:46 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
John Tsichritzis56369c12019-02-19 13:49:06 +00007#ifndef NEOVERSE_N1_H
8#define NEOVERSE_N1_H
Antonio Nino Diaz9fe40fd2018-10-25 17:11:02 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Isla Mitchellea84d6b2017-08-03 16:04:46 +010011
John Tsichritzis56369c12019-02-19 13:49:06 +000012/* Neoverse N1 MIDR for revision 0 */
13#define NEOVERSE_N1_MIDR U(0x410fd0c0)
Isla Mitchellea84d6b2017-08-03 16:04:46 +010014
laurenw-arm94accd32019-08-20 15:51:24 -050015/* Exception Syndrome register EC code for IC Trap */
16#define NEOVERSE_N1_EC_IC_TRAP U(0x1f)
17
Isla Mitchellea84d6b2017-08-03 16:04:46 +010018/*******************************************************************************
Louis Mayencourtb58142b2019-04-18 14:34:11 +010019 * CPU Power Control register specific definitions.
Isla Mitchellea84d6b2017-08-03 16:04:46 +010020 ******************************************************************************/
John Tsichritzis56369c12019-02-19 13:49:06 +000021#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
Isla Mitchellea84d6b2017-08-03 16:04:46 +010022
John Tsichritzis56369c12019-02-19 13:49:06 +000023/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
24#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
Isla Mitchellea84d6b2017-08-03 16:04:46 +010025
John Tsichritzis56369c12019-02-19 13:49:06 +000026#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4)
Dimitris Papastamos89736dd2018-02-13 11:28:02 +000027
John Tsichritzis56369c12019-02-19 13:49:06 +000028#define NEOVERSE_N1_AMU_NR_COUNTERS U(5)
29#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f)
Dimitris Papastamos89736dd2018-02-13 11:28:02 +000030
Louis Mayencourtb58142b2019-04-18 14:34:11 +010031/*******************************************************************************
32 * CPU Extended Control register specific definitions.
33 ******************************************************************************/
34#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
35
lauwal01197f14c2019-06-24 11:38:53 -050036#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
lauwal0100396bf2019-06-24 11:47:30 -050037#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
Manish Pandey3880a362020-01-24 11:54:44 +000038#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
lauwal01197f14c2019-06-24 11:38:53 -050039
Louis Mayencourtb58142b2019-04-18 14:34:11 +010040/*******************************************************************************
41 * CPU Auxiliary Control register specific definitions.
42 ******************************************************************************/
lauwal01bd555f42019-06-24 11:23:50 -050043#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0
44
45#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
lauwal0142771af2019-06-24 11:44:58 -050046#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
lauwal01bd555f42019-06-24 11:23:50 -050047
Louis Mayencourtb58142b2019-04-18 14:34:11 +010048#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1
49
lauwal01f2adb132019-06-24 11:32:40 -050050#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
Andre Przywarab9347402019-05-20 14:57:06 +010051#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
lauwal01e1590442019-06-24 11:35:37 -050052#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
lauwal01f2adb132019-06-24 11:32:40 -050053#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
Andre Przywarab9347402019-05-20 14:57:06 +010054#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
lauwal01363ee3c2019-06-24 11:28:34 -050055#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
56
lauwal0107c2a232019-06-24 11:42:02 -050057#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2
58
59#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
Louis Mayencourtb58142b2019-04-18 14:34:11 +010060
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010061/* Instruction patching registers */
62#define CPUPSELR_EL3 S3_6_C15_C8_0
63#define CPUPCR_EL3 S3_6_C15_C8_1
64#define CPUPOR_EL3 S3_6_C15_C8_2
65#define CPUPMR_EL3 S3_6_C15_C8_3
66
Pramod Kumarf01ea602020-02-05 11:27:57 +053067/******************************************************************************
68 * CPU Configuration register definitions.
69 *****************************************************************************/
70#define CPUCFR_EL1 S3_0_C15_C0_0
71
72/* SCU bit of CPU Configuration Register, EL1 */
73#define SCU_SHIFT U(2)
74
John Tsichritzis56369c12019-02-19 13:49:06 +000075#endif /* NEOVERSE_N1_H */