Paul Beesley | fc9ee36 | 2019-03-07 15:47:15 +0000 | [diff] [blame] | 1 | Porting Guide |
| 2 | ============= |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 4 | Introduction |
| 5 | ------------ |
| 6 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 7 | Porting Trusted Firmware-A (TF-A) to a new platform involves making some |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 8 | mandatory and optional modifications for both the cold and warm boot paths. |
| 9 | Modifications consist of: |
| 10 | |
| 11 | - Implementing a platform-specific function or variable, |
| 12 | - Setting up the execution context in a certain way, or |
| 13 | - Defining certain constants (for example #defines). |
| 14 | |
| 15 | The platform-specific functions and variables are declared in |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 16 | ``include/plat/common/platform.h``. The firmware provides a default |
| 17 | implementation of variables and functions to fulfill the optional requirements. |
| 18 | These implementations are all weakly defined; they are provided to ease the |
| 19 | porting effort. Each platform port can override them with its own implementation |
| 20 | if the default implementation is inadequate. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 21 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 22 | Some modifications are common to all Boot Loader (BL) stages. Section 2 |
| 23 | discusses these in detail. The subsequent sections discuss the remaining |
| 24 | modifications for each BL stage in detail. |
| 25 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 26 | Please refer to the :ref:`Platform Compatibility Policy` for the policy |
| 27 | regarding compatibility and deprecation of these porting interfaces. |
Soby Mathew | 02bdbb9 | 2018-09-26 11:17:23 +0100 | [diff] [blame] | 28 | |
Antonio Nino Diaz | 645feb4 | 2019-02-13 14:07:38 +0000 | [diff] [blame] | 29 | Only Arm development platforms (such as FVP and Juno) may use the |
| 30 | functions/definitions in ``include/plat/arm/common/`` and the corresponding |
| 31 | source files in ``plat/arm/common/``. This is done so that there are no |
| 32 | dependencies between platforms maintained by different people/companies. If you |
| 33 | want to use any of the functionality present in ``plat/arm`` files, please |
| 34 | create a pull request that moves the code to ``plat/common`` so that it can be |
| 35 | discussed. |
| 36 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 37 | Common modifications |
| 38 | -------------------- |
| 39 | |
| 40 | This section covers the modifications that should be made by the platform for |
| 41 | each BL stage to correctly port the firmware stack. They are categorized as |
| 42 | either mandatory or optional. |
| 43 | |
| 44 | Common mandatory modifications |
| 45 | ------------------------------ |
| 46 | |
| 47 | A platform port must enable the Memory Management Unit (MMU) as well as the |
| 48 | instruction and data caches for each BL stage. Setting up the translation |
| 49 | tables is the responsibility of the platform port because memory maps differ |
| 50 | across platforms. A memory translation library (see ``lib/xlat_tables/``) is |
Sandrine Bailleux | 1861b7a | 2017-07-20 16:11:01 +0100 | [diff] [blame] | 51 | provided to help in this setup. |
| 52 | |
| 53 | Note that although this library supports non-identity mappings, this is intended |
| 54 | only for re-mapping peripheral physical addresses and allows platforms with high |
| 55 | I/O addresses to reduce their virtual address space. All other addresses |
| 56 | corresponding to code and data must currently use an identity mapping. |
| 57 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 58 | Also, the only translation granule size supported in TF-A is 4KB, as various |
| 59 | parts of the code assume that is the case. It is not possible to switch to |
| 60 | 16 KB or 64 KB granule sizes at the moment. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 61 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 62 | In Arm standard platforms, each BL stage configures the MMU in the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 63 | platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses |
| 64 | an identity mapping for all addresses. |
| 65 | |
| 66 | If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a |
| 67 | block of identity mapped secure memory with Device-nGnRE attributes aligned to |
| 68 | page boundary (4K) for each BL stage. All sections which allocate coherent |
| 69 | memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a |
| 70 | section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its |
| 71 | possible for the firmware to place variables in it using the following C code |
| 72 | directive: |
| 73 | |
| 74 | :: |
| 75 | |
| 76 | __section("bakery_lock") |
| 77 | |
| 78 | Or alternatively the following assembler code directive: |
| 79 | |
| 80 | :: |
| 81 | |
| 82 | .section bakery_lock |
| 83 | |
| 84 | The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are |
| 85 | used to allocate any data structures that are accessed both when a CPU is |
| 86 | executing with its MMU and caches enabled, and when it's running with its MMU |
| 87 | and caches disabled. Examples are given below. |
| 88 | |
| 89 | The following variables, functions and constants must be defined by the platform |
| 90 | for the firmware to work correctly. |
| 91 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 92 | File : platform_def.h [mandatory] |
| 93 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 94 | |
| 95 | Each platform must ensure that a header file of this name is in the system |
Antonio Nino Diaz | 50a4d1a | 2019-02-01 12:22:22 +0000 | [diff] [blame] | 96 | include path with the following constants defined. This will require updating |
| 97 | the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 98 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 99 | Platform ports may optionally use the file ``include/plat/common/common_def.h``, |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 100 | which provides typical values for some of the constants below. These values are |
| 101 | likely to be suitable for all platform ports. |
| 102 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 103 | - **#define : PLATFORM_LINKER_FORMAT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 104 | |
| 105 | Defines the linker format used by the platform, for example |
| 106 | ``elf64-littleaarch64``. |
| 107 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 108 | - **#define : PLATFORM_LINKER_ARCH** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 109 | |
| 110 | Defines the processor architecture for the linker by the platform, for |
| 111 | example ``aarch64``. |
| 112 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 113 | - **#define : PLATFORM_STACK_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 114 | |
| 115 | Defines the normal stack memory available to each CPU. This constant is used |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 116 | by ``plat/common/aarch64/platform_mp_stack.S`` and |
| 117 | ``plat/common/aarch64/platform_up_stack.S``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 118 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 119 | - **define : CACHE_WRITEBACK_GRANULE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 120 | |
| 121 | Defines the size in bits of the largest cache line across all the cache |
| 122 | levels in the platform. |
| 123 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 124 | - **#define : FIRMWARE_WELCOME_STR** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 125 | |
| 126 | Defines the character string printed by BL1 upon entry into the ``bl1_main()`` |
| 127 | function. |
| 128 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 129 | - **#define : PLATFORM_CORE_COUNT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 130 | |
| 131 | Defines the total number of CPUs implemented by the platform across all |
| 132 | clusters in the system. |
| 133 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 134 | - **#define : PLAT_NUM_PWR_DOMAINS** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 135 | |
| 136 | Defines the total number of nodes in the power domain topology |
| 137 | tree at all the power domain levels used by the platform. |
| 138 | This macro is used by the PSCI implementation to allocate |
| 139 | data structures to represent power domain topology. |
| 140 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 141 | - **#define : PLAT_MAX_PWR_LVL** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 142 | |
| 143 | Defines the maximum power domain level that the power management operations |
| 144 | should apply to. More often, but not always, the power domain level |
| 145 | corresponds to affinity level. This macro allows the PSCI implementation |
| 146 | to know the highest power domain level that it should consider for power |
| 147 | management operations in the system that the platform implements. For |
| 148 | example, the Base AEM FVP implements two clusters with a configurable |
| 149 | number of CPUs and it reports the maximum power domain level as 1. |
| 150 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 151 | - **#define : PLAT_MAX_OFF_STATE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 152 | |
| 153 | Defines the local power state corresponding to the deepest power down |
| 154 | possible at every power domain level in the platform. The local power |
| 155 | states for each level may be sparsely allocated between 0 and this value |
| 156 | with 0 being reserved for the RUN state. The PSCI implementation uses this |
| 157 | value to initialize the local power states of the power domain nodes and |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 158 | to specify the requested power state for a PSCI_CPU_OFF call. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 159 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 160 | - **#define : PLAT_MAX_RET_STATE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 161 | |
| 162 | Defines the local power state corresponding to the deepest retention state |
| 163 | possible at every power domain level in the platform. This macro should be |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 164 | a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 165 | PSCI implementation to distinguish between retention and power down local |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 166 | power states within PSCI_CPU_SUSPEND call. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 167 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 168 | - **#define : PLAT_MAX_PWR_LVL_STATES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 169 | |
| 170 | Defines the maximum number of local power states per power domain level |
| 171 | that the platform supports. The default value of this macro is 2 since |
| 172 | most platforms just support a maximum of two local power states at each |
| 173 | power domain level (power-down and retention). If the platform needs to |
| 174 | account for more local power states, then it must redefine this macro. |
| 175 | |
| 176 | Currently, this macro is used by the Generic PSCI implementation to size |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 177 | the array used for PSCI_STAT_COUNT/RESIDENCY accounting. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 178 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 179 | - **#define : BL1_RO_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 180 | |
| 181 | Defines the base address in secure ROM where BL1 originally lives. Must be |
| 182 | aligned on a page-size boundary. |
| 183 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 184 | - **#define : BL1_RO_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 185 | |
| 186 | Defines the maximum address in secure ROM that BL1's actual content (i.e. |
| 187 | excluding any data section allocated at runtime) can occupy. |
| 188 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 189 | - **#define : BL1_RW_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 190 | |
| 191 | Defines the base address in secure RAM where BL1's read-write data will live |
| 192 | at runtime. Must be aligned on a page-size boundary. |
| 193 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 194 | - **#define : BL1_RW_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 195 | |
| 196 | Defines the maximum address in secure RAM that BL1's read-write data can |
| 197 | occupy at runtime. |
| 198 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 199 | - **#define : BL2_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 200 | |
| 201 | Defines the base address in secure RAM where BL1 loads the BL2 binary image. |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 202 | Must be aligned on a page-size boundary. This constant is not applicable |
| 203 | when BL2_IN_XIP_MEM is set to '1'. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 204 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 205 | - **#define : BL2_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 206 | |
| 207 | Defines the maximum address in secure RAM that the BL2 image can occupy. |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 208 | This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. |
| 209 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 210 | - **#define : BL2_RO_BASE** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 211 | |
| 212 | Defines the base address in secure XIP memory where BL2 RO section originally |
| 213 | lives. Must be aligned on a page-size boundary. This constant is only needed |
| 214 | when BL2_IN_XIP_MEM is set to '1'. |
| 215 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 216 | - **#define : BL2_RO_LIMIT** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 217 | |
| 218 | Defines the maximum address in secure XIP memory that BL2's actual content |
| 219 | (i.e. excluding any data section allocated at runtime) can occupy. This |
| 220 | constant is only needed when BL2_IN_XIP_MEM is set to '1'. |
| 221 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 222 | - **#define : BL2_RW_BASE** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 223 | |
| 224 | Defines the base address in secure RAM where BL2's read-write data will live |
| 225 | at runtime. Must be aligned on a page-size boundary. This constant is only |
| 226 | needed when BL2_IN_XIP_MEM is set to '1'. |
| 227 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 228 | - **#define : BL2_RW_LIMIT** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 229 | |
| 230 | Defines the maximum address in secure RAM that BL2's read-write data can |
| 231 | occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set |
| 232 | to '1'. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 233 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 234 | - **#define : BL31_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 235 | |
| 236 | Defines the base address in secure RAM where BL2 loads the BL31 binary |
| 237 | image. Must be aligned on a page-size boundary. |
| 238 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 239 | - **#define : BL31_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 240 | |
| 241 | Defines the maximum address in secure RAM that the BL31 image can occupy. |
| 242 | |
| 243 | For every image, the platform must define individual identifiers that will be |
| 244 | used by BL1 or BL2 to load the corresponding image into memory from non-volatile |
| 245 | storage. For the sake of performance, integer numbers will be used as |
| 246 | identifiers. The platform will use those identifiers to return the relevant |
| 247 | information about the image to be loaded (file handler, load address, |
| 248 | authentication information, etc.). The following image identifiers are |
| 249 | mandatory: |
| 250 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 251 | - **#define : BL2_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 252 | |
| 253 | BL2 image identifier, used by BL1 to load BL2. |
| 254 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 255 | - **#define : BL31_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 256 | |
| 257 | BL31 image identifier, used by BL2 to load BL31. |
| 258 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 259 | - **#define : BL33_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 260 | |
| 261 | BL33 image identifier, used by BL2 to load BL33. |
| 262 | |
| 263 | If Trusted Board Boot is enabled, the following certificate identifiers must |
| 264 | also be defined: |
| 265 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 266 | - **#define : TRUSTED_BOOT_FW_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 267 | |
| 268 | BL2 content certificate identifier, used by BL1 to load the BL2 content |
| 269 | certificate. |
| 270 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 271 | - **#define : TRUSTED_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 272 | |
| 273 | Trusted key certificate identifier, used by BL2 to load the trusted key |
| 274 | certificate. |
| 275 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 276 | - **#define : SOC_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 277 | |
| 278 | BL31 key certificate identifier, used by BL2 to load the BL31 key |
| 279 | certificate. |
| 280 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 281 | - **#define : SOC_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 282 | |
| 283 | BL31 content certificate identifier, used by BL2 to load the BL31 content |
| 284 | certificate. |
| 285 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 286 | - **#define : NON_TRUSTED_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 287 | |
| 288 | BL33 key certificate identifier, used by BL2 to load the BL33 key |
| 289 | certificate. |
| 290 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 291 | - **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 292 | |
| 293 | BL33 content certificate identifier, used by BL2 to load the BL33 content |
| 294 | certificate. |
| 295 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 296 | - **#define : FWU_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 297 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 298 | Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 299 | FWU content certificate. |
| 300 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 301 | - **#define : PLAT_CRYPTOCELL_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 302 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 303 | This defines the base address of Arm® TrustZone® CryptoCell and must be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 304 | defined if CryptoCell crypto driver is used for Trusted Board Boot. For |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 305 | capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 306 | set. |
| 307 | |
| 308 | If the AP Firmware Updater Configuration image, BL2U is used, the following |
| 309 | must also be defined: |
| 310 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 311 | - **#define : BL2U_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 312 | |
| 313 | Defines the base address in secure memory where BL1 copies the BL2U binary |
| 314 | image. Must be aligned on a page-size boundary. |
| 315 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 316 | - **#define : BL2U_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 317 | |
| 318 | Defines the maximum address in secure memory that the BL2U image can occupy. |
| 319 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 320 | - **#define : BL2U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 321 | |
| 322 | BL2U image identifier, used by BL1 to fetch an image descriptor |
| 323 | corresponding to BL2U. |
| 324 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 325 | If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 326 | must also be defined: |
| 327 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 328 | - **#define : SCP_BL2U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 329 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 330 | SCP_BL2U image identifier, used by BL1 to fetch an image descriptor |
| 331 | corresponding to SCP_BL2U. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 332 | |
| 333 | .. note:: |
| 334 | TF-A does not provide source code for this image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 335 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 336 | If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 337 | also be defined: |
| 338 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 339 | - **#define : NS_BL1U_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 340 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 341 | Defines the base address in non-secure ROM where NS_BL1U executes. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 342 | Must be aligned on a page-size boundary. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 343 | |
| 344 | .. note:: |
| 345 | TF-A does not provide source code for this image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 346 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 347 | - **#define : NS_BL1U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 348 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 349 | NS_BL1U image identifier, used by BL1 to fetch an image descriptor |
| 350 | corresponding to NS_BL1U. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 351 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 352 | If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 353 | be defined: |
| 354 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 355 | - **#define : NS_BL2U_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 356 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 357 | Defines the base address in non-secure memory where NS_BL2U executes. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 358 | Must be aligned on a page-size boundary. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 359 | |
| 360 | .. note:: |
| 361 | TF-A does not provide source code for this image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 362 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 363 | - **#define : NS_BL2U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 364 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 365 | NS_BL2U image identifier, used by BL1 to fetch an image descriptor |
| 366 | corresponding to NS_BL2U. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 367 | |
| 368 | For the the Firmware update capability of TRUSTED BOARD BOOT, the following |
| 369 | macros may also be defined: |
| 370 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 371 | - **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 372 | |
| 373 | Total number of images that can be loaded simultaneously. If the platform |
| 374 | doesn't specify any value, it defaults to 10. |
| 375 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 376 | If a SCP_BL2 image is supported by the platform, the following constants must |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 377 | also be defined: |
| 378 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 379 | - **#define : SCP_BL2_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 380 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 381 | SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 382 | from platform storage before being transferred to the SCP. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 383 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 384 | - **#define : SCP_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 385 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 386 | SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 387 | certificate (mandatory when Trusted Board Boot is enabled). |
| 388 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 389 | - **#define : SCP_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 390 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 391 | SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 392 | content certificate (mandatory when Trusted Board Boot is enabled). |
| 393 | |
| 394 | If a BL32 image is supported by the platform, the following constants must |
| 395 | also be defined: |
| 396 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 397 | - **#define : BL32_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 398 | |
| 399 | BL32 image identifier, used by BL2 to load BL32. |
| 400 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 401 | - **#define : TRUSTED_OS_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 402 | |
| 403 | BL32 key certificate identifier, used by BL2 to load the BL32 key |
| 404 | certificate (mandatory when Trusted Board Boot is enabled). |
| 405 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 406 | - **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 407 | |
| 408 | BL32 content certificate identifier, used by BL2 to load the BL32 content |
| 409 | certificate (mandatory when Trusted Board Boot is enabled). |
| 410 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 411 | - **#define : BL32_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 412 | |
| 413 | Defines the base address in secure memory where BL2 loads the BL32 binary |
| 414 | image. Must be aligned on a page-size boundary. |
| 415 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 416 | - **#define : BL32_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 417 | |
| 418 | Defines the maximum address that the BL32 image can occupy. |
| 419 | |
| 420 | If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the |
| 421 | platform, the following constants must also be defined: |
| 422 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 423 | - **#define : TSP_SEC_MEM_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 424 | |
| 425 | Defines the base address of the secure memory used by the TSP image on the |
| 426 | platform. This must be at the same address or below ``BL32_BASE``. |
| 427 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 428 | - **#define : TSP_SEC_MEM_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 429 | |
| 430 | Defines the size of the secure memory used by the BL32 image on the |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 431 | platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully |
| 432 | accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` |
| 433 | and ``BL32_LIMIT``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 434 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 435 | - **#define : TSP_IRQ_SEC_PHY_TIMER** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 436 | |
| 437 | Defines the ID of the secure physical generic timer interrupt used by the |
| 438 | TSP's interrupt handling code. |
| 439 | |
| 440 | If the platform port uses the translation table library code, the following |
| 441 | constants must also be defined: |
| 442 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 443 | - **#define : PLAT_XLAT_TABLES_DYNAMIC** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 444 | |
| 445 | Optional flag that can be set per-image to enable the dynamic allocation of |
| 446 | regions even when the MMU is enabled. If not defined, only static |
| 447 | functionality will be available, if defined and set to 1 it will also |
| 448 | include the dynamic functionality. |
| 449 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 450 | - **#define : MAX_XLAT_TABLES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 451 | |
| 452 | Defines the maximum number of translation tables that are allocated by the |
| 453 | translation table library code. To minimize the amount of runtime memory |
| 454 | used, choose the smallest value needed to map the required virtual addresses |
| 455 | for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL |
| 456 | image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions |
| 457 | as well. |
| 458 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 459 | - **#define : MAX_MMAP_REGIONS** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 460 | |
| 461 | Defines the maximum number of regions that are allocated by the translation |
| 462 | table library code. A region consists of physical base address, virtual base |
| 463 | address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as |
| 464 | defined in the ``mmap_region_t`` structure. The platform defines the regions |
| 465 | that should be mapped. Then, the translation table library will create the |
| 466 | corresponding tables and descriptors at runtime. To minimize the amount of |
| 467 | runtime memory used, choose the smallest value needed to register the |
| 468 | required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is |
| 469 | enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate |
| 470 | the dynamic regions as well. |
| 471 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 472 | - **#define : PLAT_VIRT_ADDR_SPACE_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 473 | |
| 474 | Defines the total size of the virtual address space in bytes. For example, |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 475 | for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 476 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 477 | - **#define : PLAT_PHY_ADDR_SPACE_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 478 | |
| 479 | Defines the total size of the physical address space in bytes. For example, |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 480 | for a 32 bit physical address space, this value should be ``(1ULL << 32)``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 481 | |
| 482 | If the platform port uses the IO storage framework, the following constants |
| 483 | must also be defined: |
| 484 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 485 | - **#define : MAX_IO_DEVICES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 486 | |
| 487 | Defines the maximum number of registered IO devices. Attempting to register |
| 488 | more devices than this value using ``io_register_device()`` will fail with |
| 489 | -ENOMEM. |
| 490 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 491 | - **#define : MAX_IO_HANDLES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 492 | |
| 493 | Defines the maximum number of open IO handles. Attempting to open more IO |
| 494 | entities than this value using ``io_open()`` will fail with -ENOMEM. |
| 495 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 496 | - **#define : MAX_IO_BLOCK_DEVICES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 497 | |
| 498 | Defines the maximum number of registered IO block devices. Attempting to |
| 499 | register more devices this value using ``io_dev_open()`` will fail |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 500 | with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 501 | With this macro, multiple block devices could be supported at the same |
| 502 | time. |
| 503 | |
| 504 | If the platform needs to allocate data within the per-cpu data framework in |
| 505 | BL31, it should define the following macro. Currently this is only required if |
| 506 | the platform decides not to use the coherent memory section by undefining the |
| 507 | ``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the |
| 508 | required memory within the the per-cpu data to minimize wastage. |
| 509 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 510 | - **#define : PLAT_PCPU_DATA_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 511 | |
| 512 | Defines the memory (in bytes) to be reserved within the per-cpu data |
| 513 | structure for use by the platform layer. |
| 514 | |
| 515 | The following constants are optional. They should be defined when the platform |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 516 | memory layout implies some image overlaying like in Arm standard platforms. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 517 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 518 | - **#define : BL31_PROGBITS_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 519 | |
| 520 | Defines the maximum address in secure RAM that the BL31's progbits sections |
| 521 | can occupy. |
| 522 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 523 | - **#define : TSP_PROGBITS_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 524 | |
| 525 | Defines the maximum address that the TSP's progbits sections can occupy. |
| 526 | |
| 527 | If the platform port uses the PL061 GPIO driver, the following constant may |
| 528 | optionally be defined: |
| 529 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 530 | - **PLAT_PL061_MAX_GPIOS** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 531 | Maximum number of GPIOs required by the platform. This allows control how |
| 532 | much memory is allocated for PL061 GPIO controllers. The default value is |
| 533 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 534 | #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 535 | |
| 536 | If the platform port uses the partition driver, the following constant may |
| 537 | optionally be defined: |
| 538 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 539 | - **PLAT_PARTITION_MAX_ENTRIES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 540 | Maximum number of partition entries required by the platform. This allows |
| 541 | control how much memory is allocated for partition entries. The default |
| 542 | value is 128. |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 543 | For example, define the build flag in ``platform.mk``: |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 544 | PLAT_PARTITION_MAX_ENTRIES := 12 |
| 545 | $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 546 | |
Haojian Zhuang | 42a746d | 2019-09-14 18:01:16 +0800 | [diff] [blame] | 547 | - **PLAT_PARTITION_BLOCK_SIZE** |
| 548 | The size of partition block. It could be either 512 bytes or 4096 bytes. |
| 549 | The default value is 512. |
Paul Beesley | f2ec714 | 2019-10-04 16:17:46 +0000 | [diff] [blame] | 550 | For example, define the build flag in ``platform.mk``: |
Haojian Zhuang | 42a746d | 2019-09-14 18:01:16 +0800 | [diff] [blame] | 551 | PLAT_PARTITION_BLOCK_SIZE := 4096 |
| 552 | $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) |
| 553 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 554 | The following constant is optional. It should be defined to override the default |
| 555 | behaviour of the ``assert()`` function (for example, to save memory). |
| 556 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 557 | - **PLAT_LOG_LEVEL_ASSERT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 558 | If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, |
| 559 | ``assert()`` prints the name of the file, the line number and the asserted |
| 560 | expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file |
| 561 | name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it |
| 562 | doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't |
| 563 | defined, it defaults to ``LOG_LEVEL``. |
| 564 | |
Dimitris Papastamos | 60346db | 2017-12-13 10:54:37 +0000 | [diff] [blame] | 565 | If the platform port uses the Activity Monitor Unit, the following constants |
| 566 | may be defined: |
| 567 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 568 | - **PLAT_AMU_GROUP1_COUNTERS_MASK** |
Dimitris Papastamos | 60346db | 2017-12-13 10:54:37 +0000 | [diff] [blame] | 569 | This mask reflects the set of group counters that should be enabled. The |
| 570 | maximum number of group 1 counters supported by AMUv1 is 16 so the mask |
| 571 | can be at most 0xffff. If the platform does not define this mask, no group 1 |
| 572 | counters are enabled. If the platform defines this mask, the following |
| 573 | constant needs to also be defined. |
| 574 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 575 | - **PLAT_AMU_GROUP1_NR_COUNTERS** |
Dimitris Papastamos | 60346db | 2017-12-13 10:54:37 +0000 | [diff] [blame] | 576 | This value is used to allocate an array to save and restore the counters |
| 577 | specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. |
| 578 | This value should be equal to the highest bit position set in the |
| 579 | mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. |
| 580 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 581 | File : plat_macros.S [mandatory] |
| 582 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 583 | |
| 584 | Each platform must ensure a file of this name is in the system include path with |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 585 | the following macro defined. In the Arm development platforms, this file is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 586 | found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. |
| 587 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 588 | - **Macro : plat_crash_print_regs** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 589 | |
| 590 | This macro allows the crash reporting routine to print relevant platform |
| 591 | registers in case of an unhandled exception in BL31. This aids in debugging |
| 592 | and this macro can be defined to be empty in case register reporting is not |
| 593 | desired. |
| 594 | |
| 595 | For instance, GIC or interconnect registers may be helpful for |
| 596 | troubleshooting. |
| 597 | |
| 598 | Handling Reset |
| 599 | -------------- |
| 600 | |
| 601 | BL1 by default implements the reset vector where execution starts from a cold |
| 602 | or warm boot. BL31 can be optionally set as a reset vector using the |
| 603 | ``RESET_TO_BL31`` make variable. |
| 604 | |
| 605 | For each CPU, the reset vector code is responsible for the following tasks: |
| 606 | |
| 607 | #. Distinguishing between a cold boot and a warm boot. |
| 608 | |
| 609 | #. In the case of a cold boot and the CPU being a secondary CPU, ensuring that |
| 610 | the CPU is placed in a platform-specific state until the primary CPU |
| 611 | performs the necessary steps to remove it from this state. |
| 612 | |
| 613 | #. In the case of a warm boot, ensuring that the CPU jumps to a platform- |
| 614 | specific address in the BL31 image in the same processor mode as it was |
| 615 | when released from reset. |
| 616 | |
| 617 | The following functions need to be implemented by the platform port to enable |
| 618 | reset vector code to perform the above tasks. |
| 619 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 620 | Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] |
| 621 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 622 | |
| 623 | :: |
| 624 | |
| 625 | Argument : void |
| 626 | Return : uintptr_t |
| 627 | |
| 628 | This function is called with the MMU and caches disabled |
| 629 | (``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for |
| 630 | distinguishing between a warm and cold reset for the current CPU using |
| 631 | platform-specific means. If it's a warm reset, then it returns the warm |
| 632 | reset entrypoint point provided to ``plat_setup_psci_ops()`` during |
| 633 | BL31 initialization. If it's a cold reset then this function must return zero. |
| 634 | |
| 635 | This function does not follow the Procedure Call Standard used by the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 636 | Application Binary Interface for the Arm 64-bit architecture. The caller should |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 637 | not assume that callee saved registers are preserved across a call to this |
| 638 | function. |
| 639 | |
| 640 | This function fulfills requirement 1 and 3 listed above. |
| 641 | |
| 642 | Note that for platforms that support programming the reset address, it is |
| 643 | expected that a CPU will start executing code directly at the right address, |
| 644 | both on a cold and warm reset. In this case, there is no need to identify the |
| 645 | type of reset nor to query the warm reset entrypoint. Therefore, implementing |
| 646 | this function is not required on such platforms. |
| 647 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 648 | Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] |
| 649 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 650 | |
| 651 | :: |
| 652 | |
| 653 | Argument : void |
| 654 | |
| 655 | This function is called with the MMU and data caches disabled. It is responsible |
| 656 | for placing the executing secondary CPU in a platform-specific state until the |
| 657 | primary CPU performs the necessary actions to bring it out of that state and |
| 658 | allow entry into the OS. This function must not return. |
| 659 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 660 | In the Arm FVP port, when using the normal boot flow, each secondary CPU powers |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 661 | itself off. The primary CPU is responsible for powering up the secondary CPUs |
| 662 | when normal world software requires them. When booting an EL3 payload instead, |
| 663 | they stay powered on and are put in a holding pen until their mailbox gets |
| 664 | populated. |
| 665 | |
| 666 | This function fulfills requirement 2 above. |
| 667 | |
| 668 | Note that for platforms that can't release secondary CPUs out of reset, only the |
| 669 | primary CPU will execute the cold boot code. Therefore, implementing this |
| 670 | function is not required on such platforms. |
| 671 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 672 | Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] |
| 673 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 674 | |
| 675 | :: |
| 676 | |
| 677 | Argument : void |
| 678 | Return : unsigned int |
| 679 | |
| 680 | This function identifies whether the current CPU is the primary CPU or a |
| 681 | secondary CPU. A return value of zero indicates that the CPU is not the |
| 682 | primary CPU, while a non-zero return value indicates that the CPU is the |
| 683 | primary CPU. |
| 684 | |
| 685 | Note that for platforms that can't release secondary CPUs out of reset, only the |
| 686 | primary CPU will execute the cold boot code. Therefore, there is no need to |
| 687 | distinguish between primary and secondary CPUs and implementing this function is |
| 688 | not required. |
| 689 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 690 | Function : platform_mem_init() [mandatory] |
| 691 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 692 | |
| 693 | :: |
| 694 | |
| 695 | Argument : void |
| 696 | Return : void |
| 697 | |
| 698 | This function is called before any access to data is made by the firmware, in |
| 699 | order to carry out any essential memory initialization. |
| 700 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 701 | Function: plat_get_rotpk_info() |
| 702 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 703 | |
| 704 | :: |
| 705 | |
| 706 | Argument : void *, void **, unsigned int *, unsigned int * |
| 707 | Return : int |
| 708 | |
| 709 | This function is mandatory when Trusted Board Boot is enabled. It returns a |
| 710 | pointer to the ROTPK stored in the platform (or a hash of it) and its length. |
| 711 | The ROTPK must be encoded in DER format according to the following ASN.1 |
| 712 | structure: |
| 713 | |
| 714 | :: |
| 715 | |
| 716 | AlgorithmIdentifier ::= SEQUENCE { |
| 717 | algorithm OBJECT IDENTIFIER, |
| 718 | parameters ANY DEFINED BY algorithm OPTIONAL |
| 719 | } |
| 720 | |
| 721 | SubjectPublicKeyInfo ::= SEQUENCE { |
| 722 | algorithm AlgorithmIdentifier, |
| 723 | subjectPublicKey BIT STRING |
| 724 | } |
| 725 | |
| 726 | In case the function returns a hash of the key: |
| 727 | |
| 728 | :: |
| 729 | |
| 730 | DigestInfo ::= SEQUENCE { |
| 731 | digestAlgorithm AlgorithmIdentifier, |
| 732 | digest OCTET STRING |
| 733 | } |
| 734 | |
| 735 | The function returns 0 on success. Any other value is treated as error by the |
| 736 | Trusted Board Boot. The function also reports extra information related |
| 737 | to the ROTPK in the flags parameter: |
| 738 | |
| 739 | :: |
| 740 | |
| 741 | ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a |
| 742 | hash. |
| 743 | ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK |
| 744 | verification while the platform ROTPK is not deployed. |
| 745 | When this flag is set, the function does not need to |
| 746 | return a platform ROTPK, and the authentication |
| 747 | framework uses the ROTPK in the certificate without |
| 748 | verifying it against the platform value. This flag |
| 749 | must not be used in a deployed production environment. |
| 750 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 751 | Function: plat_get_nv_ctr() |
| 752 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 753 | |
| 754 | :: |
| 755 | |
| 756 | Argument : void *, unsigned int * |
| 757 | Return : int |
| 758 | |
| 759 | This function is mandatory when Trusted Board Boot is enabled. It returns the |
| 760 | non-volatile counter value stored in the platform in the second argument. The |
| 761 | cookie in the first argument may be used to select the counter in case the |
| 762 | platform provides more than one (for example, on platforms that use the default |
| 763 | TBBR CoT, the cookie will correspond to the OID values defined in |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 764 | TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 765 | |
| 766 | The function returns 0 on success. Any other value means the counter value could |
| 767 | not be retrieved from the platform. |
| 768 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 769 | Function: plat_set_nv_ctr() |
| 770 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 771 | |
| 772 | :: |
| 773 | |
| 774 | Argument : void *, unsigned int |
| 775 | Return : int |
| 776 | |
| 777 | This function is mandatory when Trusted Board Boot is enabled. It sets a new |
| 778 | counter value in the platform. The cookie in the first argument may be used to |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 779 | select the counter (as explained in plat_get_nv_ctr()). The second argument is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 780 | the updated counter value to be written to the NV counter. |
| 781 | |
| 782 | The function returns 0 on success. Any other value means the counter value could |
| 783 | not be updated. |
| 784 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 785 | Function: plat_set_nv_ctr2() |
| 786 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 787 | |
| 788 | :: |
| 789 | |
| 790 | Argument : void *, const auth_img_desc_t *, unsigned int |
| 791 | Return : int |
| 792 | |
| 793 | This function is optional when Trusted Board Boot is enabled. If this |
| 794 | interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The |
| 795 | first argument passed is a cookie and is typically used to |
| 796 | differentiate between a Non Trusted NV Counter and a Trusted NV |
| 797 | Counter. The second argument is a pointer to an authentication image |
| 798 | descriptor and may be used to decide if the counter is allowed to be |
| 799 | updated or not. The third argument is the updated counter value to |
| 800 | be written to the NV counter. |
| 801 | |
| 802 | The function returns 0 on success. Any other value means the counter value |
| 803 | either could not be updated or the authentication image descriptor indicates |
| 804 | that it is not allowed to be updated. |
| 805 | |
| 806 | Common mandatory function modifications |
| 807 | --------------------------------------- |
| 808 | |
| 809 | The following functions are mandatory functions which need to be implemented |
| 810 | by the platform port. |
| 811 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 812 | Function : plat_my_core_pos() |
| 813 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 814 | |
| 815 | :: |
| 816 | |
| 817 | Argument : void |
| 818 | Return : unsigned int |
| 819 | |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 820 | This function returns the index of the calling CPU which is used as a |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 821 | CPU-specific linear index into blocks of memory (for example while allocating |
| 822 | per-CPU stacks). This function will be invoked very early in the |
| 823 | initialization sequence which mandates that this function should be |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 824 | implemented in assembly and should not rely on the availability of a C |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 825 | runtime environment. This function can clobber x0 - x8 and must preserve |
| 826 | x9 - x29. |
| 827 | |
| 828 | This function plays a crucial role in the power domain topology framework in |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 829 | PSCI and details of this can be found in |
| 830 | :ref:`PSCI Power Domain Tree Structure`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 831 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 832 | Function : plat_core_pos_by_mpidr() |
| 833 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 834 | |
| 835 | :: |
| 836 | |
| 837 | Argument : u_register_t |
| 838 | Return : int |
| 839 | |
| 840 | This function validates the ``MPIDR`` of a CPU and converts it to an index, |
| 841 | which can be used as a CPU-specific linear index into blocks of memory. In |
| 842 | case the ``MPIDR`` is invalid, this function returns -1. This function will only |
| 843 | be invoked by BL31 after the power domain topology is initialized and can |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 844 | utilize the C runtime environment. For further details about how TF-A |
| 845 | represents the power domain topology and how this relates to the linear CPU |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 846 | index, please refer :ref:`PSCI Power Domain Tree Structure`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 847 | |
Ambroise Vincent | d207f56 | 2019-04-10 12:50:27 +0100 | [diff] [blame] | 848 | Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] |
| 849 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 850 | |
| 851 | :: |
| 852 | |
| 853 | Arguments : void **heap_addr, size_t *heap_size |
| 854 | Return : int |
| 855 | |
| 856 | This function is invoked during Mbed TLS library initialisation to get a heap, |
| 857 | by means of a starting address and a size. This heap will then be used |
| 858 | internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS |
| 859 | must be able to provide a heap to it. |
| 860 | |
| 861 | A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in |
| 862 | which a heap is statically reserved during compile time inside every image |
| 863 | (i.e. every BL stage) that utilises Mbed TLS. In this default implementation, |
| 864 | the function simply returns the address and size of this "pre-allocated" heap. |
| 865 | For a platform to use this default implementation, only a call to the helper |
| 866 | from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. |
| 867 | |
| 868 | However, by writting their own implementation, platforms have the potential to |
| 869 | optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is |
| 870 | shared between BL1 and BL2 stages and, thus, the necessary space is not reserved |
| 871 | twice. |
| 872 | |
| 873 | On success the function should return 0 and a negative error code otherwise. |
| 874 | |
Sumit Garg | c0c369c | 2019-11-15 18:47:53 +0530 | [diff] [blame] | 875 | Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] |
| 876 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 877 | |
| 878 | :: |
| 879 | |
| 880 | Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, |
| 881 | size_t *key_len, unsigned int *flags, const uint8_t *img_id, |
| 882 | size_t img_id_len |
| 883 | Return : int |
| 884 | |
| 885 | This function provides a symmetric key (either SSK or BSSK depending on |
| 886 | fw_enc_status) which is invoked during runtime decryption of encrypted |
| 887 | firmware images. `plat/common/plat_bl_common.c` provides a dummy weak |
| 888 | implementation for testing purposes which must be overridden by the platform |
| 889 | trying to implement a real world firmware encryption use-case. |
| 890 | |
| 891 | It also allows the platform to pass symmetric key identifier rather than |
| 892 | actual symmetric key which is useful in cases where the crypto backend provides |
| 893 | secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` |
| 894 | flag must be set in ``flags``. |
| 895 | |
| 896 | In addition to above a platform may also choose to provide an image specific |
| 897 | symmetric key/identifier using img_id. |
| 898 | |
| 899 | On success the function should return 0 and a negative error code otherwise. |
| 900 | |
| 901 | Note that this API depends on ``DECRYPTION_SUPPORT`` build flag which is |
| 902 | marked as experimental. |
| 903 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 904 | Common optional modifications |
| 905 | ----------------------------- |
| 906 | |
| 907 | The following are helper functions implemented by the firmware that perform |
| 908 | common platform-specific tasks. A platform may choose to override these |
| 909 | definitions. |
| 910 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 911 | Function : plat_set_my_stack() |
| 912 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 913 | |
| 914 | :: |
| 915 | |
| 916 | Argument : void |
| 917 | Return : void |
| 918 | |
| 919 | This function sets the current stack pointer to the normal memory stack that |
| 920 | has been allocated for the current CPU. For BL images that only require a |
| 921 | stack for the primary CPU, the UP version of the function is used. The size |
| 922 | of the stack allocated to each CPU is specified by the platform defined |
| 923 | constant ``PLATFORM_STACK_SIZE``. |
| 924 | |
| 925 | Common implementations of this function for the UP and MP BL images are |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 926 | provided in ``plat/common/aarch64/platform_up_stack.S`` and |
| 927 | ``plat/common/aarch64/platform_mp_stack.S`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 928 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 929 | Function : plat_get_my_stack() |
| 930 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 931 | |
| 932 | :: |
| 933 | |
| 934 | Argument : void |
| 935 | Return : uintptr_t |
| 936 | |
| 937 | This function returns the base address of the normal memory stack that |
| 938 | has been allocated for the current CPU. For BL images that only require a |
| 939 | stack for the primary CPU, the UP version of the function is used. The size |
| 940 | of the stack allocated to each CPU is specified by the platform defined |
| 941 | constant ``PLATFORM_STACK_SIZE``. |
| 942 | |
| 943 | Common implementations of this function for the UP and MP BL images are |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 944 | provided in ``plat/common/aarch64/platform_up_stack.S`` and |
| 945 | ``plat/common/aarch64/platform_mp_stack.S`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 946 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 947 | Function : plat_report_exception() |
| 948 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 949 | |
| 950 | :: |
| 951 | |
| 952 | Argument : unsigned int |
| 953 | Return : void |
| 954 | |
| 955 | A platform may need to report various information about its status when an |
| 956 | exception is taken, for example the current exception level, the CPU security |
| 957 | state (secure/non-secure), the exception type, and so on. This function is |
| 958 | called in the following circumstances: |
| 959 | |
| 960 | - In BL1, whenever an exception is taken. |
| 961 | - In BL2, whenever an exception is taken. |
| 962 | |
| 963 | The default implementation doesn't do anything, to avoid making assumptions |
| 964 | about the way the platform displays its status information. |
| 965 | |
| 966 | For AArch64, this function receives the exception type as its argument. |
| 967 | Possible values for exceptions types are listed in the |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 968 | ``include/common/bl_common.h`` header file. Note that these constants are not |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 969 | related to any architectural exception code; they are just a TF-A convention. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 970 | |
| 971 | For AArch32, this function receives the exception mode as its argument. |
| 972 | Possible values for exception modes are listed in the |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 973 | ``include/lib/aarch32/arch.h`` header file. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 974 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 975 | Function : plat_reset_handler() |
| 976 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 977 | |
| 978 | :: |
| 979 | |
| 980 | Argument : void |
| 981 | Return : void |
| 982 | |
| 983 | A platform may need to do additional initialization after reset. This function |
Paul Beesley | f2ec714 | 2019-10-04 16:17:46 +0000 | [diff] [blame] | 984 | allows the platform to do the platform specific initializations. Platform |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 985 | specific errata workarounds could also be implemented here. The API should |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 986 | preserve the values of callee saved registers x19 to x29. |
| 987 | |
| 988 | The default implementation doesn't do anything. If a platform needs to override |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 989 | the default implementation, refer to the :ref:`Firmware Design` for general |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 990 | guidelines. |
| 991 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 992 | Function : plat_disable_acp() |
| 993 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 994 | |
| 995 | :: |
| 996 | |
| 997 | Argument : void |
| 998 | Return : void |
| 999 | |
John Tsichritzis | 6dda976 | 2018-07-23 09:18:04 +0100 | [diff] [blame] | 1000 | This API allows a platform to disable the Accelerator Coherency Port (if |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1001 | present) during a cluster power down sequence. The default weak implementation |
John Tsichritzis | 6dda976 | 2018-07-23 09:18:04 +0100 | [diff] [blame] | 1002 | doesn't do anything. Since this API is called during the power down sequence, |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1003 | it has restrictions for stack usage and it can use the registers x0 - x17 as |
| 1004 | scratch registers. It should preserve the value in x18 register as it is used |
| 1005 | by the caller to store the return address. |
| 1006 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1007 | Function : plat_error_handler() |
| 1008 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1009 | |
| 1010 | :: |
| 1011 | |
| 1012 | Argument : int |
| 1013 | Return : void |
| 1014 | |
| 1015 | This API is called when the generic code encounters an error situation from |
| 1016 | which it cannot continue. It allows the platform to perform error reporting or |
| 1017 | recovery actions (for example, reset the system). This function must not return. |
| 1018 | |
| 1019 | The parameter indicates the type of error using standard codes from ``errno.h``. |
| 1020 | Possible errors reported by the generic code are: |
| 1021 | |
| 1022 | - ``-EAUTH``: a certificate or image could not be authenticated (when Trusted |
| 1023 | Board Boot is enabled) |
| 1024 | - ``-ENOENT``: the requested image or certificate could not be found or an IO |
| 1025 | error was detected |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1026 | - ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this |
| 1027 | error is usually an indication of an incorrect array size |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1028 | |
| 1029 | The default implementation simply spins. |
| 1030 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1031 | Function : plat_panic_handler() |
| 1032 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1033 | |
| 1034 | :: |
| 1035 | |
| 1036 | Argument : void |
| 1037 | Return : void |
| 1038 | |
| 1039 | This API is called when the generic code encounters an unexpected error |
| 1040 | situation from which it cannot recover. This function must not return, |
| 1041 | and must be implemented in assembly because it may be called before the C |
| 1042 | environment is initialized. |
| 1043 | |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 1044 | .. note:: |
| 1045 | The address from where it was called is stored in x30 (Link Register). |
| 1046 | The default implementation simply spins. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1047 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1048 | Function : plat_get_bl_image_load_info() |
| 1049 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1050 | |
| 1051 | :: |
| 1052 | |
| 1053 | Argument : void |
| 1054 | Return : bl_load_info_t * |
| 1055 | |
| 1056 | This function returns pointer to the list of images that the platform has |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1057 | populated to load. This function is invoked in BL2 to load the |
| 1058 | BL3xx images. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1059 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1060 | Function : plat_get_next_bl_params() |
| 1061 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1062 | |
| 1063 | :: |
| 1064 | |
| 1065 | Argument : void |
| 1066 | Return : bl_params_t * |
| 1067 | |
| 1068 | This function returns a pointer to the shared memory that the platform has |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1069 | kept aside to pass TF-A related information that next BL image needs. This |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1070 | function is invoked in BL2 to pass this information to the next BL |
| 1071 | image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1072 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1073 | Function : plat_get_stack_protector_canary() |
| 1074 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1075 | |
| 1076 | :: |
| 1077 | |
| 1078 | Argument : void |
| 1079 | Return : u_register_t |
| 1080 | |
| 1081 | This function returns a random value that is used to initialize the canary used |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1082 | when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1083 | value will weaken the protection as the attacker could easily write the right |
| 1084 | value as part of the attack most of the time. Therefore, it should return a |
| 1085 | true random number. |
| 1086 | |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 1087 | .. warning:: |
| 1088 | For the protection to be effective, the global data need to be placed at |
| 1089 | a lower address than the stack bases. Failure to do so would allow an |
| 1090 | attacker to overwrite the canary as part of the stack buffer overflow attack. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1091 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1092 | Function : plat_flush_next_bl_params() |
| 1093 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1094 | |
| 1095 | :: |
| 1096 | |
| 1097 | Argument : void |
| 1098 | Return : void |
| 1099 | |
| 1100 | This function flushes to main memory all the image params that are passed to |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1101 | next image. This function is invoked in BL2 to flush this information |
| 1102 | to the next BL image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1103 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1104 | Function : plat_log_get_prefix() |
| 1105 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Soby Mathew | aaf15f5 | 2017-09-04 11:49:29 +0100 | [diff] [blame] | 1106 | |
| 1107 | :: |
| 1108 | |
| 1109 | Argument : unsigned int |
| 1110 | Return : const char * |
| 1111 | |
| 1112 | This function defines the prefix string corresponding to the `log_level` to be |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1113 | prepended to all the log output from TF-A. The `log_level` (argument) will |
| 1114 | correspond to one of the standard log levels defined in debug.h. The platform |
| 1115 | can override the common implementation to define a different prefix string for |
John Tsichritzis | 30f8964 | 2018-06-07 16:31:34 +0100 | [diff] [blame] | 1116 | the log output. The implementation should be robust to future changes that |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1117 | increase the number of log levels. |
Soby Mathew | aaf15f5 | 2017-09-04 11:49:29 +0100 | [diff] [blame] | 1118 | |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1119 | Function : plat_get_soc_version() |
Manish V Badarkhe | 904f93a | 2020-03-26 14:20:27 +0000 | [diff] [blame] | 1120 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1121 | |
| 1122 | :: |
| 1123 | |
| 1124 | Argument : void |
| 1125 | Return : int32_t |
| 1126 | |
| 1127 | This function returns soc version which mainly consist of below fields |
| 1128 | |
| 1129 | :: |
| 1130 | |
| 1131 | soc_version[30:24] = JEP-106 continuation code for the SiP |
| 1132 | soc_version[23:16] = JEP-106 identification code with parity bit for the SiP |
| 1133 | |
| 1134 | Function : plat_get_soc_revision() |
Manish V Badarkhe | 904f93a | 2020-03-26 14:20:27 +0000 | [diff] [blame] | 1135 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1136 | |
| 1137 | :: |
| 1138 | |
| 1139 | Argument : void |
| 1140 | Return : int32_t |
| 1141 | |
| 1142 | This function returns soc revision in below format |
| 1143 | |
| 1144 | :: |
| 1145 | |
| 1146 | soc_revision[0:30] = SOC revision of specific SOC |
| 1147 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1148 | Modifications specific to a Boot Loader stage |
| 1149 | --------------------------------------------- |
| 1150 | |
| 1151 | Boot Loader Stage 1 (BL1) |
| 1152 | ------------------------- |
| 1153 | |
| 1154 | BL1 implements the reset vector where execution starts from after a cold or |
| 1155 | warm boot. For each CPU, BL1 is responsible for the following tasks: |
| 1156 | |
| 1157 | #. Handling the reset as described in section 2.2 |
| 1158 | |
| 1159 | #. In the case of a cold boot and the CPU being the primary CPU, ensuring that |
| 1160 | only this CPU executes the remaining BL1 code, including loading and passing |
| 1161 | control to the BL2 stage. |
| 1162 | |
| 1163 | #. Identifying and starting the Firmware Update process (if required). |
| 1164 | |
| 1165 | #. Loading the BL2 image from non-volatile storage into secure memory at the |
| 1166 | address specified by the platform defined constant ``BL2_BASE``. |
| 1167 | |
| 1168 | #. Populating a ``meminfo`` structure with the following information in memory, |
| 1169 | accessible by BL2 immediately upon entry. |
| 1170 | |
| 1171 | :: |
| 1172 | |
| 1173 | meminfo.total_base = Base address of secure RAM visible to BL2 |
| 1174 | meminfo.total_size = Size of secure RAM visible to BL2 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1175 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1176 | By default, BL1 places this ``meminfo`` structure at the end of secure |
| 1177 | memory visible to BL2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1178 | |
Soby Mathew | b1bf044 | 2018-02-16 14:52:52 +0000 | [diff] [blame] | 1179 | It is possible for the platform to decide where it wants to place the |
| 1180 | ``meminfo`` structure for BL2 or restrict the amount of memory visible to |
| 1181 | BL2 by overriding the weak default implementation of |
| 1182 | ``bl1_plat_handle_post_image_load`` API. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1183 | |
| 1184 | The following functions need to be implemented by the platform port to enable |
| 1185 | BL1 to perform the above tasks. |
| 1186 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1187 | Function : bl1_early_platform_setup() [mandatory] |
| 1188 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1189 | |
| 1190 | :: |
| 1191 | |
| 1192 | Argument : void |
| 1193 | Return : void |
| 1194 | |
| 1195 | This function executes with the MMU and data caches disabled. It is only called |
| 1196 | by the primary CPU. |
| 1197 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1198 | On Arm standard platforms, this function: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1199 | |
| 1200 | - Enables a secure instance of SP805 to act as the Trusted Watchdog. |
| 1201 | |
| 1202 | - Initializes a UART (PL011 console), which enables access to the ``printf`` |
| 1203 | family of functions in BL1. |
| 1204 | |
| 1205 | - Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to |
| 1206 | the CCI slave interface corresponding to the cluster that includes the |
| 1207 | primary CPU. |
| 1208 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1209 | Function : bl1_plat_arch_setup() [mandatory] |
| 1210 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1211 | |
| 1212 | :: |
| 1213 | |
| 1214 | Argument : void |
| 1215 | Return : void |
| 1216 | |
| 1217 | This function performs any platform-specific and architectural setup that the |
| 1218 | platform requires. Platform-specific setup might include configuration of |
| 1219 | memory controllers and the interconnect. |
| 1220 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1221 | In Arm standard platforms, this function enables the MMU. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1222 | |
| 1223 | This function helps fulfill requirement 2 above. |
| 1224 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1225 | Function : bl1_platform_setup() [mandatory] |
| 1226 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1227 | |
| 1228 | :: |
| 1229 | |
| 1230 | Argument : void |
| 1231 | Return : void |
| 1232 | |
| 1233 | This function executes with the MMU and data caches enabled. It is responsible |
| 1234 | for performing any remaining platform-specific setup that can occur after the |
| 1235 | MMU and data cache have been enabled. |
| 1236 | |
Roberto Vargas | 0cd866c | 2017-12-12 10:39:44 +0000 | [diff] [blame] | 1237 | if support for multiple boot sources is required, it initializes the boot |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1238 | sequence used by plat_try_next_boot_source(). |
Roberto Vargas | 0cd866c | 2017-12-12 10:39:44 +0000 | [diff] [blame] | 1239 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1240 | In Arm standard platforms, this function initializes the storage abstraction |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1241 | layer used to load the next bootloader image. |
| 1242 | |
| 1243 | This function helps fulfill requirement 4 above. |
| 1244 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1245 | Function : bl1_plat_sec_mem_layout() [mandatory] |
| 1246 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1247 | |
| 1248 | :: |
| 1249 | |
| 1250 | Argument : void |
| 1251 | Return : meminfo * |
| 1252 | |
| 1253 | This function should only be called on the cold boot path. It executes with the |
| 1254 | MMU and data caches enabled. The pointer returned by this function must point to |
| 1255 | a ``meminfo`` structure containing the extents and availability of secure RAM for |
| 1256 | the BL1 stage. |
| 1257 | |
| 1258 | :: |
| 1259 | |
| 1260 | meminfo.total_base = Base address of secure RAM visible to BL1 |
| 1261 | meminfo.total_size = Size of secure RAM visible to BL1 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1262 | |
| 1263 | This information is used by BL1 to load the BL2 image in secure RAM. BL1 also |
| 1264 | populates a similar structure to tell BL2 the extents of memory available for |
| 1265 | its own use. |
| 1266 | |
| 1267 | This function helps fulfill requirements 4 and 5 above. |
| 1268 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1269 | Function : bl1_plat_prepare_exit() [optional] |
| 1270 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1271 | |
| 1272 | :: |
| 1273 | |
| 1274 | Argument : entry_point_info_t * |
| 1275 | Return : void |
| 1276 | |
| 1277 | This function is called prior to exiting BL1 in response to the |
| 1278 | ``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform |
| 1279 | platform specific clean up or bookkeeping operations before transferring |
| 1280 | control to the next image. It receives the address of the ``entry_point_info_t`` |
| 1281 | structure passed from BL2. This function runs with MMU disabled. |
| 1282 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1283 | Function : bl1_plat_set_ep_info() [optional] |
| 1284 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1285 | |
| 1286 | :: |
| 1287 | |
| 1288 | Argument : unsigned int image_id, entry_point_info_t *ep_info |
| 1289 | Return : void |
| 1290 | |
| 1291 | This function allows platforms to override ``ep_info`` for the given ``image_id``. |
| 1292 | |
| 1293 | The default implementation just returns. |
| 1294 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1295 | Function : bl1_plat_get_next_image_id() [optional] |
| 1296 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1297 | |
| 1298 | :: |
| 1299 | |
| 1300 | Argument : void |
| 1301 | Return : unsigned int |
| 1302 | |
| 1303 | This and the following function must be overridden to enable the FWU feature. |
| 1304 | |
| 1305 | BL1 calls this function after platform setup to identify the next image to be |
| 1306 | loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds |
| 1307 | with the normal boot sequence, which loads and executes BL2. If the platform |
| 1308 | returns a different image id, BL1 assumes that Firmware Update is required. |
| 1309 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1310 | The default implementation always returns ``BL2_IMAGE_ID``. The Arm development |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1311 | platforms override this function to detect if firmware update is required, and |
| 1312 | if so, return the first image in the firmware update process. |
| 1313 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1314 | Function : bl1_plat_get_image_desc() [optional] |
| 1315 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1316 | |
| 1317 | :: |
| 1318 | |
| 1319 | Argument : unsigned int image_id |
| 1320 | Return : image_desc_t * |
| 1321 | |
| 1322 | BL1 calls this function to get the image descriptor information ``image_desc_t`` |
| 1323 | for the provided ``image_id`` from the platform. |
| 1324 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1325 | The default implementation always returns a common BL2 image descriptor. Arm |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1326 | standard platforms return an image descriptor corresponding to BL2 or one of |
| 1327 | the firmware update images defined in the Trusted Board Boot Requirements |
| 1328 | specification. |
| 1329 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1330 | Function : bl1_plat_handle_pre_image_load() [optional] |
| 1331 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1332 | |
| 1333 | :: |
| 1334 | |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1335 | Argument : unsigned int image_id |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1336 | Return : int |
| 1337 | |
| 1338 | This function can be used by the platforms to update/use image information |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1339 | corresponding to ``image_id``. This function is invoked in BL1, both in cold |
| 1340 | boot and FWU code path, before loading the image. |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1341 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1342 | Function : bl1_plat_handle_post_image_load() [optional] |
| 1343 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1344 | |
| 1345 | :: |
| 1346 | |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1347 | Argument : unsigned int image_id |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1348 | Return : int |
| 1349 | |
| 1350 | This function can be used by the platforms to update/use image information |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1351 | corresponding to ``image_id``. This function is invoked in BL1, both in cold |
| 1352 | boot and FWU code path, after loading and authenticating the image. |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1353 | |
Soby Mathew | b1bf044 | 2018-02-16 14:52:52 +0000 | [diff] [blame] | 1354 | The default weak implementation of this function calculates the amount of |
| 1355 | Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` |
| 1356 | structure at the beginning of this free memory and populates it. The address |
| 1357 | of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint |
| 1358 | information to BL2. |
| 1359 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1360 | Function : bl1_plat_fwu_done() [optional] |
| 1361 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1362 | |
| 1363 | :: |
| 1364 | |
| 1365 | Argument : unsigned int image_id, uintptr_t image_src, |
| 1366 | unsigned int image_size |
| 1367 | Return : void |
| 1368 | |
| 1369 | BL1 calls this function when the FWU process is complete. It must not return. |
| 1370 | The platform may override this function to take platform specific action, for |
| 1371 | example to initiate the normal boot flow. |
| 1372 | |
| 1373 | The default implementation spins forever. |
| 1374 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1375 | Function : bl1_plat_mem_check() [mandatory] |
| 1376 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1377 | |
| 1378 | :: |
| 1379 | |
| 1380 | Argument : uintptr_t mem_base, unsigned int mem_size, |
| 1381 | unsigned int flags |
| 1382 | Return : int |
| 1383 | |
| 1384 | BL1 calls this function while handling FWU related SMCs, more specifically when |
| 1385 | copying or authenticating an image. Its responsibility is to ensure that the |
| 1386 | region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and |
| 1387 | that this memory corresponds to either a secure or non-secure memory region as |
| 1388 | indicated by the security state of the ``flags`` argument. |
| 1389 | |
| 1390 | This function can safely assume that the value resulting from the addition of |
| 1391 | ``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not |
| 1392 | overflow. |
| 1393 | |
| 1394 | This function must return 0 on success, a non-null error code otherwise. |
| 1395 | |
| 1396 | The default implementation of this function asserts therefore platforms must |
| 1397 | override it when using the FWU feature. |
| 1398 | |
| 1399 | Boot Loader Stage 2 (BL2) |
| 1400 | ------------------------- |
| 1401 | |
| 1402 | The BL2 stage is executed only by the primary CPU, which is determined in BL1 |
| 1403 | using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1404 | ``BL2_BASE``. BL2 executes in Secure EL1 and and invokes |
| 1405 | ``plat_get_bl_image_load_info()`` to retrieve the list of images to load from |
| 1406 | non-volatile storage to secure/non-secure RAM. After all the images are loaded |
| 1407 | then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable |
| 1408 | images to be passed to the next BL image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1409 | |
| 1410 | The following functions must be implemented by the platform port to enable BL2 |
| 1411 | to perform the above tasks. |
| 1412 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1413 | Function : bl2_early_platform_setup2() [mandatory] |
| 1414 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1415 | |
| 1416 | :: |
| 1417 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1418 | Argument : u_register_t, u_register_t, u_register_t, u_register_t |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1419 | Return : void |
| 1420 | |
| 1421 | This function executes with the MMU and data caches disabled. It is only called |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1422 | by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments |
| 1423 | are platform specific. |
| 1424 | |
| 1425 | On Arm standard platforms, the arguments received are : |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1426 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1427 | arg0 - Points to load address of HW_CONFIG if present |
| 1428 | |
| 1429 | arg1 - ``meminfo`` structure populated by BL1. The platform copies |
| 1430 | the contents of ``meminfo`` as it may be subsequently overwritten by BL2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1431 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1432 | On Arm standard platforms, this function also: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1433 | |
| 1434 | - Initializes a UART (PL011 console), which enables access to the ``printf`` |
| 1435 | family of functions in BL2. |
| 1436 | |
| 1437 | - Initializes the storage abstraction layer used to load further bootloader |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1438 | images. It is necessary to do this early on platforms with a SCP_BL2 image, |
| 1439 | since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1440 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1441 | Function : bl2_plat_arch_setup() [mandatory] |
| 1442 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1443 | |
| 1444 | :: |
| 1445 | |
| 1446 | Argument : void |
| 1447 | Return : void |
| 1448 | |
| 1449 | This function executes with the MMU and data caches disabled. It is only called |
| 1450 | by the primary CPU. |
| 1451 | |
| 1452 | The purpose of this function is to perform any architectural initialization |
| 1453 | that varies across platforms. |
| 1454 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1455 | On Arm standard platforms, this function enables the MMU. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1456 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1457 | Function : bl2_platform_setup() [mandatory] |
| 1458 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1459 | |
| 1460 | :: |
| 1461 | |
| 1462 | Argument : void |
| 1463 | Return : void |
| 1464 | |
| 1465 | This function may execute with the MMU and data caches enabled if the platform |
| 1466 | port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only |
| 1467 | called by the primary CPU. |
| 1468 | |
| 1469 | The purpose of this function is to perform any platform initialization |
| 1470 | specific to BL2. |
| 1471 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1472 | In Arm standard platforms, this function performs security setup, including |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1473 | configuration of the TrustZone controller to allow non-secure masters access |
| 1474 | to most of DRAM. Part of DRAM is reserved for secure world use. |
| 1475 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1476 | Function : bl2_plat_handle_pre_image_load() [optional] |
| 1477 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1478 | |
| 1479 | :: |
| 1480 | |
| 1481 | Argument : unsigned int |
| 1482 | Return : int |
| 1483 | |
| 1484 | This function can be used by the platforms to update/use image information |
Masahiro Yamada | 02a0d3d | 2018-02-01 16:45:51 +0900 | [diff] [blame] | 1485 | for given ``image_id``. This function is currently invoked in BL2 before |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1486 | loading each image. |
Masahiro Yamada | 02a0d3d | 2018-02-01 16:45:51 +0900 | [diff] [blame] | 1487 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1488 | Function : bl2_plat_handle_post_image_load() [optional] |
| 1489 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Masahiro Yamada | 02a0d3d | 2018-02-01 16:45:51 +0900 | [diff] [blame] | 1490 | |
| 1491 | :: |
| 1492 | |
| 1493 | Argument : unsigned int |
| 1494 | Return : int |
| 1495 | |
| 1496 | This function can be used by the platforms to update/use image information |
| 1497 | for given ``image_id``. This function is currently invoked in BL2 after |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1498 | loading each image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1499 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1500 | Function : bl2_plat_preload_setup [optional] |
| 1501 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1502 | |
| 1503 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1504 | |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1505 | Argument : void |
| 1506 | Return : void |
| 1507 | |
| 1508 | This optional function performs any BL2 platform initialization |
| 1509 | required before image loading, that is not done later in |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1510 | bl2_platform_setup(). Specifically, if support for multiple |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1511 | boot sources is required, it initializes the boot sequence used by |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1512 | plat_try_next_boot_source(). |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1513 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1514 | Function : plat_try_next_boot_source() [optional] |
| 1515 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1516 | |
| 1517 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1518 | |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1519 | Argument : void |
| 1520 | Return : int |
| 1521 | |
| 1522 | This optional function passes to the next boot source in the redundancy |
| 1523 | sequence. |
| 1524 | |
| 1525 | This function moves the current boot redundancy source to the next |
| 1526 | element in the boot sequence. If there are no more boot sources then it |
| 1527 | must return 0, otherwise it must return 1. The default implementation |
| 1528 | of this always returns 0. |
| 1529 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1530 | Boot Loader Stage 2 (BL2) at EL3 |
| 1531 | -------------------------------- |
| 1532 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1533 | When the platform has a non-TF-A Boot ROM it is desirable to jump |
| 1534 | directly to BL2 instead of TF-A BL1. In this case BL2 is expected to |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1535 | execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` |
| 1536 | document for more information. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1537 | |
| 1538 | All mandatory functions of BL2 must be implemented, except the functions |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1539 | bl2_early_platform_setup and bl2_el3_plat_arch_setup, because |
| 1540 | their work is done now by bl2_el3_early_platform_setup and |
| 1541 | bl2_el3_plat_arch_setup. These functions should generally implement |
| 1542 | the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1543 | |
| 1544 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1545 | Function : bl2_el3_early_platform_setup() [mandatory] |
| 1546 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1547 | |
| 1548 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1549 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1550 | Argument : u_register_t, u_register_t, u_register_t, u_register_t |
| 1551 | Return : void |
| 1552 | |
| 1553 | This function executes with the MMU and data caches disabled. It is only called |
| 1554 | by the primary CPU. This function receives four parameters which can be used |
| 1555 | by the platform to pass any needed information from the Boot ROM to BL2. |
| 1556 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1557 | On Arm standard platforms, this function does the following: |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1558 | |
| 1559 | - Initializes a UART (PL011 console), which enables access to the ``printf`` |
| 1560 | family of functions in BL2. |
| 1561 | |
| 1562 | - Initializes the storage abstraction layer used to load further bootloader |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1563 | images. It is necessary to do this early on platforms with a SCP_BL2 image, |
| 1564 | since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1565 | |
| 1566 | - Initializes the private variables that define the memory layout used. |
| 1567 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1568 | Function : bl2_el3_plat_arch_setup() [mandatory] |
| 1569 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1570 | |
| 1571 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1572 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1573 | Argument : void |
| 1574 | Return : void |
| 1575 | |
| 1576 | This function executes with the MMU and data caches disabled. It is only called |
| 1577 | by the primary CPU. |
| 1578 | |
| 1579 | The purpose of this function is to perform any architectural initialization |
| 1580 | that varies across platforms. |
| 1581 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1582 | On Arm standard platforms, this function enables the MMU. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1583 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1584 | Function : bl2_el3_plat_prepare_exit() [optional] |
| 1585 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1586 | |
| 1587 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1588 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1589 | Argument : void |
| 1590 | Return : void |
| 1591 | |
| 1592 | This function is called prior to exiting BL2 and run the next image. |
| 1593 | It should be used to perform platform specific clean up or bookkeeping |
| 1594 | operations before transferring control to the next image. This function |
| 1595 | runs with MMU disabled. |
| 1596 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1597 | FWU Boot Loader Stage 2 (BL2U) |
| 1598 | ------------------------------ |
| 1599 | |
| 1600 | The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU |
| 1601 | process and is executed only by the primary CPU. BL1 passes control to BL2U at |
| 1602 | ``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: |
| 1603 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1604 | #. (Optional) Transferring the optional SCP_BL2U binary image from AP secure |
| 1605 | memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. |
| 1606 | ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U |
| 1607 | should be copied from. Subsequent handling of the SCP_BL2U image is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1608 | implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. |
| 1609 | If ``SCP_BL2U_BASE`` is not defined then this step is not performed. |
| 1610 | |
| 1611 | #. Any platform specific setup required to perform the FWU process. For |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1612 | example, Arm standard platforms initialize the TZC controller so that the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1613 | normal world can access DDR memory. |
| 1614 | |
| 1615 | The following functions must be implemented by the platform port to enable |
| 1616 | BL2U to perform the tasks mentioned above. |
| 1617 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1618 | Function : bl2u_early_platform_setup() [mandatory] |
| 1619 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1620 | |
| 1621 | :: |
| 1622 | |
| 1623 | Argument : meminfo *mem_info, void *plat_info |
| 1624 | Return : void |
| 1625 | |
| 1626 | This function executes with the MMU and data caches disabled. It is only |
| 1627 | called by the primary CPU. The arguments to this function is the address |
| 1628 | of the ``meminfo`` structure and platform specific info provided by BL1. |
| 1629 | |
| 1630 | The platform may copy the contents of the ``mem_info`` and ``plat_info`` into |
| 1631 | private storage as the original memory may be subsequently overwritten by BL2U. |
| 1632 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1633 | On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1634 | to extract SCP_BL2U image information, which is then copied into a private |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1635 | variable. |
| 1636 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1637 | Function : bl2u_plat_arch_setup() [mandatory] |
| 1638 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1639 | |
| 1640 | :: |
| 1641 | |
| 1642 | Argument : void |
| 1643 | Return : void |
| 1644 | |
| 1645 | This function executes with the MMU and data caches disabled. It is only |
| 1646 | called by the primary CPU. |
| 1647 | |
| 1648 | The purpose of this function is to perform any architectural initialization |
| 1649 | that varies across platforms, for example enabling the MMU (since the memory |
| 1650 | map differs across platforms). |
| 1651 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1652 | Function : bl2u_platform_setup() [mandatory] |
| 1653 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1654 | |
| 1655 | :: |
| 1656 | |
| 1657 | Argument : void |
| 1658 | Return : void |
| 1659 | |
| 1660 | This function may execute with the MMU and data caches enabled if the platform |
| 1661 | port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only |
| 1662 | called by the primary CPU. |
| 1663 | |
| 1664 | The purpose of this function is to perform any platform initialization |
| 1665 | specific to BL2U. |
| 1666 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1667 | In Arm standard platforms, this function performs security setup, including |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1668 | configuration of the TrustZone controller to allow non-secure masters access |
| 1669 | to most of DRAM. Part of DRAM is reserved for secure world use. |
| 1670 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1671 | Function : bl2u_plat_handle_scp_bl2u() [optional] |
| 1672 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1673 | |
| 1674 | :: |
| 1675 | |
| 1676 | Argument : void |
| 1677 | Return : int |
| 1678 | |
| 1679 | This function is used to perform any platform-specific actions required to |
| 1680 | handle the SCP firmware. Typically it transfers the image into SCP memory using |
| 1681 | a platform-specific protocol and waits until SCP executes it and signals to the |
| 1682 | Application Processor (AP) for BL2U execution to continue. |
| 1683 | |
| 1684 | This function returns 0 on success, a negative error code otherwise. |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1685 | This function is included if SCP_BL2U_BASE is defined. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1686 | |
| 1687 | Boot Loader Stage 3-1 (BL31) |
| 1688 | ---------------------------- |
| 1689 | |
| 1690 | During cold boot, the BL31 stage is executed only by the primary CPU. This is |
| 1691 | determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes |
| 1692 | control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all |
| 1693 | CPUs. BL31 executes at EL3 and is responsible for: |
| 1694 | |
| 1695 | #. Re-initializing all architectural and platform state. Although BL1 performs |
| 1696 | some of this initialization, BL31 remains resident in EL3 and must ensure |
| 1697 | that EL3 architectural and platform state is completely initialized. It |
| 1698 | should make no assumptions about the system state when it receives control. |
| 1699 | |
| 1700 | #. Passing control to a normal world BL image, pre-loaded at a platform- |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1701 | specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list |
| 1702 | populated by BL2 in memory to do this. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1703 | |
| 1704 | #. Providing runtime firmware services. Currently, BL31 only implements a |
| 1705 | subset of the Power State Coordination Interface (PSCI) API as a runtime |
| 1706 | service. See Section 3.3 below for details of porting the PSCI |
| 1707 | implementation. |
| 1708 | |
| 1709 | #. Optionally passing control to the BL32 image, pre-loaded at a platform- |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 1710 | specific address by BL2. BL31 exports a set of APIs that allow runtime |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1711 | services to specify the security state in which the next image should be |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1712 | executed and run the corresponding image. On ARM platforms, BL31 uses the |
| 1713 | ``bl_params`` list populated by BL2 in memory to do this. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1714 | |
| 1715 | If BL31 is a reset vector, It also needs to handle the reset as specified in |
| 1716 | section 2.2 before the tasks described above. |
| 1717 | |
| 1718 | The following functions must be implemented by the platform port to enable BL31 |
| 1719 | to perform the above tasks. |
| 1720 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1721 | Function : bl31_early_platform_setup2() [mandatory] |
| 1722 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1723 | |
| 1724 | :: |
| 1725 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1726 | Argument : u_register_t, u_register_t, u_register_t, u_register_t |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1727 | Return : void |
| 1728 | |
| 1729 | This function executes with the MMU and data caches disabled. It is only called |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1730 | by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are |
| 1731 | platform specific. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1732 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1733 | In Arm standard platforms, the arguments received are : |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1734 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1735 | arg0 - The pointer to the head of `bl_params_t` list |
| 1736 | which is list of executable images following BL31, |
| 1737 | |
| 1738 | arg1 - Points to load address of SOC_FW_CONFIG if present |
| 1739 | |
| 1740 | arg2 - Points to load address of HW_CONFIG if present |
| 1741 | |
| 1742 | arg3 - A special value to verify platform parameters from BL2 to BL31. Not |
| 1743 | used in release builds. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1744 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1745 | The function runs through the `bl_param_t` list and extracts the entry point |
| 1746 | information for BL32 and BL33. It also performs the following: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1747 | |
| 1748 | - Initialize a UART (PL011 console), which enables access to the ``printf`` |
| 1749 | family of functions in BL31. |
| 1750 | |
| 1751 | - Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the |
| 1752 | CCI slave interface corresponding to the cluster that includes the primary |
| 1753 | CPU. |
| 1754 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1755 | Function : bl31_plat_arch_setup() [mandatory] |
| 1756 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1757 | |
| 1758 | :: |
| 1759 | |
| 1760 | Argument : void |
| 1761 | Return : void |
| 1762 | |
| 1763 | This function executes with the MMU and data caches disabled. It is only called |
| 1764 | by the primary CPU. |
| 1765 | |
| 1766 | The purpose of this function is to perform any architectural initialization |
| 1767 | that varies across platforms. |
| 1768 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1769 | On Arm standard platforms, this function enables the MMU. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1770 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1771 | Function : bl31_platform_setup() [mandatory] |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1772 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1773 | |
| 1774 | :: |
| 1775 | |
| 1776 | Argument : void |
| 1777 | Return : void |
| 1778 | |
| 1779 | This function may execute with the MMU and data caches enabled if the platform |
| 1780 | port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only |
| 1781 | called by the primary CPU. |
| 1782 | |
| 1783 | The purpose of this function is to complete platform initialization so that both |
| 1784 | BL31 runtime services and normal world software can function correctly. |
| 1785 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1786 | On Arm standard platforms, this function does the following: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1787 | |
| 1788 | - Initialize the generic interrupt controller. |
| 1789 | |
| 1790 | Depending on the GIC driver selected by the platform, the appropriate GICv2 |
| 1791 | or GICv3 initialization will be done, which mainly consists of: |
| 1792 | |
| 1793 | - Enable secure interrupts in the GIC CPU interface. |
| 1794 | - Disable the legacy interrupt bypass mechanism. |
| 1795 | - Configure the priority mask register to allow interrupts of all priorities |
| 1796 | to be signaled to the CPU interface. |
| 1797 | - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. |
| 1798 | - Target all secure SPIs to CPU0. |
| 1799 | - Enable these secure interrupts in the GIC distributor. |
| 1800 | - Configure all other interrupts as non-secure. |
| 1801 | - Enable signaling of secure interrupts in the GIC distributor. |
| 1802 | |
| 1803 | - Enable system-level implementation of the generic timer counter through the |
| 1804 | memory mapped interface. |
| 1805 | |
| 1806 | - Grant access to the system counter timer module |
| 1807 | |
| 1808 | - Initialize the power controller device. |
| 1809 | |
| 1810 | In particular, initialise the locks that prevent concurrent accesses to the |
| 1811 | power controller device. |
| 1812 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1813 | Function : bl31_plat_runtime_setup() [optional] |
| 1814 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1815 | |
| 1816 | :: |
| 1817 | |
| 1818 | Argument : void |
| 1819 | Return : void |
| 1820 | |
| 1821 | The purpose of this function is allow the platform to perform any BL31 runtime |
| 1822 | setup just prior to BL31 exit during cold boot. The default weak |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 1823 | implementation of this function will invoke ``console_switch_state()`` to switch |
| 1824 | console output to consoles marked for use in the ``runtime`` state. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1825 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1826 | Function : bl31_plat_get_next_image_ep_info() [mandatory] |
| 1827 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1828 | |
| 1829 | :: |
| 1830 | |
Sandrine Bailleux | 842117d | 2018-05-14 14:25:47 +0200 | [diff] [blame] | 1831 | Argument : uint32_t |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1832 | Return : entry_point_info * |
| 1833 | |
| 1834 | This function may execute with the MMU and data caches enabled if the platform |
| 1835 | port does the necessary initializations in ``bl31_plat_arch_setup()``. |
| 1836 | |
| 1837 | This function is called by ``bl31_main()`` to retrieve information provided by |
| 1838 | BL2 for the next image in the security state specified by the argument. BL31 |
| 1839 | uses this information to pass control to that image in the specified security |
| 1840 | state. This function must return a pointer to the ``entry_point_info`` structure |
| 1841 | (that was copied during ``bl31_early_platform_setup()``) if the image exists. It |
| 1842 | should return NULL otherwise. |
| 1843 | |
Jeenu Viswambharan | e834ee1 | 2018-04-27 15:17:03 +0100 | [diff] [blame] | 1844 | Function : bl31_plat_enable_mmu [optional] |
| 1845 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1846 | |
| 1847 | :: |
| 1848 | |
| 1849 | Argument : uint32_t |
| 1850 | Return : void |
| 1851 | |
| 1852 | This function enables the MMU. The boot code calls this function with MMU and |
| 1853 | caches disabled. This function should program necessary registers to enable |
| 1854 | translation, and upon return, the MMU on the calling PE must be enabled. |
| 1855 | |
| 1856 | The function must honor flags passed in the first argument. These flags are |
| 1857 | defined by the translation library, and can be found in the file |
| 1858 | ``include/lib/xlat_tables/xlat_mmu_helpers.h``. |
| 1859 | |
| 1860 | On DynamIQ systems, this function must not use stack while enabling MMU, which |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 1861 | is how the function in xlat table library version 2 is implemented. |
Jeenu Viswambharan | e834ee1 | 2018-04-27 15:17:03 +0100 | [diff] [blame] | 1862 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 1863 | Function : plat_init_apkey [optional] |
| 1864 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 1865 | |
| 1866 | :: |
| 1867 | |
| 1868 | Argument : void |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 1869 | Return : uint128_t |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 1870 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 1871 | This function returns the 128-bit value which can be used to program ARMv8.3 |
| 1872 | pointer authentication keys. |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 1873 | |
| 1874 | The value should be obtained from a reliable source of randomness. |
| 1875 | |
| 1876 | This function is only needed if ARMv8.3 pointer authentication is used in the |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 1877 | Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 1878 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1879 | Function : plat_get_syscnt_freq2() [mandatory] |
| 1880 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1881 | |
| 1882 | :: |
| 1883 | |
| 1884 | Argument : void |
| 1885 | Return : unsigned int |
| 1886 | |
| 1887 | This function is used by the architecture setup code to retrieve the counter |
| 1888 | frequency for the CPU's generic timer. This value will be programmed into the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1889 | ``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1890 | of the system counter, which is retrieved from the first entry in the frequency |
| 1891 | modes table. |
| 1892 | |
johpow01 | 3e24c16 | 2020-04-22 14:05:13 -0500 | [diff] [blame] | 1893 | Function : plat_arm_set_twedel_scr_el3() [optional] |
| 1894 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1895 | |
| 1896 | :: |
| 1897 | |
| 1898 | Argument : void |
| 1899 | Return : uint32_t |
| 1900 | |
| 1901 | This function is used in v8.6+ systems to set the WFE trap delay value in |
| 1902 | SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this |
| 1903 | feature is not enabled. The only hook provided is to set the TWED fields in |
| 1904 | SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust |
| 1905 | the WFE trap delays in lower ELs and these fields should be set by the |
| 1906 | appropriate EL2 or EL1 code depending on the platform configuration. |
| 1907 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1908 | #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] |
| 1909 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1910 | |
| 1911 | When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in |
| 1912 | bytes) aligned to the cache line boundary that should be allocated per-cpu to |
| 1913 | accommodate all the bakery locks. |
| 1914 | |
| 1915 | If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker |
| 1916 | calculates the size of the ``bakery_lock`` input section, aligns it to the |
| 1917 | nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` |
| 1918 | and stores the result in a linker symbol. This constant prevents a platform |
| 1919 | from relying on the linker and provide a more efficient mechanism for |
| 1920 | accessing per-cpu bakery lock information. |
| 1921 | |
| 1922 | If this constant is defined and its value is not equal to the value |
| 1923 | calculated by the linker then a link time assertion is raised. A compile time |
| 1924 | assertion is raised if the value of the constant is not aligned to the cache |
| 1925 | line boundary. |
| 1926 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1927 | .. _porting_guide_sdei_requirements: |
| 1928 | |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1929 | SDEI porting requirements |
| 1930 | ~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1931 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1932 | The |SDEI| dispatcher requires the platform to provide the following macros |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1933 | and functions, of which some are optional, and some others mandatory. |
| 1934 | |
| 1935 | Macros |
| 1936 | ...... |
| 1937 | |
| 1938 | Macro: PLAT_SDEI_NORMAL_PRI [mandatory] |
| 1939 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1940 | |
| 1941 | This macro must be defined to the EL3 exception priority level associated with |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1942 | Normal |SDEI| events on the platform. This must have a higher value |
| 1943 | (therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1944 | |
| 1945 | Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] |
| 1946 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1947 | |
| 1948 | This macro must be defined to the EL3 exception priority level associated with |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1949 | Critical |SDEI| events on the platform. This must have a lower value |
| 1950 | (therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1951 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1952 | **Note**: |SDEI| exception priorities must be the lowest among Secure |
| 1953 | priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must |
| 1954 | be higher than Normal |SDEI| priority. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1955 | |
| 1956 | Functions |
| 1957 | ......... |
| 1958 | |
| 1959 | Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] |
| 1960 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1961 | |
| 1962 | :: |
| 1963 | |
| 1964 | Argument: uintptr_t |
| 1965 | Return: int |
| 1966 | |
| 1967 | This function validates the address of client entry points provided for both |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1968 | event registration and *Complete and Resume* |SDEI| calls. The function |
| 1969 | takes one argument, which is the address of the handler the |SDEI| client |
| 1970 | requested to register. The function must return ``0`` for successful validation, |
| 1971 | or ``-1`` upon failure. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1972 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1973 | The default implementation always returns ``0``. On Arm platforms, this function |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1974 | is implemented to translate the entry point to physical address, and further to |
| 1975 | ensure that the address is located in Non-secure DRAM. |
| 1976 | |
| 1977 | Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] |
| 1978 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1979 | |
| 1980 | :: |
| 1981 | |
| 1982 | Argument: uint64_t |
| 1983 | Argument: unsigned int |
| 1984 | Return: void |
| 1985 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1986 | |SDEI| specification requires that a PE comes out of reset with the events |
| 1987 | masked. The client therefore is expected to call ``PE_UNMASK`` to unmask |
| 1988 | |SDEI| events on the PE. No |SDEI| events can be dispatched until such |
| 1989 | time. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1990 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 1991 | Should a PE receive an interrupt that was bound to an |SDEI| event while the |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 1992 | events are masked on the PE, the dispatcher implementation invokes the function |
| 1993 | ``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the |
| 1994 | interrupt and the interrupt ID are passed as parameters. |
| 1995 | |
| 1996 | The default implementation only prints out a warning message. |
| 1997 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1998 | Power State Coordination Interface (in BL31) |
| 1999 | -------------------------------------------- |
| 2000 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2001 | The TF-A implementation of the PSCI API is based around the concept of a |
| 2002 | *power domain*. A *power domain* is a CPU or a logical group of CPUs which |
| 2003 | share some state on which power management operations can be performed as |
| 2004 | specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is |
| 2005 | a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The |
| 2006 | *power domains* are arranged in a hierarchical tree structure and each |
| 2007 | *power domain* can be identified in a system by the cpu index of any CPU that |
| 2008 | is part of that domain and a *power domain level*. A processing element (for |
| 2009 | example, a CPU) is at level 0. If the *power domain* node above a CPU is a |
| 2010 | logical grouping of CPUs that share some state, then level 1 is that group of |
| 2011 | CPUs (for example, a cluster), and level 2 is a group of clusters (for |
| 2012 | example, the system). More details on the power domain topology and its |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2013 | organization can be found in :ref:`PSCI Power Domain Tree Structure`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2014 | |
| 2015 | BL31's platform initialization code exports a pointer to the platform-specific |
| 2016 | power management operations required for the PSCI implementation to function |
| 2017 | correctly. This information is populated in the ``plat_psci_ops`` structure. The |
| 2018 | PSCI implementation calls members of the ``plat_psci_ops`` structure for performing |
| 2019 | power management operations on the power domains. For example, the target |
| 2020 | CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` |
| 2021 | handler (if present) is called for the CPU power domain. |
| 2022 | |
| 2023 | The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to |
| 2024 | describe composite power states specific to a platform. The PSCI implementation |
Antonio Nino Diaz | 56b68ad | 2019-02-28 13:35:21 +0000 | [diff] [blame] | 2025 | defines a generic representation of the power-state parameter, which is an |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2026 | array of local power states where each index corresponds to a power domain |
| 2027 | level. Each entry contains the local power state the power domain at that power |
| 2028 | level could enter. It depends on the ``validate_power_state()`` handler to |
| 2029 | convert the power-state parameter (possibly encoding a composite power state) |
| 2030 | passed in a PSCI ``CPU_SUSPEND`` call to this representation. |
| 2031 | |
| 2032 | The following functions form part of platform port of PSCI functionality. |
| 2033 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2034 | Function : plat_psci_stat_accounting_start() [optional] |
| 2035 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2036 | |
| 2037 | :: |
| 2038 | |
| 2039 | Argument : const psci_power_state_t * |
| 2040 | Return : void |
| 2041 | |
| 2042 | This is an optional hook that platforms can implement for residency statistics |
| 2043 | accounting before entering a low power state. The ``pwr_domain_state`` field of |
| 2044 | ``state_info`` (first argument) can be inspected if stat accounting is done |
| 2045 | differently at CPU level versus higher levels. As an example, if the element at |
| 2046 | index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down |
| 2047 | state, special hardware logic may be programmed in order to keep track of the |
| 2048 | residency statistics. For higher levels (array indices > 0), the residency |
| 2049 | statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the |
| 2050 | default implementation will use PMF to capture timestamps. |
| 2051 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2052 | Function : plat_psci_stat_accounting_stop() [optional] |
| 2053 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2054 | |
| 2055 | :: |
| 2056 | |
| 2057 | Argument : const psci_power_state_t * |
| 2058 | Return : void |
| 2059 | |
| 2060 | This is an optional hook that platforms can implement for residency statistics |
| 2061 | accounting after exiting from a low power state. The ``pwr_domain_state`` field |
| 2062 | of ``state_info`` (first argument) can be inspected if stat accounting is done |
| 2063 | differently at CPU level versus higher levels. As an example, if the element at |
| 2064 | index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down |
| 2065 | state, special hardware logic may be programmed in order to keep track of the |
| 2066 | residency statistics. For higher levels (array indices > 0), the residency |
| 2067 | statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the |
| 2068 | default implementation will use PMF to capture timestamps. |
| 2069 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2070 | Function : plat_psci_stat_get_residency() [optional] |
| 2071 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2072 | |
| 2073 | :: |
| 2074 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 2075 | Argument : unsigned int, const psci_power_state_t *, unsigned int |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2076 | Return : u_register_t |
| 2077 | |
| 2078 | This is an optional interface that is is invoked after resuming from a low power |
| 2079 | state and provides the time spent resident in that low power state by the power |
| 2080 | domain at a particular power domain level. When a CPU wakes up from suspend, |
| 2081 | all its parent power domain levels are also woken up. The generic PSCI code |
| 2082 | invokes this function for each parent power domain that is resumed and it |
| 2083 | identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second |
| 2084 | argument) describes the low power state that the power domain has resumed from. |
| 2085 | The current CPU is the first CPU in the power domain to resume from the low |
| 2086 | power state and the ``last_cpu_idx`` (third parameter) is the index of the last |
| 2087 | CPU in the power domain to suspend and may be needed to calculate the residency |
| 2088 | for that power domain. |
| 2089 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2090 | Function : plat_get_target_pwr_state() [optional] |
| 2091 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2092 | |
| 2093 | :: |
| 2094 | |
| 2095 | Argument : unsigned int, const plat_local_state_t *, unsigned int |
| 2096 | Return : plat_local_state_t |
| 2097 | |
| 2098 | The PSCI generic code uses this function to let the platform participate in |
| 2099 | state coordination during a power management operation. The function is passed |
| 2100 | a pointer to an array of platform specific local power state ``states`` (second |
| 2101 | argument) which contains the requested power state for each CPU at a particular |
| 2102 | power domain level ``lvl`` (first argument) within the power domain. The function |
| 2103 | is expected to traverse this array of upto ``ncpus`` (third argument) and return |
| 2104 | a coordinated target power state by the comparing all the requested power |
| 2105 | states. The target power state should not be deeper than any of the requested |
| 2106 | power states. |
| 2107 | |
| 2108 | A weak definition of this API is provided by default wherein it assumes |
| 2109 | that the platform assigns a local state value in order of increasing depth |
| 2110 | of the power state i.e. for two power states X & Y, if X < Y |
| 2111 | then X represents a shallower power state than Y. As a result, the |
| 2112 | coordinated target local power state for a power domain will be the minimum |
| 2113 | of the requested local power state values. |
| 2114 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2115 | Function : plat_get_power_domain_tree_desc() [mandatory] |
| 2116 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2117 | |
| 2118 | :: |
| 2119 | |
| 2120 | Argument : void |
| 2121 | Return : const unsigned char * |
| 2122 | |
| 2123 | This function returns a pointer to the byte array containing the power domain |
| 2124 | topology tree description. The format and method to construct this array are |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2125 | described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI |
| 2126 | initialization code requires this array to be described by the platform, either |
| 2127 | statically or dynamically, to initialize the power domain topology tree. In case |
| 2128 | the array is populated dynamically, then plat_core_pos_by_mpidr() and |
| 2129 | plat_my_core_pos() should also be implemented suitably so that the topology tree |
| 2130 | description matches the CPU indices returned by these APIs. These APIs together |
| 2131 | form the platform interface for the PSCI topology framework. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2132 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2133 | Function : plat_setup_psci_ops() [mandatory] |
| 2134 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2135 | |
| 2136 | :: |
| 2137 | |
| 2138 | Argument : uintptr_t, const plat_psci_ops ** |
| 2139 | Return : int |
| 2140 | |
| 2141 | This function may execute with the MMU and data caches enabled if the platform |
| 2142 | port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only |
| 2143 | called by the primary CPU. |
| 2144 | |
| 2145 | This function is called by PSCI initialization code. Its purpose is to let |
| 2146 | the platform layer know about the warm boot entrypoint through the |
| 2147 | ``sec_entrypoint`` (first argument) and to export handler routines for |
| 2148 | platform-specific psci power management actions by populating the passed |
| 2149 | pointer with a pointer to BL31's private ``plat_psci_ops`` structure. |
| 2150 | |
| 2151 | A description of each member of this structure is given below. Please refer to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2152 | the Arm FVP specific implementation of these handlers in |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2153 | ``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2154 | platform wants to support, the associated operation or operations in this |
| 2155 | structure must be provided and implemented (Refer section 4 of |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2156 | :ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2157 | function in a platform port, the operation should be removed from this |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2158 | structure instead of providing an empty implementation. |
| 2159 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2160 | plat_psci_ops.cpu_standby() |
| 2161 | ........................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2162 | |
| 2163 | Perform the platform-specific actions to enter the standby state for a cpu |
| 2164 | indicated by the passed argument. This provides a fast path for CPU standby |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 2165 | wherein overheads of PSCI state management and lock acquisition is avoided. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2166 | For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, |
| 2167 | the suspend state type specified in the ``power-state`` parameter should be |
| 2168 | STANDBY and the target power domain level specified should be the CPU. The |
| 2169 | handler should put the CPU into a low power retention state (usually by |
| 2170 | issuing a wfi instruction) and ensure that it can be woken up from that |
| 2171 | state by a normal interrupt. The generic code expects the handler to succeed. |
| 2172 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2173 | plat_psci_ops.pwr_domain_on() |
| 2174 | ............................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2175 | |
| 2176 | Perform the platform specific actions to power on a CPU, specified |
| 2177 | by the ``MPIDR`` (first argument). The generic code expects the platform to |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2178 | return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2179 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2180 | plat_psci_ops.pwr_domain_off() |
| 2181 | .............................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2182 | |
| 2183 | Perform the platform specific actions to prepare to power off the calling CPU |
| 2184 | and its higher parent power domain levels as indicated by the ``target_state`` |
| 2185 | (first argument). It is called by the PSCI ``CPU_OFF`` API implementation. |
| 2186 | |
| 2187 | The ``target_state`` encodes the platform coordinated target local power states |
| 2188 | for the CPU power domain and its parent power domain levels. The handler |
| 2189 | needs to perform power management operation corresponding to the local state |
| 2190 | at each power level. |
| 2191 | |
| 2192 | For this handler, the local power state for the CPU power domain will be a |
| 2193 | power down state where as it could be either power down, retention or run state |
| 2194 | for the higher power domain levels depending on the result of state |
| 2195 | coordination. The generic code expects the handler to succeed. |
| 2196 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2197 | plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] |
| 2198 | ........................................................... |
Varun Wadekar | ae87f4b | 2017-07-10 16:02:05 -0700 | [diff] [blame] | 2199 | |
| 2200 | This optional function may be used as a performance optimization to replace |
| 2201 | or complement pwr_domain_suspend() on some platforms. Its calling semantics |
| 2202 | are identical to pwr_domain_suspend(), except the PSCI implementation only |
| 2203 | calls this function when suspending to a power down state, and it guarantees |
| 2204 | that data caches are enabled. |
| 2205 | |
| 2206 | When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches |
| 2207 | before calling pwr_domain_suspend(). If the target_state corresponds to a |
| 2208 | power down state and it is safe to perform some or all of the platform |
| 2209 | specific actions in that function with data caches enabled, it may be more |
| 2210 | efficient to move those actions to this function. When HW_ASSISTED_COHERENCY |
| 2211 | = 1, data caches remain enabled throughout, and so there is no advantage to |
| 2212 | moving platform specific actions to this function. |
| 2213 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2214 | plat_psci_ops.pwr_domain_suspend() |
| 2215 | .................................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2216 | |
| 2217 | Perform the platform specific actions to prepare to suspend the calling |
| 2218 | CPU and its higher parent power domain levels as indicated by the |
| 2219 | ``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` |
| 2220 | API implementation. |
| 2221 | |
| 2222 | The ``target_state`` has a similar meaning as described in |
| 2223 | the ``pwr_domain_off()`` operation. It encodes the platform coordinated |
| 2224 | target local power states for the CPU power domain and its parent |
| 2225 | power domain levels. The handler needs to perform power management operation |
| 2226 | corresponding to the local state at each power level. The generic code |
| 2227 | expects the handler to succeed. |
| 2228 | |
Douglas Raillard | a84996b | 2017-08-02 16:57:32 +0100 | [diff] [blame] | 2229 | The difference between turning a power domain off versus suspending it is that |
| 2230 | in the former case, the power domain is expected to re-initialize its state |
| 2231 | when it is next powered on (see ``pwr_domain_on_finish()``). In the latter |
| 2232 | case, the power domain is expected to save enough state so that it can resume |
| 2233 | execution by restoring this state when its powered on (see |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2234 | ``pwr_domain_suspend_finish()``). |
| 2235 | |
Douglas Raillard | a84996b | 2017-08-02 16:57:32 +0100 | [diff] [blame] | 2236 | When suspending a core, the platform can also choose to power off the GICv3 |
| 2237 | Redistributor and ITS through an implementation-defined sequence. To achieve |
| 2238 | this safely, the ITS context must be saved first. The architectural part is |
| 2239 | implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed |
| 2240 | sequence is implementation defined and it is therefore the responsibility of |
| 2241 | the platform code to implement the necessary sequence. Then the GIC |
| 2242 | Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. |
| 2243 | Powering off the Redistributor requires the implementation to support it and it |
| 2244 | is the responsibility of the platform code to execute the right implementation |
| 2245 | defined sequence. |
| 2246 | |
| 2247 | When a system suspend is requested, the platform can also make use of the |
| 2248 | ``gicv3_distif_save()`` helper to save the context of the GIC Distributor after |
| 2249 | it has saved the context of the Redistributors and ITS of all the cores in the |
| 2250 | system. The context of the Distributor can be large and may require it to be |
| 2251 | allocated in a special area if it cannot fit in the platform's global static |
| 2252 | data, for example in DRAM. The Distributor can then be powered down using an |
| 2253 | implementation-defined sequence. |
| 2254 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2255 | plat_psci_ops.pwr_domain_pwr_down_wfi() |
| 2256 | ....................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2257 | |
| 2258 | This is an optional function and, if implemented, is expected to perform |
| 2259 | platform specific actions including the ``wfi`` invocation which allows the |
| 2260 | CPU to powerdown. Since this function is invoked outside the PSCI locks, |
| 2261 | the actions performed in this hook must be local to the CPU or the platform |
| 2262 | must ensure that races between multiple CPUs cannot occur. |
| 2263 | |
| 2264 | The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` |
| 2265 | operation and it encodes the platform coordinated target local power states for |
| 2266 | the CPU power domain and its parent power domain levels. This function must |
| 2267 | not return back to the caller. |
| 2268 | |
| 2269 | If this function is not implemented by the platform, PSCI generic |
| 2270 | implementation invokes ``psci_power_down_wfi()`` for power down. |
| 2271 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2272 | plat_psci_ops.pwr_domain_on_finish() |
| 2273 | .................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2274 | |
| 2275 | This function is called by the PSCI implementation after the calling CPU is |
| 2276 | powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. |
| 2277 | It performs the platform-specific setup required to initialize enough state for |
| 2278 | this CPU to enter the normal world and also provide secure runtime firmware |
| 2279 | services. |
| 2280 | |
| 2281 | The ``target_state`` (first argument) is the prior state of the power domains |
| 2282 | immediately before the CPU was turned on. It indicates which power domains |
| 2283 | above the CPU might require initialization due to having previously been in |
| 2284 | low power states. The generic code expects the handler to succeed. |
| 2285 | |
Madhukar Pappireddy | 33bd514 | 2019-08-12 18:31:33 -0500 | [diff] [blame] | 2286 | plat_psci_ops.pwr_domain_on_finish_late() [optional] |
| 2287 | ........................................................... |
| 2288 | |
| 2289 | This optional function is called by the PSCI implementation after the calling |
| 2290 | CPU is fully powered on with respective data caches enabled. The calling CPU and |
| 2291 | the associated cluster are guaranteed to be participating in coherency. This |
| 2292 | function gives the flexibility to perform any platform-specific actions safely, |
| 2293 | such as initialization or modification of shared data structures, without the |
| 2294 | overhead of explicit cache maintainace operations. |
| 2295 | |
| 2296 | The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` |
| 2297 | operation. The generic code expects the handler to succeed. |
| 2298 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2299 | plat_psci_ops.pwr_domain_suspend_finish() |
| 2300 | ......................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2301 | |
| 2302 | This function is called by the PSCI implementation after the calling CPU is |
| 2303 | powered on and released from reset in response to an asynchronous wakeup |
| 2304 | event, for example a timer interrupt that was programmed by the CPU during the |
| 2305 | ``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific |
| 2306 | setup required to restore the saved state for this CPU to resume execution |
| 2307 | in the normal world and also provide secure runtime firmware services. |
| 2308 | |
| 2309 | The ``target_state`` (first argument) has a similar meaning as described in |
| 2310 | the ``pwr_domain_on_finish()`` operation. The generic code expects the platform |
| 2311 | to succeed. |
| 2312 | |
Douglas Raillard | a84996b | 2017-08-02 16:57:32 +0100 | [diff] [blame] | 2313 | If the Distributor, Redistributors or ITS have been powered off as part of a |
| 2314 | suspend, their context must be restored in this function in the reverse order |
| 2315 | to how they were saved during suspend sequence. |
| 2316 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2317 | plat_psci_ops.system_off() |
| 2318 | .......................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2319 | |
| 2320 | This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` |
| 2321 | call. It performs the platform-specific system poweroff sequence after |
| 2322 | notifying the Secure Payload Dispatcher. |
| 2323 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2324 | plat_psci_ops.system_reset() |
| 2325 | ............................ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2326 | |
| 2327 | This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` |
| 2328 | call. It performs the platform-specific system reset sequence after |
| 2329 | notifying the Secure Payload Dispatcher. |
| 2330 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2331 | plat_psci_ops.validate_power_state() |
| 2332 | .................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2333 | |
| 2334 | This function is called by the PSCI implementation during the ``CPU_SUSPEND`` |
| 2335 | call to validate the ``power_state`` parameter of the PSCI API and if valid, |
| 2336 | populate it in ``req_state`` (second argument) array as power domain level |
| 2337 | specific local states. If the ``power_state`` is invalid, the platform must |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2338 | return PSCI_E_INVALID_PARAMS as error, which is propagated back to the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2339 | normal world PSCI client. |
| 2340 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2341 | plat_psci_ops.validate_ns_entrypoint() |
| 2342 | ...................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2343 | |
| 2344 | This function is called by the PSCI implementation during the ``CPU_SUSPEND``, |
| 2345 | ``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` |
| 2346 | parameter passed by the normal world. If the ``entry_point`` is invalid, |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2347 | the platform must return PSCI_E_INVALID_ADDRESS as error, which is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2348 | propagated back to the normal world PSCI client. |
| 2349 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2350 | plat_psci_ops.get_sys_suspend_power_state() |
| 2351 | ........................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2352 | |
| 2353 | This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` |
| 2354 | call to get the ``req_state`` parameter from platform which encodes the power |
| 2355 | domain level specific local states to suspend to system affinity level. The |
| 2356 | ``req_state`` will be utilized to do the PSCI state coordination and |
| 2357 | ``pwr_domain_suspend()`` will be invoked with the coordinated target state to |
| 2358 | enter system suspend. |
| 2359 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2360 | plat_psci_ops.get_pwr_lvl_state_idx() |
| 2361 | ..................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2362 | |
| 2363 | This is an optional function and, if implemented, is invoked by the PSCI |
| 2364 | implementation to convert the ``local_state`` (first argument) at a specified |
| 2365 | ``pwr_lvl`` (second argument) to an index between 0 and |
| 2366 | ``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform |
| 2367 | supports more than two local power states at each power domain level, that is |
| 2368 | ``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these |
| 2369 | local power states. |
| 2370 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2371 | plat_psci_ops.translate_power_state_by_mpidr() |
| 2372 | .............................................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2373 | |
| 2374 | This is an optional function and, if implemented, verifies the ``power_state`` |
| 2375 | (second argument) parameter of the PSCI API corresponding to a target power |
| 2376 | domain. The target power domain is identified by using both ``MPIDR`` (first |
| 2377 | argument) and the power domain level encoded in ``power_state``. The power domain |
| 2378 | level specific local states are to be extracted from ``power_state`` and be |
| 2379 | populated in the ``output_state`` (third argument) array. The functionality |
| 2380 | is similar to the ``validate_power_state`` function described above and is |
| 2381 | envisaged to be used in case the validity of ``power_state`` depend on the |
| 2382 | targeted power domain. If the ``power_state`` is invalid for the targeted power |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2383 | domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2384 | function is not implemented, then the generic implementation relies on |
| 2385 | ``validate_power_state`` function to translate the ``power_state``. |
| 2386 | |
| 2387 | This function can also be used in case the platform wants to support local |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2388 | power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2389 | APIs as described in Section 5.18 of `PSCI`_. |
| 2390 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2391 | plat_psci_ops.get_node_hw_state() |
| 2392 | ................................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2393 | |
| 2394 | This is an optional function. If implemented this function is intended to return |
| 2395 | the power state of a node (identified by the first parameter, the ``MPIDR``) in |
| 2396 | the power domain topology (identified by the second parameter, ``power_level``), |
| 2397 | as retrieved from a power controller or equivalent component on the platform. |
| 2398 | Upon successful completion, the implementation must map and return the final |
| 2399 | status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it |
| 2400 | must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as |
| 2401 | appropriate. |
| 2402 | |
| 2403 | Implementations are not expected to handle ``power_levels`` greater than |
| 2404 | ``PLAT_MAX_PWR_LVL``. |
| 2405 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2406 | plat_psci_ops.system_reset2() |
| 2407 | ............................. |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2408 | |
| 2409 | This is an optional function. If implemented this function is |
| 2410 | called during the ``SYSTEM_RESET2`` call to perform a reset |
| 2411 | based on the first parameter ``reset_type`` as specified in |
| 2412 | `PSCI`_. The parameter ``cookie`` can be used to pass additional |
| 2413 | reset information. If the ``reset_type`` is not supported, the |
| 2414 | function must return ``PSCI_E_NOT_SUPPORTED``. For architectural |
| 2415 | resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` |
| 2416 | and vendor reset can return other PSCI error codes as defined |
| 2417 | in `PSCI`_. On success this function will not return. |
| 2418 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2419 | plat_psci_ops.write_mem_protect() |
| 2420 | ................................. |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2421 | |
| 2422 | This is an optional function. If implemented it enables or disables the |
| 2423 | ``MEM_PROTECT`` functionality based on the value of ``val``. |
| 2424 | A non-zero value enables ``MEM_PROTECT`` and a value of zero |
| 2425 | disables it. Upon encountering failures it must return a negative value |
| 2426 | and on success it must return 0. |
| 2427 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2428 | plat_psci_ops.read_mem_protect() |
| 2429 | ................................ |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2430 | |
| 2431 | This is an optional function. If implemented it returns the current |
| 2432 | state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering |
| 2433 | failures it must return a negative value and on success it must |
| 2434 | return 0. |
| 2435 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2436 | plat_psci_ops.mem_protect_chk() |
| 2437 | ............................... |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2438 | |
| 2439 | This is an optional function. If implemented it checks if a memory |
| 2440 | region defined by a base address ``base`` and with a size of ``length`` |
| 2441 | bytes is protected by ``MEM_PROTECT``. If the region is protected |
| 2442 | then it must return 0, otherwise it must return a negative number. |
| 2443 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2444 | .. _porting_guide_imf_in_bl31: |
| 2445 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2446 | Interrupt Management framework (in BL31) |
| 2447 | ---------------------------------------- |
| 2448 | |
| 2449 | BL31 implements an Interrupt Management Framework (IMF) to manage interrupts |
| 2450 | generated in either security state and targeted to EL1 or EL2 in the non-secure |
| 2451 | state or EL3/S-EL1 in the secure state. The design of this framework is |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2452 | described in the :ref:`Interrupt Management Framework` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2453 | |
| 2454 | A platform should export the following APIs to support the IMF. The following |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 2455 | text briefly describes each API and its implementation in Arm standard |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2456 | platforms. The API implementation depends upon the type of interrupt controller |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2457 | present in the platform. Arm standard platform layer supports both |
| 2458 | `Arm Generic Interrupt Controller version 2.0 (GICv2)`_ |
| 2459 | and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the |
| 2460 | FVP can be configured to use either GICv2 or GICv3 depending on the build flag |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 2461 | ``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more |
| 2462 | details). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2463 | |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 2464 | See also: `Interrupt Controller Abstraction APIs`__. |
| 2465 | |
Paul Beesley | ea22512 | 2019-02-11 17:54:45 +0000 | [diff] [blame] | 2466 | .. __: ../design/platform-interrupt-controller-API.rst |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 2467 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2468 | Function : plat_interrupt_type_to_line() [mandatory] |
| 2469 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2470 | |
| 2471 | :: |
| 2472 | |
| 2473 | Argument : uint32_t, uint32_t |
| 2474 | Return : uint32_t |
| 2475 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2476 | The Arm processor signals an interrupt exception either through the IRQ or FIQ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2477 | interrupt line. The specific line that is signaled depends on how the interrupt |
| 2478 | controller (IC) reports different interrupt types from an execution context in |
| 2479 | either security state. The IMF uses this API to determine which interrupt line |
| 2480 | the platform IC uses to signal each type of interrupt supported by the framework |
| 2481 | from a given security state. This API must be invoked at EL3. |
| 2482 | |
| 2483 | The first parameter will be one of the ``INTR_TYPE_*`` values (see |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2484 | :ref:`Interrupt Management Framework`) indicating the target type of the |
| 2485 | interrupt, the second parameter is the security state of the originating |
| 2486 | execution context. The return result is the bit position in the ``SCR_EL3`` |
| 2487 | register of the respective interrupt trap: IRQ=1, FIQ=2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2488 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2489 | In the case of Arm standard platforms using GICv2, S-EL1 interrupts are |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2490 | configured as FIQs and Non-secure interrupts as IRQs from either security |
| 2491 | state. |
| 2492 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2493 | In the case of Arm standard platforms using GICv3, the interrupt line to be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2494 | configured depends on the security state of the execution context when the |
| 2495 | interrupt is signalled and are as follows: |
| 2496 | |
| 2497 | - The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in |
| 2498 | NS-EL0/1/2 context. |
| 2499 | - The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ |
| 2500 | in the NS-EL0/1/2 context. |
| 2501 | - The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 |
| 2502 | context. |
| 2503 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2504 | Function : plat_ic_get_pending_interrupt_type() [mandatory] |
| 2505 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2506 | |
| 2507 | :: |
| 2508 | |
| 2509 | Argument : void |
| 2510 | Return : uint32_t |
| 2511 | |
| 2512 | This API returns the type of the highest priority pending interrupt at the |
| 2513 | platform IC. The IMF uses the interrupt type to retrieve the corresponding |
| 2514 | handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt |
| 2515 | pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, |
| 2516 | ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. |
| 2517 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2518 | In the case of Arm standard platforms using GICv2, the *Highest Priority |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2519 | Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of |
| 2520 | the pending interrupt. The type of interrupt depends upon the id value as |
| 2521 | follows. |
| 2522 | |
| 2523 | #. id < 1022 is reported as a S-EL1 interrupt |
| 2524 | #. id = 1022 is reported as a Non-secure interrupt. |
| 2525 | #. id = 1023 is reported as an invalid interrupt type. |
| 2526 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2527 | In the case of Arm standard platforms using GICv3, the system register |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2528 | ``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, |
| 2529 | is read to determine the id of the pending interrupt. The type of interrupt |
| 2530 | depends upon the id value as follows. |
| 2531 | |
| 2532 | #. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt |
| 2533 | #. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. |
| 2534 | #. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. |
| 2535 | #. All other interrupt id's are reported as EL3 interrupt. |
| 2536 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2537 | Function : plat_ic_get_pending_interrupt_id() [mandatory] |
| 2538 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2539 | |
| 2540 | :: |
| 2541 | |
| 2542 | Argument : void |
| 2543 | Return : uint32_t |
| 2544 | |
| 2545 | This API returns the id of the highest priority pending interrupt at the |
| 2546 | platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt |
| 2547 | pending. |
| 2548 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2549 | In the case of Arm standard platforms using GICv2, the *Highest Priority |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2550 | Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the |
| 2551 | pending interrupt. The id that is returned by API depends upon the value of |
| 2552 | the id read from the interrupt controller as follows. |
| 2553 | |
| 2554 | #. id < 1022. id is returned as is. |
| 2555 | #. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* |
| 2556 | (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. |
| 2557 | This id is returned by the API. |
| 2558 | #. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. |
| 2559 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2560 | In the case of Arm standard platforms using GICv3, if the API is invoked from |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2561 | EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt |
| 2562 | group 0 Register*, is read to determine the id of the pending interrupt. The id |
| 2563 | that is returned by API depends upon the value of the id read from the |
| 2564 | interrupt controller as follows. |
| 2565 | |
| 2566 | #. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. |
| 2567 | #. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system |
| 2568 | register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 |
| 2569 | Register* is read to determine the id of the group 1 interrupt. This id |
| 2570 | is returned by the API as long as it is a valid interrupt id |
| 2571 | #. If the id is any of the special interrupt identifiers, |
| 2572 | ``INTR_ID_UNAVAILABLE`` is returned. |
| 2573 | |
| 2574 | When the API invoked from S-EL1 for GICv3 systems, the id read from system |
| 2575 | register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2576 | Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2577 | ``INTR_ID_UNAVAILABLE`` is returned. |
| 2578 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2579 | Function : plat_ic_acknowledge_interrupt() [mandatory] |
| 2580 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2581 | |
| 2582 | :: |
| 2583 | |
| 2584 | Argument : void |
| 2585 | Return : uint32_t |
| 2586 | |
| 2587 | This API is used by the CPU to indicate to the platform IC that processing of |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 2588 | the highest pending interrupt has begun. It should return the raw, unmodified |
| 2589 | value obtained from the interrupt controller when acknowledging an interrupt. |
| 2590 | The actual interrupt number shall be extracted from this raw value using the API |
| 2591 | `plat_ic_get_interrupt_id()`__. |
| 2592 | |
Paul Beesley | ea22512 | 2019-02-11 17:54:45 +0000 | [diff] [blame] | 2593 | .. __: ../design/platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2594 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2595 | This function in Arm standard platforms using GICv2, reads the *Interrupt |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2596 | Acknowledge Register* (``GICC_IAR``). This changes the state of the highest |
| 2597 | priority pending interrupt from pending to active in the interrupt controller. |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 2598 | It returns the value read from the ``GICC_IAR``, unmodified. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2599 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2600 | In the case of Arm standard platforms using GICv3, if the API is invoked |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2601 | from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt |
| 2602 | Acknowledge Register group 0*. If the API is invoked from S-EL1, the function |
| 2603 | reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register |
| 2604 | group 1*. The read changes the state of the highest pending interrupt from |
| 2605 | pending to active in the interrupt controller. The value read is returned |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 2606 | unmodified. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2607 | |
| 2608 | The TSP uses this API to start processing of the secure physical timer |
| 2609 | interrupt. |
| 2610 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2611 | Function : plat_ic_end_of_interrupt() [mandatory] |
| 2612 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2613 | |
| 2614 | :: |
| 2615 | |
| 2616 | Argument : uint32_t |
| 2617 | Return : void |
| 2618 | |
| 2619 | This API is used by the CPU to indicate to the platform IC that processing of |
| 2620 | the interrupt corresponding to the id (passed as the parameter) has |
| 2621 | finished. The id should be the same as the id returned by the |
| 2622 | ``plat_ic_acknowledge_interrupt()`` API. |
| 2623 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2624 | Arm standard platforms write the id to the *End of Interrupt Register* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2625 | (``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` |
| 2626 | system register in case of GICv3 depending on where the API is invoked from, |
| 2627 | EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt |
| 2628 | controller. |
| 2629 | |
| 2630 | The TSP uses this API to finish processing of the secure physical timer |
| 2631 | interrupt. |
| 2632 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2633 | Function : plat_ic_get_interrupt_type() [mandatory] |
| 2634 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2635 | |
| 2636 | :: |
| 2637 | |
| 2638 | Argument : uint32_t |
| 2639 | Return : uint32_t |
| 2640 | |
| 2641 | This API returns the type of the interrupt id passed as the parameter. |
| 2642 | ``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid |
| 2643 | interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is |
| 2644 | returned depending upon how the interrupt has been configured by the platform |
| 2645 | IC. This API must be invoked at EL3. |
| 2646 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2647 | Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2648 | and Non-secure interrupts as Group1 interrupts. It reads the group value |
| 2649 | corresponding to the interrupt id from the relevant *Interrupt Group Register* |
| 2650 | (``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. |
| 2651 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2652 | In the case of Arm standard platforms using GICv3, both the *Interrupt Group |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2653 | Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* |
| 2654 | (``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured |
| 2655 | as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. |
| 2656 | |
| 2657 | Crash Reporting mechanism (in BL31) |
| 2658 | ----------------------------------- |
| 2659 | |
| 2660 | BL31 implements a crash reporting mechanism which prints the various registers |
Antonio Nino Diaz | 4bac045 | 2018-10-16 14:32:34 +0100 | [diff] [blame] | 2661 | of the CPU to enable quick crash analysis and debugging. This mechanism relies |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 2662 | on the platform implementing ``plat_crash_console_init``, |
Antonio Nino Diaz | 4bac045 | 2018-10-16 14:32:34 +0100 | [diff] [blame] | 2663 | ``plat_crash_console_putc`` and ``plat_crash_console_flush``. |
| 2664 | |
| 2665 | The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample |
| 2666 | implementation of all of them. Platforms may include this file to their |
| 2667 | makefiles in order to benefit from them. By default, they will cause the crash |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 2668 | output to be routed over the normal console infrastructure and get printed on |
| 2669 | consoles configured to output in crash state. ``console_set_scope()`` can be |
| 2670 | used to control whether a console is used for crash output. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 2671 | |
| 2672 | .. note:: |
| 2673 | Platforms are responsible for making sure that they only mark consoles for |
| 2674 | use in the crash scope that are able to support this, i.e. that are written |
| 2675 | in assembly and conform with the register clobber rules for putc() |
| 2676 | (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2677 | |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 2678 | In some cases (such as debugging very early crashes that happen before the |
| 2679 | normal boot console can be set up), platforms may want to control crash output |
Julius Werner | 1338c9c | 2018-11-19 14:25:55 -0800 | [diff] [blame] | 2680 | more explicitly. These platforms may instead provide custom implementations for |
| 2681 | these. They are executed outside of a C environment and without a stack. Many |
| 2682 | console drivers provide functions named ``console_xxx_core_init/putc/flush`` |
| 2683 | that are designed to be used by these functions. See Arm platforms (like juno) |
| 2684 | for an example of this. |
Antonio Nino Diaz | 4bac045 | 2018-10-16 14:32:34 +0100 | [diff] [blame] | 2685 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2686 | Function : plat_crash_console_init [mandatory] |
| 2687 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2688 | |
| 2689 | :: |
| 2690 | |
| 2691 | Argument : void |
| 2692 | Return : int |
| 2693 | |
| 2694 | This API is used by the crash reporting mechanism to initialize the crash |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 2695 | console. It must only use the general purpose registers x0 through x7 to do the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2696 | initialization and returns 1 on success. |
| 2697 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2698 | Function : plat_crash_console_putc [mandatory] |
| 2699 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2700 | |
| 2701 | :: |
| 2702 | |
| 2703 | Argument : int |
| 2704 | Return : int |
| 2705 | |
| 2706 | This API is used by the crash reporting mechanism to print a character on the |
| 2707 | designated crash console. It must only use general purpose registers x1 and |
| 2708 | x2 to do its work. The parameter and the return value are in general purpose |
| 2709 | register x0. |
| 2710 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2711 | Function : plat_crash_console_flush [mandatory] |
| 2712 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2713 | |
| 2714 | :: |
| 2715 | |
| 2716 | Argument : void |
| 2717 | Return : int |
| 2718 | |
| 2719 | This API is used by the crash reporting mechanism to force write of all buffered |
| 2720 | data on the designated crash console. It should only use general purpose |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 2721 | registers x0 through x5 to do its work. The return value is 0 on successful |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2722 | completion; otherwise the return value is -1. |
| 2723 | |
Jeenu Viswambharan | e34bf58 | 2018-10-12 08:48:36 +0100 | [diff] [blame] | 2724 | External Abort handling and RAS Support |
| 2725 | --------------------------------------- |
Jeenu Viswambharan | bf235bc | 2018-07-12 10:00:01 +0100 | [diff] [blame] | 2726 | |
| 2727 | Function : plat_ea_handler |
| 2728 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2729 | |
| 2730 | :: |
| 2731 | |
| 2732 | Argument : int |
| 2733 | Argument : uint64_t |
| 2734 | Argument : void * |
| 2735 | Argument : void * |
| 2736 | Argument : uint64_t |
| 2737 | Return : void |
| 2738 | |
| 2739 | This function is invoked by the RAS framework for the platform to handle an |
| 2740 | External Abort received at EL3. The intention of the function is to attempt to |
| 2741 | resolve the cause of External Abort and return; if that's not possible, to |
| 2742 | initiate orderly shutdown of the system. |
| 2743 | |
| 2744 | The first parameter (``int ea_reason``) indicates the reason for External Abort. |
| 2745 | Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. |
| 2746 | |
| 2747 | The second parameter (``uint64_t syndrome``) is the respective syndrome |
| 2748 | presented to EL3 after having received the External Abort. Depending on the |
| 2749 | nature of the abort (as can be inferred from the ``ea_reason`` parameter), this |
| 2750 | can be the content of either ``ESR_EL3`` or ``DISR_EL1``. |
| 2751 | |
| 2752 | The third parameter (``void *cookie``) is unused for now. The fourth parameter |
| 2753 | (``void *handle``) is a pointer to the preempted context. The fifth parameter |
| 2754 | (``uint64_t flags``) indicates the preempted security state. These parameters |
| 2755 | are received from the top-level exception handler. |
| 2756 | |
| 2757 | If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this |
| 2758 | function iterates through RAS handlers registered by the platform. If any of the |
| 2759 | RAS handlers resolve the External Abort, no further action is taken. |
| 2760 | |
| 2761 | If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers |
| 2762 | could resolve the External Abort, the default implementation prints an error |
| 2763 | message, and panics. |
| 2764 | |
| 2765 | Function : plat_handle_uncontainable_ea |
| 2766 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2767 | |
| 2768 | :: |
| 2769 | |
| 2770 | Argument : int |
| 2771 | Argument : uint64_t |
| 2772 | Return : void |
| 2773 | |
| 2774 | This function is invoked by the RAS framework when an External Abort of |
| 2775 | Uncontainable type is received at EL3. Due to the critical nature of |
| 2776 | Uncontainable errors, the intention of this function is to initiate orderly |
| 2777 | shutdown of the system, and is not expected to return. |
| 2778 | |
| 2779 | This function must be implemented in assembly. |
| 2780 | |
| 2781 | The first and second parameters are the same as that of ``plat_ea_handler``. |
| 2782 | |
| 2783 | The default implementation of this function calls |
| 2784 | ``report_unhandled_exception``. |
| 2785 | |
| 2786 | Function : plat_handle_double_fault |
| 2787 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2788 | |
| 2789 | :: |
| 2790 | |
| 2791 | Argument : int |
| 2792 | Argument : uint64_t |
| 2793 | Return : void |
| 2794 | |
| 2795 | This function is invoked by the RAS framework when another External Abort is |
| 2796 | received at EL3 while one is already being handled. I.e., a call to |
| 2797 | ``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of |
| 2798 | this function is to initiate orderly shutdown of the system, and is not expected |
| 2799 | recover or return. |
| 2800 | |
| 2801 | This function must be implemented in assembly. |
| 2802 | |
| 2803 | The first and second parameters are the same as that of ``plat_ea_handler``. |
| 2804 | |
| 2805 | The default implementation of this function calls |
| 2806 | ``report_unhandled_exception``. |
| 2807 | |
| 2808 | Function : plat_handle_el3_ea |
| 2809 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2810 | |
| 2811 | :: |
| 2812 | |
| 2813 | Return : void |
| 2814 | |
| 2815 | This function is invoked when an External Abort is received while executing in |
| 2816 | EL3. Due to its critical nature, the intention of this function is to initiate |
| 2817 | orderly shutdown of the system, and is not expected recover or return. |
| 2818 | |
| 2819 | This function must be implemented in assembly. |
| 2820 | |
| 2821 | The default implementation of this function calls |
| 2822 | ``report_unhandled_exception``. |
| 2823 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2824 | Build flags |
| 2825 | ----------- |
| 2826 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2827 | There are some build flags which can be defined by the platform to control |
| 2828 | inclusion or exclusion of certain BL stages from the FIP image. These flags |
| 2829 | need to be defined in the platform makefile which will get included by the |
| 2830 | build system. |
| 2831 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2832 | - **NEED_BL33** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2833 | By default, this flag is defined ``yes`` by the build system and ``BL33`` |
| 2834 | build option should be supplied as a build option. The platform has the |
| 2835 | option of excluding the BL33 image in the ``fip`` image by defining this flag |
| 2836 | to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` |
| 2837 | are used, this flag will be set to ``no`` automatically. |
| 2838 | |
Paul Beesley | 07f0a31 | 2019-05-16 13:33:18 +0100 | [diff] [blame] | 2839 | Platform include paths |
| 2840 | ---------------------- |
| 2841 | |
| 2842 | Platforms are allowed to add more include paths to be passed to the compiler. |
| 2843 | The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in |
| 2844 | particular for the file ``platform_def.h``. |
| 2845 | |
| 2846 | Example: |
| 2847 | |
| 2848 | .. code:: c |
| 2849 | |
| 2850 | PLAT_INCLUDES += -Iinclude/plat/myplat/include |
| 2851 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2852 | C Library |
| 2853 | --------- |
| 2854 | |
| 2855 | To avoid subtle toolchain behavioral dependencies, the header files provided |
| 2856 | by the compiler are not used. The software is built with the ``-nostdinc`` flag |
| 2857 | to ensure no headers are included from the toolchain inadvertently. Instead the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2858 | required headers are included in the TF-A source tree. The library only |
| 2859 | contains those C library definitions required by the local implementation. If |
| 2860 | more functionality is required, the needed library functions will need to be |
| 2861 | added to the local implementation. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2862 | |
Antonio Nino Diaz | cf0f805 | 2018-08-17 10:45:47 +0100 | [diff] [blame] | 2863 | Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have |
Paul Beesley | f2ec714 | 2019-10-04 16:17:46 +0000 | [diff] [blame] | 2864 | been written specifically for TF-A. Some implementation files have been obtained |
Antonio Nino Diaz | cf0f805 | 2018-08-17 10:45:47 +0100 | [diff] [blame] | 2865 | from `FreeBSD`_, others have been written specifically for TF-A as well. The |
| 2866 | files can be found in ``include/lib/libc`` and ``lib/libc``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2867 | |
Sandrine Bailleux | 6f0ecd7 | 2019-02-08 14:46:42 +0100 | [diff] [blame] | 2868 | SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources |
| 2869 | can be obtained from http://github.com/freebsd/freebsd. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2870 | |
| 2871 | Storage abstraction layer |
| 2872 | ------------------------- |
| 2873 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 2874 | In order to improve platform independence and portability a storage abstraction |
| 2875 | layer is used to load data from non-volatile platform storage. Currently |
| 2876 | storage access is only required by BL1 and BL2 phases and performed inside the |
| 2877 | ``load_image()`` function in ``bl_common.c``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2878 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 2879 | .. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2880 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2881 | It is mandatory to implement at least one storage driver. For the Arm |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2882 | development platforms the Firmware Image Package (FIP) driver is provided as |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 2883 | the default means to load data from storage (see :ref:`firmware_design_fip`). |
| 2884 | The storage layer is described in the header file |
| 2885 | ``include/drivers/io/io_storage.h``. The implementation of the common library is |
| 2886 | in ``drivers/io/io_storage.c`` and the driver files are located in |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2887 | ``drivers/io/``. |
| 2888 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 2889 | .. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml |
| 2890 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2891 | Each IO driver must provide ``io_dev_*`` structures, as described in |
| 2892 | ``drivers/io/io_driver.h``. These are returned via a mandatory registration |
| 2893 | function that is called on platform initialization. The semi-hosting driver |
| 2894 | implementation in ``io_semihosting.c`` can be used as an example. |
| 2895 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 2896 | Each platform should register devices and their drivers via the storage |
| 2897 | abstraction layer. These drivers then need to be initialized by bootloader |
| 2898 | phases as required in their respective ``blx_platform_setup()`` functions. |
| 2899 | |
| 2900 | .. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml |
| 2901 | |
| 2902 | The storage abstraction layer provides mechanisms (``io_dev_init()``) to |
| 2903 | initialize storage devices before IO operations are called. |
| 2904 | |
| 2905 | .. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml |
| 2906 | |
| 2907 | The basic operations supported by the layer |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2908 | include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. |
| 2909 | Drivers do not have to implement all operations, but each platform must |
| 2910 | provide at least one driver for a device capable of supporting generic |
| 2911 | operations such as loading a bootloader image. |
| 2912 | |
| 2913 | The current implementation only allows for known images to be loaded by the |
| 2914 | firmware. These images are specified by using their identifiers, as defined in |
Antonio Nino Diaz | 645feb4 | 2019-02-13 14:07:38 +0000 | [diff] [blame] | 2915 | ``include/plat/common/common_def.h`` (or a separate header file included from |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2916 | there). The platform layer (``plat_get_image_source()``) then returns a reference |
| 2917 | to a device and a driver-specific ``spec`` which will be understood by the driver |
| 2918 | to allow access to the image data. |
| 2919 | |
| 2920 | The layer is designed in such a way that is it possible to chain drivers with |
| 2921 | other drivers. For example, file-system drivers may be implemented on top of |
| 2922 | physical block devices, both represented by IO devices with corresponding |
| 2923 | drivers. In such a case, the file-system "binding" with the block device may |
| 2924 | be deferred until the file-system device is initialised. |
| 2925 | |
| 2926 | The abstraction currently depends on structures being statically allocated |
| 2927 | by the drivers and callers, as the system does not yet provide a means of |
| 2928 | dynamically allocating memory. This may also have the affect of limiting the |
| 2929 | amount of open resources per driver. |
| 2930 | |
| 2931 | -------------- |
| 2932 | |
Paul Beesley | 07f0a31 | 2019-05-16 13:33:18 +0100 | [diff] [blame] | 2933 | *Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2934 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2935 | .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2936 | .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2937 | .. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html |
Paul Beesley | 2437ddc | 2019-02-08 16:43:05 +0000 | [diff] [blame] | 2938 | .. _FreeBSD: https://www.freebsd.org |
Antonio Nino Diaz | cf0f805 | 2018-08-17 10:45:47 +0100 | [diff] [blame] | 2939 | .. _SCC: http://www.simple-cc.org/ |