Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Govindraj Raja | b6709b0 | 2023-02-21 17:43:55 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <platform_def.h> |
| 8 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | #include <arch.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 10 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <bl31/ea_handle.h> |
| 12 | #include <bl31/interrupt_mgmt.h> |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 13 | #include <bl31/sync_handle.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <common/runtime_svc.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 15 | #include <context.h> |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 16 | #include <el3_common_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <lib/el3_runtime/cpu_data.h> |
| 18 | #include <lib/smccc.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 19 | |
| 20 | .globl runtime_exceptions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 21 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 22 | .globl sync_exception_sp_el0 |
| 23 | .globl irq_sp_el0 |
| 24 | .globl fiq_sp_el0 |
| 25 | .globl serror_sp_el0 |
| 26 | |
| 27 | .globl sync_exception_sp_elx |
| 28 | .globl irq_sp_elx |
| 29 | .globl fiq_sp_elx |
| 30 | .globl serror_sp_elx |
| 31 | |
| 32 | .globl sync_exception_aarch64 |
| 33 | .globl irq_aarch64 |
| 34 | .globl fiq_aarch64 |
| 35 | .globl serror_aarch64 |
| 36 | |
| 37 | .globl sync_exception_aarch32 |
| 38 | .globl irq_aarch32 |
| 39 | .globl fiq_aarch32 |
| 40 | .globl serror_aarch32 |
| 41 | |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 42 | /* |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 43 | * Save LR and make x30 available as most of the routines in vector entry |
| 44 | * need a free register |
| 45 | */ |
| 46 | .macro save_x30 |
| 47 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 48 | .endm |
| 49 | |
| 50 | /* |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 51 | * Macro that prepares entry to EL3 upon taking an exception. |
| 52 | * |
Manish Pandey | d419e22 | 2023-02-13 12:39:17 +0000 | [diff] [blame] | 53 | * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an |
| 54 | * ESB instruction. When an error is thus synchronized, the handling is |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 55 | * delegated to platform EA handler. |
| 56 | * |
Manish Pandey | d419e22 | 2023-02-13 12:39:17 +0000 | [diff] [blame] | 57 | * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 58 | * a DSB, unmasks Asynchronous External Aborts and saves X30 before |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 59 | * setting the flag CTX_IS_IN_EL3. |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 60 | */ |
| 61 | .macro check_and_unmask_ea |
Manish Pandey | d419e22 | 2023-02-13 12:39:17 +0000 | [diff] [blame] | 62 | #if RAS_FFH_SUPPORT |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 63 | /* Synchronize pending External Aborts */ |
| 64 | esb |
| 65 | |
| 66 | /* Unmask the SError interrupt */ |
| 67 | msr daifclr, #DAIF_ABT_BIT |
| 68 | |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 69 | /* Check for SErrors synchronized by the ESB instruction */ |
| 70 | mrs x30, DISR_EL1 |
| 71 | tbz x30, #DISR_A_BIT, 1f |
| 72 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 73 | /* |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 74 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
Boyan Karatotev | ed85cf7 | 2022-12-06 09:03:42 +0000 | [diff] [blame] | 75 | * Also save PMCR_EL0 and set the PSTATE to a known state. |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 76 | */ |
Daniel Boulby | 95fb1aa | 2022-01-19 11:20:05 +0000 | [diff] [blame] | 77 | bl prepare_el3_entry |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 78 | |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 79 | bl handle_lower_el_ea_esb |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 80 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 81 | /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ |
| 82 | bl restore_gp_pmcr_pauth_regs |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 83 | 1: |
| 84 | #else |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 85 | /* |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 86 | * Note 1: The explicit DSB at the entry of various exception vectors |
| 87 | * for handling exceptions from lower ELs can inadvertently trigger an |
| 88 | * SError exception in EL3 due to pending asynchronous aborts in lower |
| 89 | * ELs. This will end up being handled by serror_sp_elx which will |
| 90 | * ultimately panic and die. |
| 91 | * The way to workaround is to update a flag to indicate if the exception |
| 92 | * truly came from EL3. This flag is allocated in the cpu_context |
| 93 | * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3" |
| 94 | * This is not a bullet proof solution to the problem at hand because |
| 95 | * we assume the instructions following "isb" that help to update the |
| 96 | * flag execute without causing further exceptions. |
| 97 | */ |
| 98 | |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 99 | /* |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 100 | * For SoCs which do not implement RAS, use DSB as a barrier to |
| 101 | * synchronize pending external aborts. |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 102 | */ |
| 103 | dsb sy |
| 104 | |
| 105 | /* Unmask the SError interrupt */ |
| 106 | msr daifclr, #DAIF_ABT_BIT |
| 107 | |
| 108 | /* Use ISB for the above unmask operation to take effect immediately */ |
| 109 | isb |
| 110 | |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 111 | /* Refer Note 1. */ |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 112 | mov x30, #1 |
| 113 | str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] |
| 114 | dmb sy |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 115 | #endif |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 116 | .endm |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 117 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 118 | /* --------------------------------------------------------------------- |
| 119 | * This macro handles Synchronous exceptions. |
| 120 | * Only SMC exceptions are supported. |
| 121 | * --------------------------------------------------------------------- |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 122 | */ |
| 123 | .macro handle_sync_exception |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 124 | #if ENABLE_RUNTIME_INSTRUMENTATION |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 125 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 126 | * Read the timestamp value and store it in per-cpu data. The value |
| 127 | * will be extracted from per-cpu data by the C level SMC handler and |
| 128 | * saved to the PMF timestamp region. |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 129 | */ |
| 130 | mrs x30, cntpct_el0 |
| 131 | str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 132 | mrs x29, tpidr_el3 |
| 133 | str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] |
| 134 | ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 135 | #endif |
| 136 | |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 137 | mrs x30, esr_el3 |
| 138 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 139 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 140 | /* Handle SMC exceptions separately from other synchronous exceptions */ |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 141 | cmp x30, #EC_AARCH32_SMC |
| 142 | b.eq smc_handler32 |
| 143 | |
| 144 | cmp x30, #EC_AARCH64_SMC |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 145 | b.eq sync_handler64 |
| 146 | |
| 147 | cmp x30, #EC_AARCH64_SYS |
| 148 | b.eq sync_handler64 |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 149 | |
Jeenu Viswambharan | e86a247 | 2018-07-05 15:24:45 +0100 | [diff] [blame] | 150 | /* Synchronous exceptions other than the above are assumed to be EA */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 151 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Manish Pandey | c918c18 | 2023-01-11 21:53:02 +0000 | [diff] [blame] | 152 | b handle_lower_el_sync_ea |
Achin Gupta | 9cf2bb7 | 2014-05-09 11:07:09 +0100 | [diff] [blame] | 153 | .endm |
| 154 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 155 | vector_base runtime_exceptions |
| 156 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 157 | /* --------------------------------------------------------------------- |
| 158 | * Current EL with SP_EL0 : 0x0 - 0x200 |
| 159 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 160 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 161 | vector_entry sync_exception_sp_el0 |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 162 | #ifdef MONITOR_TRAPS |
| 163 | stp x29, x30, [sp, #-16]! |
| 164 | |
| 165 | mrs x30, esr_el3 |
| 166 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 167 | |
| 168 | /* Check for BRK */ |
| 169 | cmp x30, #EC_BRK |
| 170 | b.eq brk_handler |
| 171 | |
| 172 | ldp x29, x30, [sp], #16 |
| 173 | #endif /* MONITOR_TRAPS */ |
| 174 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 175 | /* We don't expect any synchronous exceptions from EL3 */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 176 | b report_unhandled_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 177 | end_vector_entry sync_exception_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 178 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 179 | vector_entry irq_sp_el0 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 180 | /* |
| 181 | * EL3 code is non-reentrant. Any asynchronous exception is a serious |
| 182 | * error. Loop infinitely. |
| 183 | */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 184 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 185 | end_vector_entry irq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 186 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 187 | |
| 188 | vector_entry fiq_sp_el0 |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 189 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 190 | end_vector_entry fiq_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 191 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 192 | |
| 193 | vector_entry serror_sp_el0 |
Jeenu Viswambharan | 911fcc9 | 2018-07-06 16:50:06 +0100 | [diff] [blame] | 194 | no_ret plat_handle_el3_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 195 | end_vector_entry serror_sp_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 196 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 197 | /* --------------------------------------------------------------------- |
| 198 | * Current EL with SP_ELx: 0x200 - 0x400 |
| 199 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 200 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 201 | vector_entry sync_exception_sp_elx |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 202 | /* |
| 203 | * This exception will trigger if anything went wrong during a previous |
| 204 | * exception entry or exit or while handling an earlier unexpected |
| 205 | * synchronous exception. There is a high probability that SP_EL3 is |
| 206 | * corrupted. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 207 | */ |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 208 | b report_unhandled_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 209 | end_vector_entry sync_exception_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 210 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 211 | vector_entry irq_sp_elx |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 212 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 213 | end_vector_entry irq_sp_elx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 214 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 215 | vector_entry fiq_sp_elx |
Julius Werner | 67ebde7 | 2017-07-27 14:59:34 -0700 | [diff] [blame] | 216 | b report_unhandled_interrupt |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 217 | end_vector_entry fiq_sp_elx |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 218 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 219 | vector_entry serror_sp_elx |
Manish Pandey | d419e22 | 2023-02-13 12:39:17 +0000 | [diff] [blame] | 220 | #if !RAS_FFH_SUPPORT |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 221 | /* |
| 222 | * This will trigger if the exception was taken due to SError in EL3 or |
| 223 | * because of pending asynchronous external aborts from lower EL that got |
| 224 | * triggered due to explicit synchronization in EL3. Refer Note 1. |
| 225 | */ |
| 226 | /* Assumes SP_EL3 on entry */ |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 227 | save_x30 |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 228 | ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] |
| 229 | cbnz x30, 1f |
| 230 | |
| 231 | /* Handle asynchronous external abort from lower EL */ |
| 232 | b handle_lower_el_async_ea |
| 233 | 1: |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 234 | #endif |
Jeenu Viswambharan | 911fcc9 | 2018-07-06 16:50:06 +0100 | [diff] [blame] | 235 | no_ret plat_handle_el3_ea |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 236 | end_vector_entry serror_sp_elx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 237 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 238 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 239 | * Lower EL using AArch64 : 0x400 - 0x600 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 240 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 241 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 242 | vector_entry sync_exception_aarch64 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 243 | /* |
| 244 | * This exception vector will be the entry point for SMCs and traps |
| 245 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 246 | * to a valid cpu context where the general purpose and system register |
| 247 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 248 | */ |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 249 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 250 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 251 | check_and_unmask_ea |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 252 | handle_sync_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 253 | end_vector_entry sync_exception_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 254 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 255 | vector_entry irq_aarch64 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 256 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 257 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 258 | check_and_unmask_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 259 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 260 | end_vector_entry irq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 261 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 262 | vector_entry fiq_aarch64 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 263 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 264 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 265 | check_and_unmask_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 266 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 267 | end_vector_entry fiq_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 268 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 269 | vector_entry serror_aarch64 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 270 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 271 | apply_at_speculative_wa |
Manish Pandey | d419e22 | 2023-02-13 12:39:17 +0000 | [diff] [blame] | 272 | #if RAS_FFH_SUPPORT |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 273 | msr daifclr, #DAIF_ABT_BIT |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 274 | #else |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 275 | check_and_unmask_ea |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 276 | #endif |
Manish Pandey | c918c18 | 2023-01-11 21:53:02 +0000 | [diff] [blame] | 277 | b handle_lower_el_async_ea |
| 278 | |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 279 | end_vector_entry serror_aarch64 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 280 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 281 | /* --------------------------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 282 | * Lower EL using AArch32 : 0x600 - 0x800 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 283 | * --------------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 284 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 285 | vector_entry sync_exception_aarch32 |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 286 | /* |
| 287 | * This exception vector will be the entry point for SMCs and traps |
| 288 | * that are unhandled at lower ELs most commonly. SP_EL3 should point |
| 289 | * to a valid cpu context where the general purpose and system register |
| 290 | * state can be saved. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 291 | */ |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 292 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 293 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 294 | check_and_unmask_ea |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 295 | handle_sync_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 296 | end_vector_entry sync_exception_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 297 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 298 | vector_entry irq_aarch32 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 299 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 300 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 301 | check_and_unmask_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 302 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 303 | end_vector_entry irq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 304 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 305 | vector_entry fiq_aarch32 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 306 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 307 | apply_at_speculative_wa |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 308 | check_and_unmask_ea |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 309 | b handle_interrupt_exception |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 310 | end_vector_entry fiq_aarch32 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 311 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 312 | vector_entry serror_aarch32 |
Manish Pandey | 66a056e | 2023-01-11 21:41:07 +0000 | [diff] [blame] | 313 | save_x30 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 314 | apply_at_speculative_wa |
Manish Pandey | d419e22 | 2023-02-13 12:39:17 +0000 | [diff] [blame] | 315 | #if RAS_FFH_SUPPORT |
Jeenu Viswambharan | 96c7df0 | 2017-11-30 12:54:15 +0000 | [diff] [blame] | 316 | msr daifclr, #DAIF_ABT_BIT |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 317 | #else |
Manish Pandey | b3c6198 | 2023-01-06 13:38:03 +0000 | [diff] [blame] | 318 | check_and_unmask_ea |
Madhukar Pappireddy | fba2572 | 2020-07-24 03:27:12 -0500 | [diff] [blame] | 319 | #endif |
Manish Pandey | c918c18 | 2023-01-11 21:53:02 +0000 | [diff] [blame] | 320 | b handle_lower_el_async_ea |
| 321 | |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 322 | end_vector_entry serror_aarch32 |
Jeenu Viswambharan | a7934d6 | 2014-02-07 15:53:18 +0000 | [diff] [blame] | 323 | |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 324 | #ifdef MONITOR_TRAPS |
| 325 | .section .rodata.brk_string, "aS" |
| 326 | brk_location: |
| 327 | .asciz "Error at instruction 0x" |
| 328 | brk_message: |
| 329 | .asciz "Unexpected BRK instruction with value 0x" |
| 330 | #endif /* MONITOR_TRAPS */ |
| 331 | |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 332 | /* --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 333 | * The following code handles secure monitor calls. |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 334 | * Depending upon the execution state from where the SMC has been |
| 335 | * invoked, it frees some general purpose registers to perform the |
| 336 | * remaining tasks. They involve finding the runtime service handler |
| 337 | * that is the target of the SMC & switching to runtime stacks (SP_EL0) |
| 338 | * before calling the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 339 | * |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 340 | * Note that x30 has been explicitly saved and can be used here |
| 341 | * --------------------------------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 342 | */ |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 343 | func sync_exception_handler |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 344 | smc_handler32: |
| 345 | /* Check whether aarch32 issued an SMC64 */ |
| 346 | tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited |
| 347 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 348 | sync_handler64: |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 349 | /* NOTE: The code below must preserve x0-x4 */ |
| 350 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 351 | /* |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 352 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
Boyan Karatotev | ed85cf7 | 2022-12-06 09:03:42 +0000 | [diff] [blame] | 353 | * Also save PMCR_EL0 and set the PSTATE to a known state. |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 354 | */ |
Daniel Boulby | 95fb1aa | 2022-01-19 11:20:05 +0000 | [diff] [blame] | 355 | bl prepare_el3_entry |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 356 | |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 357 | #if ENABLE_PAUTH |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 358 | /* Load and program APIAKey firmware key */ |
| 359 | bl pauth_load_bl31_apiakey |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 360 | #endif |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 361 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 362 | /* |
| 363 | * Populate the parameters for the SMC handler. |
| 364 | * We already have x0-x4 in place. x5 will point to a cookie (not used |
| 365 | * now). x6 will point to the context structure (SP_EL3) and x7 will |
Dimitris Papastamos | 0415951 | 2018-01-22 11:53:04 +0000 | [diff] [blame] | 366 | * contain flags we need to pass to the handler. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 367 | */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 368 | mov x5, xzr |
| 369 | mov x6, sp |
| 370 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 371 | /* |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 372 | * Restore the saved C runtime stack value which will become the new |
| 373 | * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' |
| 374 | * structure prior to the last ERET from EL3. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 375 | */ |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 376 | ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 377 | |
| 378 | /* Switch to SP_EL0 */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 379 | msr spsel, #MODE_SP_EL0 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 380 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 381 | /* |
Manish Pandey | 70bbdbd | 2022-12-07 13:04:20 +0000 | [diff] [blame] | 382 | * Save the SPSR_EL3 and ELR_EL3 in case there is a world |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 383 | * switch during SMC handling. |
| 384 | * TODO: Revisit if all system registers can be saved later. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 385 | */ |
| 386 | mrs x16, spsr_el3 |
| 387 | mrs x17, elr_el3 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 388 | stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
Manish Pandey | 70bbdbd | 2022-12-07 13:04:20 +0000 | [diff] [blame] | 389 | |
| 390 | /* Load SCR_EL3 */ |
| 391 | mrs x18, scr_el3 |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 392 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 393 | /* check for system register traps */ |
| 394 | mrs x16, esr_el3 |
| 395 | ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 396 | cmp x17, #EC_AARCH64_SYS |
| 397 | b.eq sysreg_handler64 |
| 398 | |
Zelalem Aweke | 4d666ac | 2021-07-08 17:13:09 -0500 | [diff] [blame] | 399 | /* Clear flag register */ |
| 400 | mov x7, xzr |
| 401 | |
| 402 | #if ENABLE_RME |
| 403 | /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ |
| 404 | ubfx x7, x18, #SCR_NSE_SHIFT, 1 |
| 405 | |
| 406 | /* |
| 407 | * Shift copied SCR_EL3.NSE bit by 5 to create space for |
Olivier Deprez | 33dd845 | 2022-10-11 15:38:27 +0200 | [diff] [blame] | 408 | * SCR_EL3.NS bit. Bit 5 of the flag corresponds to |
Zelalem Aweke | 4d666ac | 2021-07-08 17:13:09 -0500 | [diff] [blame] | 409 | * the SCR_EL3.NSE bit. |
| 410 | */ |
| 411 | lsl x7, x7, #5 |
| 412 | #endif /* ENABLE_RME */ |
| 413 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 414 | /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ |
| 415 | bfi x7, x18, #0, #1 |
| 416 | |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 417 | mov sp, x12 |
| 418 | |
| 419 | /* |
| 420 | * Per SMCCC documentation, bits [23:17] must be zero for Fast |
| 421 | * SMCs. Other values are reserved for future use. Ensure that |
| 422 | * these bits are zeroes, if not report as unknown SMC. |
| 423 | */ |
| 424 | tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/ |
| 425 | tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT) |
| 426 | b.ne smc_unknown |
| 427 | |
Olivier Deprez | 33dd845 | 2022-10-11 15:38:27 +0200 | [diff] [blame] | 428 | /* |
| 429 | * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID |
| 430 | * passed through x0. Copy the SVE hint bit to flags and mask the |
| 431 | * bit in smc_fid passed to the standard service dispatcher. |
| 432 | * A service/dispatcher can retrieve the SVE hint bit state from |
| 433 | * flags using the appropriate helper. |
| 434 | */ |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 435 | 2: |
Olivier Deprez | 62cc109 | 2023-05-24 17:42:00 +0200 | [diff] [blame] | 436 | and x16, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) |
| 437 | orr x7, x7, x16 |
Olivier Deprez | 33dd845 | 2022-10-11 15:38:27 +0200 | [diff] [blame] | 438 | bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) |
| 439 | |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 440 | /* Get the unique owning entity number */ |
| 441 | ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH |
| 442 | ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH |
| 443 | orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH |
| 444 | |
| 445 | /* Load descriptor index from array of indices */ |
Madhukar Pappireddy | f4e6ea6 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 446 | adrp x14, rt_svc_descs_indices |
| 447 | add x14, x14, :lo12:rt_svc_descs_indices |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 448 | ldrb w15, [x14, x16] |
| 449 | |
| 450 | /* Any index greater than 127 is invalid. Check bit 7. */ |
| 451 | tbnz w15, 7, smc_unknown |
| 452 | |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 453 | /* |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 454 | * Get the descriptor using the index |
| 455 | * x11 = (base + off), w15 = index |
| 456 | * |
| 457 | * handler = (base + off) + (index << log2(size)) |
| 458 | */ |
| 459 | adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) |
| 460 | lsl w10, w15, #RT_SVC_SIZE_LOG2 |
| 461 | ldr x15, [x11, w10, uxtw] |
| 462 | |
| 463 | /* |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 464 | * Call the Secure Monitor Call handler and then drop directly into |
| 465 | * el3_exit() which will program any remaining architectural state |
| 466 | * prior to issuing the ERET to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 467 | */ |
| 468 | #if DEBUG |
| 469 | cbz x15, rt_svc_fw_critical_error |
| 470 | #endif |
| 471 | blr x15 |
| 472 | |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 473 | b el3_exit |
| 474 | |
| 475 | sysreg_handler64: |
| 476 | mov x0, x16 /* ESR_EL3, containing syndrome information */ |
| 477 | mov x1, x6 /* lower EL's context */ |
| 478 | mov x19, x6 /* save context pointer for after the call */ |
| 479 | mov sp, x12 /* EL3 runtime stack, as loaded above */ |
| 480 | |
| 481 | /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */ |
| 482 | bl handle_sysreg_trap |
| 483 | /* |
| 484 | * returns: |
| 485 | * -1: unhandled trap, panic |
| 486 | * 0: handled trap, return to the trapping instruction (repeating it) |
| 487 | * 1: handled trap, return to the next instruction |
| 488 | */ |
| 489 | |
| 490 | tst w0, w0 |
Govindraj Raja | b6709b0 | 2023-02-21 17:43:55 +0000 | [diff] [blame] | 491 | b.mi elx_panic /* negative return value: panic */ |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 492 | b.eq 1f /* zero: do not change ELR_EL3 */ |
| 493 | |
| 494 | /* advance the PC to continue after the instruction */ |
| 495 | ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] |
| 496 | add x1, x1, #4 |
| 497 | str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3] |
| 498 | 1: |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 499 | b el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 500 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 501 | smc_unknown: |
| 502 | /* |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 503 | * Unknown SMC call. Populate return value with SMC_UNK and call |
| 504 | * el3_exit() which will restore the remaining architectural state |
| 505 | * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET |
Jayanth Dodderi Chidanand | 3e474f7 | 2023-03-09 13:56:03 +0000 | [diff] [blame] | 506 | * to the desired lower EL. |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 507 | */ |
Antonio Nino Diaz | e4794b7 | 2018-02-14 14:22:29 +0000 | [diff] [blame] | 508 | mov x0, #SMC_UNK |
Madhukar Pappireddy | d87233a | 2019-05-08 15:41:41 -0500 | [diff] [blame] | 509 | str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 510 | b el3_exit |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 511 | |
| 512 | smc_prohibited: |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 513 | restore_ptw_el1_sys_regs |
| 514 | ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 515 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Antonio Nino Diaz | e4794b7 | 2018-02-14 14:22:29 +0000 | [diff] [blame] | 516 | mov x0, #SMC_UNK |
Anthony Steinhauser | 0f7e601 | 2020-01-07 15:44:06 -0800 | [diff] [blame] | 517 | exception_return |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 518 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 519 | #if DEBUG |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 520 | rt_svc_fw_critical_error: |
Douglas Raillard | 0980eed | 2016-11-09 17:48:27 +0000 | [diff] [blame] | 521 | /* Switch to SP_ELx */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 522 | msr spsel, #MODE_SP_ELX |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 523 | no_ret report_unhandled_exception |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 524 | #endif |
Andre Przywara | fa914d8 | 2022-11-21 17:04:10 +0000 | [diff] [blame] | 525 | endfunc sync_exception_handler |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 526 | |
| 527 | /* --------------------------------------------------------------------- |
Manish Pandey | 62040f4 | 2023-07-20 14:08:38 +0100 | [diff] [blame] | 528 | * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS |
| 529 | * interrupts. |
| 530 | * |
| 531 | * Note that x30 has been explicitly saved and can be used here |
| 532 | * --------------------------------------------------------------------- |
| 533 | */ |
| 534 | func handle_interrupt_exception |
| 535 | /* |
| 536 | * Save general purpose and ARMv8.3-PAuth registers (if enabled). |
| 537 | * Also save PMCR_EL0 and set the PSTATE to a known state. |
| 538 | */ |
| 539 | bl prepare_el3_entry |
| 540 | |
| 541 | #if ENABLE_PAUTH |
| 542 | /* Load and program APIAKey firmware key */ |
| 543 | bl pauth_load_bl31_apiakey |
| 544 | #endif |
| 545 | |
| 546 | /* Save the EL3 system registers needed to return from this exception */ |
| 547 | mrs x0, spsr_el3 |
| 548 | mrs x1, elr_el3 |
| 549 | stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 550 | |
| 551 | /* Switch to the runtime stack i.e. SP_EL0 */ |
| 552 | ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 553 | mov x20, sp |
| 554 | msr spsel, #MODE_SP_EL0 |
| 555 | mov sp, x2 |
| 556 | |
| 557 | /* |
| 558 | * Find out whether this is a valid interrupt type. |
| 559 | * If the interrupt controller reports a spurious interrupt then return |
| 560 | * to where we came from. |
| 561 | */ |
| 562 | bl plat_ic_get_pending_interrupt_type |
| 563 | cmp x0, #INTR_TYPE_INVAL |
| 564 | b.eq interrupt_exit |
| 565 | |
| 566 | /* |
| 567 | * Get the registered handler for this interrupt type. |
| 568 | * A NULL return value could be 'cause of the following conditions: |
| 569 | * |
| 570 | * a. An interrupt of a type was routed correctly but a handler for its |
| 571 | * type was not registered. |
| 572 | * |
| 573 | * b. An interrupt of a type was not routed correctly so a handler for |
| 574 | * its type was not registered. |
| 575 | * |
| 576 | * c. An interrupt of a type was routed correctly to EL3, but was |
| 577 | * deasserted before its pending state could be read. Another |
| 578 | * interrupt of a different type pended at the same time and its |
| 579 | * type was reported as pending instead. However, a handler for this |
| 580 | * type was not registered. |
| 581 | * |
| 582 | * a. and b. can only happen due to a programming error. The |
| 583 | * occurrence of c. could be beyond the control of Trusted Firmware. |
| 584 | * It makes sense to return from this exception instead of reporting an |
| 585 | * error. |
| 586 | */ |
| 587 | bl get_interrupt_type_handler |
| 588 | cbz x0, interrupt_exit |
| 589 | mov x21, x0 |
| 590 | |
| 591 | mov x0, #INTR_ID_UNAVAILABLE |
| 592 | |
| 593 | /* Set the current security state in the 'flags' parameter */ |
| 594 | mrs x2, scr_el3 |
| 595 | ubfx x1, x2, #0, #1 |
| 596 | |
| 597 | /* Restore the reference to the 'handle' i.e. SP_EL3 */ |
| 598 | mov x2, x20 |
| 599 | |
| 600 | /* x3 will point to a cookie (not used now) */ |
| 601 | mov x3, xzr |
| 602 | |
| 603 | /* Call the interrupt type handler */ |
| 604 | blr x21 |
| 605 | |
| 606 | interrupt_exit: |
| 607 | /* Return from exception, possibly in a different security state */ |
| 608 | b el3_exit |
| 609 | endfunc handle_interrupt_exception |
| 610 | |
| 611 | /* --------------------------------------------------------------------- |
Justin Chadwell | 83e0488 | 2019-08-20 11:01:52 +0100 | [diff] [blame] | 612 | * The following code handles exceptions caused by BRK instructions. |
| 613 | * Following a BRK instruction, the only real valid cause of action is |
| 614 | * to print some information and panic, as the code that caused it is |
| 615 | * likely in an inconsistent internal state. |
| 616 | * |
| 617 | * This is initially intended to be used in conjunction with |
| 618 | * __builtin_trap. |
| 619 | * --------------------------------------------------------------------- |
| 620 | */ |
| 621 | #ifdef MONITOR_TRAPS |
| 622 | func brk_handler |
| 623 | /* Extract the ISS */ |
| 624 | mrs x10, esr_el3 |
| 625 | ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH |
| 626 | |
| 627 | /* Ensure the console is initialized */ |
| 628 | bl plat_crash_console_init |
| 629 | |
| 630 | adr x4, brk_location |
| 631 | bl asm_print_str |
| 632 | mrs x4, elr_el3 |
| 633 | bl asm_print_hex |
| 634 | bl asm_print_newline |
| 635 | |
| 636 | adr x4, brk_message |
| 637 | bl asm_print_str |
| 638 | mov x4, x10 |
| 639 | mov x5, #28 |
| 640 | bl asm_print_hex_bits |
| 641 | bl asm_print_newline |
| 642 | |
| 643 | no_ret plat_panic_handler |
| 644 | endfunc brk_handler |
| 645 | #endif /* MONITOR_TRAPS */ |