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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Govindraj Rajab6709b02023-02-21 17:43:55 +00002 * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
Andre Przywarafa914d82022-11-21 17:04:10 +000013#include <bl31/sync_handle.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010015#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010016#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/el3_runtime/cpu_data.h>
18#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
20 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010021
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000022 .globl sync_exception_sp_el0
23 .globl irq_sp_el0
24 .globl fiq_sp_el0
25 .globl serror_sp_el0
26
27 .globl sync_exception_sp_elx
28 .globl irq_sp_elx
29 .globl fiq_sp_elx
30 .globl serror_sp_elx
31
32 .globl sync_exception_aarch64
33 .globl irq_aarch64
34 .globl fiq_aarch64
35 .globl serror_aarch64
36
37 .globl sync_exception_aarch32
38 .globl irq_aarch32
39 .globl fiq_aarch32
40 .globl serror_aarch32
41
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000042 /*
Manish Pandey66a056e2023-01-11 21:41:07 +000043 * Save LR and make x30 available as most of the routines in vector entry
44 * need a free register
45 */
46 .macro save_x30
47 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
48 .endm
49
50 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010051 * Macro that prepares entry to EL3 upon taking an exception.
52 *
Manish Pandeyd419e222023-02-13 12:39:17 +000053 * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an
54 * ESB instruction. When an error is thus synchronized, the handling is
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010055 * delegated to platform EA handler.
56 *
Manish Pandeyd419e222023-02-13 12:39:17 +000057 * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +000058 * a DSB, unmasks Asynchronous External Aborts and saves X30 before
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050059 * setting the flag CTX_IS_IN_EL3.
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010060 */
61 .macro check_and_unmask_ea
Manish Pandeyd419e222023-02-13 12:39:17 +000062#if RAS_FFH_SUPPORT
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010063 /* Synchronize pending External Aborts */
64 esb
65
66 /* Unmask the SError interrupt */
67 msr daifclr, #DAIF_ABT_BIT
68
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010069 /* Check for SErrors synchronized by the ESB instruction */
70 mrs x30, DISR_EL1
71 tbz x30, #DISR_A_BIT, 1f
72
Alexei Fedorov503bbf32019-08-13 15:17:53 +010073 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010074 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
Boyan Karatoteved85cf72022-12-06 09:03:42 +000075 * Also save PMCR_EL0 and set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010076 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +000077 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +010078
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010079 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010080
Alexei Fedorovf41355c2019-09-13 14:11:59 +010081 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
82 bl restore_gp_pmcr_pauth_regs
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100831:
84#else
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050085 /*
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050086 * Note 1: The explicit DSB at the entry of various exception vectors
87 * for handling exceptions from lower ELs can inadvertently trigger an
88 * SError exception in EL3 due to pending asynchronous aborts in lower
89 * ELs. This will end up being handled by serror_sp_elx which will
90 * ultimately panic and die.
91 * The way to workaround is to update a flag to indicate if the exception
92 * truly came from EL3. This flag is allocated in the cpu_context
93 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
94 * This is not a bullet proof solution to the problem at hand because
95 * we assume the instructions following "isb" that help to update the
96 * flag execute without causing further exceptions.
97 */
98
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050099 /*
Manish Pandeyb3c61982023-01-06 13:38:03 +0000100 * For SoCs which do not implement RAS, use DSB as a barrier to
101 * synchronize pending external aborts.
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500102 */
103 dsb sy
104
105 /* Unmask the SError interrupt */
106 msr daifclr, #DAIF_ABT_BIT
107
108 /* Use ISB for the above unmask operation to take effect immediately */
109 isb
110
Manish Pandey66a056e2023-01-11 21:41:07 +0000111 /* Refer Note 1. */
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500112 mov x30, #1
113 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
114 dmb sy
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500115#endif
Manish Pandeyb3c61982023-01-06 13:38:03 +0000116 .endm
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500117
Douglas Raillard0980eed2016-11-09 17:48:27 +0000118 /* ---------------------------------------------------------------------
119 * This macro handles Synchronous exceptions.
120 * Only SMC exceptions are supported.
121 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100122 */
123 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +0100124#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +0100125 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000126 * Read the timestamp value and store it in per-cpu data. The value
127 * will be extracted from per-cpu data by the C level SMC handler and
128 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +0100129 */
130 mrs x30, cntpct_el0
131 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
132 mrs x29, tpidr_el3
133 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
134 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
135#endif
136
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100137 mrs x30, esr_el3
138 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
139
Douglas Raillard0980eed2016-11-09 17:48:27 +0000140 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100141 cmp x30, #EC_AARCH32_SMC
142 b.eq smc_handler32
143
144 cmp x30, #EC_AARCH64_SMC
Andre Przywarafa914d82022-11-21 17:04:10 +0000145 b.eq sync_handler64
146
147 cmp x30, #EC_AARCH64_SYS
148 b.eq sync_handler64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100149
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100150 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700151 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Manish Pandeyc918c182023-01-11 21:53:02 +0000152 b handle_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100153 .endm
154
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100155vector_base runtime_exceptions
156
Douglas Raillard0980eed2016-11-09 17:48:27 +0000157 /* ---------------------------------------------------------------------
158 * Current EL with SP_EL0 : 0x0 - 0x200
159 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100161vector_entry sync_exception_sp_el0
Justin Chadwell83e04882019-08-20 11:01:52 +0100162#ifdef MONITOR_TRAPS
163 stp x29, x30, [sp, #-16]!
164
165 mrs x30, esr_el3
166 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
167
168 /* Check for BRK */
169 cmp x30, #EC_BRK
170 b.eq brk_handler
171
172 ldp x29, x30, [sp], #16
173#endif /* MONITOR_TRAPS */
174
Douglas Raillard0980eed2016-11-09 17:48:27 +0000175 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700176 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100177end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100179vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000180 /*
181 * EL3 code is non-reentrant. Any asynchronous exception is a serious
182 * error. Loop infinitely.
183 */
Julius Werner67ebde72017-07-27 14:59:34 -0700184 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100185end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100186
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100187
188vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700189 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100190end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100192
193vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100194 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100195end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196
Douglas Raillard0980eed2016-11-09 17:48:27 +0000197 /* ---------------------------------------------------------------------
198 * Current EL with SP_ELx: 0x200 - 0x400
199 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100201vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000202 /*
203 * This exception will trigger if anything went wrong during a previous
204 * exception entry or exit or while handling an earlier unexpected
205 * synchronous exception. There is a high probability that SP_EL3 is
206 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000207 */
Julius Werner67ebde72017-07-27 14:59:34 -0700208 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100209end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100211vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700212 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100213end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000214
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100215vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700216 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100217end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000218
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100219vector_entry serror_sp_elx
Manish Pandeyd419e222023-02-13 12:39:17 +0000220#if !RAS_FFH_SUPPORT
Manish Pandeyb3c61982023-01-06 13:38:03 +0000221 /*
222 * This will trigger if the exception was taken due to SError in EL3 or
223 * because of pending asynchronous external aborts from lower EL that got
224 * triggered due to explicit synchronization in EL3. Refer Note 1.
225 */
226 /* Assumes SP_EL3 on entry */
Manish Pandey66a056e2023-01-11 21:41:07 +0000227 save_x30
Manish Pandeyb3c61982023-01-06 13:38:03 +0000228 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
229 cbnz x30, 1f
230
231 /* Handle asynchronous external abort from lower EL */
232 b handle_lower_el_async_ea
2331:
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500234#endif
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100235 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100236end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100237
Douglas Raillard0980eed2016-11-09 17:48:27 +0000238 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100239 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000240 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100242vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000243 /*
244 * This exception vector will be the entry point for SMCs and traps
245 * that are unhandled at lower ELs most commonly. SP_EL3 should point
246 * to a valid cpu context where the general purpose and system register
247 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000248 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000249 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100250 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100251 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000252 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100253end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100255vector_entry irq_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000256 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100257 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100258 check_and_unmask_ea
Manish Pandey62040f42023-07-20 14:08:38 +0100259 b handle_interrupt_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100260end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100261
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100262vector_entry fiq_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000263 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100264 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100265 check_and_unmask_ea
Manish Pandey62040f42023-07-20 14:08:38 +0100266 b handle_interrupt_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100267end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100269vector_entry serror_aarch64
Manish Pandey66a056e2023-01-11 21:41:07 +0000270 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100271 apply_at_speculative_wa
Manish Pandeyd419e222023-02-13 12:39:17 +0000272#if RAS_FFH_SUPPORT
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000273 msr daifclr, #DAIF_ABT_BIT
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500274#else
Manish Pandeyb3c61982023-01-06 13:38:03 +0000275 check_and_unmask_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500276#endif
Manish Pandeyc918c182023-01-11 21:53:02 +0000277 b handle_lower_el_async_ea
278
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100279end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280
Douglas Raillard0980eed2016-11-09 17:48:27 +0000281 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100282 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000283 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100284 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100285vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000286 /*
287 * This exception vector will be the entry point for SMCs and traps
288 * that are unhandled at lower ELs most commonly. SP_EL3 should point
289 * to a valid cpu context where the general purpose and system register
290 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000291 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000292 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100293 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100294 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000295 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100296end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100297
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100298vector_entry irq_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000299 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100300 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100301 check_and_unmask_ea
Manish Pandey62040f42023-07-20 14:08:38 +0100302 b handle_interrupt_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100303end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100305vector_entry fiq_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000306 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100307 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100308 check_and_unmask_ea
Manish Pandey62040f42023-07-20 14:08:38 +0100309 b handle_interrupt_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100310end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100312vector_entry serror_aarch32
Manish Pandey66a056e2023-01-11 21:41:07 +0000313 save_x30
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100314 apply_at_speculative_wa
Manish Pandeyd419e222023-02-13 12:39:17 +0000315#if RAS_FFH_SUPPORT
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000316 msr daifclr, #DAIF_ABT_BIT
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500317#else
Manish Pandeyb3c61982023-01-06 13:38:03 +0000318 check_and_unmask_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500319#endif
Manish Pandeyc918c182023-01-11 21:53:02 +0000320 b handle_lower_el_async_ea
321
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100322end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000323
Justin Chadwell83e04882019-08-20 11:01:52 +0100324#ifdef MONITOR_TRAPS
325 .section .rodata.brk_string, "aS"
326brk_location:
327 .asciz "Error at instruction 0x"
328brk_message:
329 .asciz "Unexpected BRK instruction with value 0x"
330#endif /* MONITOR_TRAPS */
331
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100332 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000333 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000334 * Depending upon the execution state from where the SMC has been
335 * invoked, it frees some general purpose registers to perform the
336 * remaining tasks. They involve finding the runtime service handler
337 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
338 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000339 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000340 * Note that x30 has been explicitly saved and can be used here
341 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000342 */
Andre Przywarafa914d82022-11-21 17:04:10 +0000343func sync_exception_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000344smc_handler32:
345 /* Check whether aarch32 issued an SMC64 */
346 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
347
Andre Przywarafa914d82022-11-21 17:04:10 +0000348sync_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000349 /* NOTE: The code below must preserve x0-x4 */
350
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100351 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100352 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
Boyan Karatoteved85cf72022-12-06 09:03:42 +0000353 * Also save PMCR_EL0 and set the PSTATE to a known state.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100354 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000355 bl prepare_el3_entry
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100356
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000357#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100358 /* Load and program APIAKey firmware key */
359 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000360#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000361
Douglas Raillard0980eed2016-11-09 17:48:27 +0000362 /*
363 * Populate the parameters for the SMC handler.
364 * We already have x0-x4 in place. x5 will point to a cookie (not used
365 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000366 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000367 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000368 mov x5, xzr
369 mov x6, sp
370
Douglas Raillard0980eed2016-11-09 17:48:27 +0000371 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100372 * Restore the saved C runtime stack value which will become the new
373 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
374 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000375 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100376 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
377
378 /* Switch to SP_EL0 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100379 msr spsel, #MODE_SP_EL0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000380
Douglas Raillard0980eed2016-11-09 17:48:27 +0000381 /*
Manish Pandey70bbdbd2022-12-07 13:04:20 +0000382 * Save the SPSR_EL3 and ELR_EL3 in case there is a world
Douglas Raillard0980eed2016-11-09 17:48:27 +0000383 * switch during SMC handling.
384 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000385 */
386 mrs x16, spsr_el3
387 mrs x17, elr_el3
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000388 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Manish Pandey70bbdbd2022-12-07 13:04:20 +0000389
390 /* Load SCR_EL3 */
391 mrs x18, scr_el3
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000392
Andre Przywarafa914d82022-11-21 17:04:10 +0000393 /* check for system register traps */
394 mrs x16, esr_el3
395 ubfx x17, x16, #ESR_EC_SHIFT, #ESR_EC_LENGTH
396 cmp x17, #EC_AARCH64_SYS
397 b.eq sysreg_handler64
398
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500399 /* Clear flag register */
400 mov x7, xzr
401
402#if ENABLE_RME
403 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
404 ubfx x7, x18, #SCR_NSE_SHIFT, 1
405
406 /*
407 * Shift copied SCR_EL3.NSE bit by 5 to create space for
Olivier Deprez33dd8452022-10-11 15:38:27 +0200408 * SCR_EL3.NS bit. Bit 5 of the flag corresponds to
Zelalem Aweke4d666ac2021-07-08 17:13:09 -0500409 * the SCR_EL3.NSE bit.
410 */
411 lsl x7, x7, #5
412#endif /* ENABLE_RME */
413
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000414 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
415 bfi x7, x18, #0, #1
416
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +0000417 mov sp, x12
418
419 /*
420 * Per SMCCC documentation, bits [23:17] must be zero for Fast
421 * SMCs. Other values are reserved for future use. Ensure that
422 * these bits are zeroes, if not report as unknown SMC.
423 */
424 tbz x0, #FUNCID_TYPE_SHIFT, 2f /* Skip check if its a Yield Call*/
425 tst x0, #(FUNCID_FC_RESERVED_MASK << FUNCID_FC_RESERVED_SHIFT)
426 b.ne smc_unknown
427
Olivier Deprez33dd8452022-10-11 15:38:27 +0200428 /*
429 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID
430 * passed through x0. Copy the SVE hint bit to flags and mask the
431 * bit in smc_fid passed to the standard service dispatcher.
432 * A service/dispatcher can retrieve the SVE hint bit state from
433 * flags using the appropriate helper.
434 */
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +00004352:
Olivier Deprez62cc1092023-05-24 17:42:00 +0200436 and x16, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
437 orr x7, x7, x16
Olivier Deprez33dd8452022-10-11 15:38:27 +0200438 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
439
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500440 /* Get the unique owning entity number */
441 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
442 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
443 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
444
445 /* Load descriptor index from array of indices */
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -0600446 adrp x14, rt_svc_descs_indices
447 add x14, x14, :lo12:rt_svc_descs_indices
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500448 ldrb w15, [x14, x16]
449
450 /* Any index greater than 127 is invalid. Check bit 7. */
451 tbnz w15, 7, smc_unknown
452
Douglas Raillard0980eed2016-11-09 17:48:27 +0000453 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500454 * Get the descriptor using the index
455 * x11 = (base + off), w15 = index
456 *
457 * handler = (base + off) + (index << log2(size))
458 */
459 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
460 lsl w10, w15, #RT_SVC_SIZE_LOG2
461 ldr x15, [x11, w10, uxtw]
462
463 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000464 * Call the Secure Monitor Call handler and then drop directly into
465 * el3_exit() which will program any remaining architectural state
466 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000467 */
468#if DEBUG
469 cbz x15, rt_svc_fw_critical_error
470#endif
471 blr x15
472
Andre Przywarafa914d82022-11-21 17:04:10 +0000473 b el3_exit
474
475sysreg_handler64:
476 mov x0, x16 /* ESR_EL3, containing syndrome information */
477 mov x1, x6 /* lower EL's context */
478 mov x19, x6 /* save context pointer for after the call */
479 mov sp, x12 /* EL3 runtime stack, as loaded above */
480
481 /* int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx); */
482 bl handle_sysreg_trap
483 /*
484 * returns:
485 * -1: unhandled trap, panic
486 * 0: handled trap, return to the trapping instruction (repeating it)
487 * 1: handled trap, return to the next instruction
488 */
489
490 tst w0, w0
Govindraj Rajab6709b02023-02-21 17:43:55 +0000491 b.mi elx_panic /* negative return value: panic */
Andre Przywarafa914d82022-11-21 17:04:10 +0000492 b.eq 1f /* zero: do not change ELR_EL3 */
493
494 /* advance the PC to continue after the instruction */
495 ldr x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
496 add x1, x1, #4
497 str x1, [x19, #CTX_EL3STATE_OFFSET + CTX_ELR_EL3]
4981:
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100499 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100500
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000501smc_unknown:
502 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500503 * Unknown SMC call. Populate return value with SMC_UNK and call
504 * el3_exit() which will restore the remaining architectural state
505 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
Jayanth Dodderi Chidanand3e474f72023-03-09 13:56:03 +0000506 * to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000507 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000508 mov x0, #SMC_UNK
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500509 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
510 b el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000511
512smc_prohibited:
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100513 restore_ptw_el1_sys_regs
514 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100515 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000516 mov x0, #SMC_UNK
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800517 exception_return
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000518
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100519#if DEBUG
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000520rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000521 /* Switch to SP_ELx */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100522 msr spsel, #MODE_SP_ELX
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000523 no_ret report_unhandled_exception
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100524#endif
Andre Przywarafa914d82022-11-21 17:04:10 +0000525endfunc sync_exception_handler
Justin Chadwell83e04882019-08-20 11:01:52 +0100526
527 /* ---------------------------------------------------------------------
Manish Pandey62040f42023-07-20 14:08:38 +0100528 * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
529 * interrupts.
530 *
531 * Note that x30 has been explicitly saved and can be used here
532 * ---------------------------------------------------------------------
533 */
534func handle_interrupt_exception
535 /*
536 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
537 * Also save PMCR_EL0 and set the PSTATE to a known state.
538 */
539 bl prepare_el3_entry
540
541#if ENABLE_PAUTH
542 /* Load and program APIAKey firmware key */
543 bl pauth_load_bl31_apiakey
544#endif
545
546 /* Save the EL3 system registers needed to return from this exception */
547 mrs x0, spsr_el3
548 mrs x1, elr_el3
549 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
550
551 /* Switch to the runtime stack i.e. SP_EL0 */
552 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
553 mov x20, sp
554 msr spsel, #MODE_SP_EL0
555 mov sp, x2
556
557 /*
558 * Find out whether this is a valid interrupt type.
559 * If the interrupt controller reports a spurious interrupt then return
560 * to where we came from.
561 */
562 bl plat_ic_get_pending_interrupt_type
563 cmp x0, #INTR_TYPE_INVAL
564 b.eq interrupt_exit
565
566 /*
567 * Get the registered handler for this interrupt type.
568 * A NULL return value could be 'cause of the following conditions:
569 *
570 * a. An interrupt of a type was routed correctly but a handler for its
571 * type was not registered.
572 *
573 * b. An interrupt of a type was not routed correctly so a handler for
574 * its type was not registered.
575 *
576 * c. An interrupt of a type was routed correctly to EL3, but was
577 * deasserted before its pending state could be read. Another
578 * interrupt of a different type pended at the same time and its
579 * type was reported as pending instead. However, a handler for this
580 * type was not registered.
581 *
582 * a. and b. can only happen due to a programming error. The
583 * occurrence of c. could be beyond the control of Trusted Firmware.
584 * It makes sense to return from this exception instead of reporting an
585 * error.
586 */
587 bl get_interrupt_type_handler
588 cbz x0, interrupt_exit
589 mov x21, x0
590
591 mov x0, #INTR_ID_UNAVAILABLE
592
593 /* Set the current security state in the 'flags' parameter */
594 mrs x2, scr_el3
595 ubfx x1, x2, #0, #1
596
597 /* Restore the reference to the 'handle' i.e. SP_EL3 */
598 mov x2, x20
599
600 /* x3 will point to a cookie (not used now) */
601 mov x3, xzr
602
603 /* Call the interrupt type handler */
604 blr x21
605
606interrupt_exit:
607 /* Return from exception, possibly in a different security state */
608 b el3_exit
609endfunc handle_interrupt_exception
610
611 /* ---------------------------------------------------------------------
Justin Chadwell83e04882019-08-20 11:01:52 +0100612 * The following code handles exceptions caused by BRK instructions.
613 * Following a BRK instruction, the only real valid cause of action is
614 * to print some information and panic, as the code that caused it is
615 * likely in an inconsistent internal state.
616 *
617 * This is initially intended to be used in conjunction with
618 * __builtin_trap.
619 * ---------------------------------------------------------------------
620 */
621#ifdef MONITOR_TRAPS
622func brk_handler
623 /* Extract the ISS */
624 mrs x10, esr_el3
625 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
626
627 /* Ensure the console is initialized */
628 bl plat_crash_console_init
629
630 adr x4, brk_location
631 bl asm_print_str
632 mrs x4, elr_el3
633 bl asm_print_hex
634 bl asm_print_newline
635
636 adr x4, brk_message
637 bl asm_print_str
638 mov x4, x10
639 mov x5, #28
640 bl asm_print_hex_bits
641 bl asm_print_newline
642
643 no_ret plat_panic_handler
644endfunc brk_handler
645#endif /* MONITOR_TRAPS */